Lines Matching refs:MI
74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo,
96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo,
100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const;
109 unsigned getEncodingType(const MCInst &MI) const;
112 unsigned getEncodingBytes(const MCInst &MI) const;
131 void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
133 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
134 unsigned bytes = getEncodingBytes(MI);
140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
161 unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
163 unsigned regCode = getRegBinaryCode(MI.getOperand(OpNo).getReg());
167 unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
170 return GPRAlign(MI, OpNo, 1);
173 unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI,
176 return GPRAlign(MI, OpNo, 2);
179 uint64_t SIMCCodeEmitter::i32LiteralEncode(const MCInst &MI,
182 return LITERAL_REG | (MI.getOperand(OpNo).getImm() << 32);
197 uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo,
201 const MCOperand &OffsetOp = MI.getOperand(OpNo + 1);
207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
209 | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT)
219 uint64_t SIMCCodeEmitter::VOPPostEncode(const MCInst &MI, uint64_t Value) const{
220 unsigned encodingType = getEncodingType(MI);
234 const MCOperand &MO = MI.getOperand(opIdx);
236 unsigned reg = MI.getOperand(opIdx).getReg();
259 unsigned SIMCCodeEmitter::getEncodingType(const MCInst &MI) const {
260 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
263 unsigned SIMCCodeEmitter::getEncodingBytes(const MCInst &MI) const {
267 for (unsigned i = 0; i < MI.getNumOperands(); i++) {
268 if (MI.getOperand(i).isFPImm()) {
274 if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) {
278 unsigned encoding_type = getEncodingType(MI);