Lines Matching refs:def
30 def low : SubRegIndex;
31 def high : SubRegIndex;
33 def sub0 : SubRegIndex;
34 def sub1 : SubRegIndex;
35 def sub2 : SubRegIndex;
36 def sub3 : SubRegIndex;
37 def sub4 : SubRegIndex;
38 def sub5 : SubRegIndex;
39 def sub6 : SubRegIndex;
40 def sub7 : SubRegIndex;
90 def VCC : SIReg<"VCC">;
91 def EXEC : SIReg<"EXEC">;
92 def SCC : SIReg<"SCC">;
93 def SREG_LIT_0 : SIReg <"S LIT 0">;
95 def M0 : SIReg <"M0">;
99 def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">;
100 def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">;
101 def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">;
102 def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">;
103 def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">;
104 def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">;
105 def PERSP_I_W : SIReg <"PERSP_I_W">;
106 def PERSP_J_W : SIReg <"PERSP_J_W">;
107 def PERSP_1_W : SIReg <"PERSP_1_W">;
108 def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">;
109 def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">;
110 def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">;
111 def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">;
112 def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">;
113 def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">;
114 def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">;
115 def POS_X_FLOAT : SIReg <"POS_X_FLOAT">;
116 def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">;
117 def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">;
118 def POS_W_FLOAT : SIReg <"POS_W_FLOAT">;
119 def FRONT_FACE : SIReg <"FRONT_FACE">;
120 def ANCILLARY : SIReg <"ANCILLARY">;
121 def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">;
122 def POS_FIXED_PT : SIReg <"POS_FIXED_PT">;
130 print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n";
136 print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n";
142 def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
146 def VReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
167 def AllReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
171 def SCCReg : RegisterClass<"AMDGPU", [i1], 1, (add SCC)>;
172 def VCCReg : RegisterClass<"AMDGPU", [i1], 1, (add VCC)>;
173 def EXECReg : RegisterClass<"AMDGPU", [i1], 1, (add EXEC)>;
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
195 def AllReg_64 : RegisterClass<"AMDGPU", [f64, i64], 64,
269 print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n";
285 print "def $class_prefix\_$reg_width : RegisterClass<\"AMDGPU\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n";