Lines Matching refs:i830
54 struct i830_context *i830 = i830_context(ctx);
63 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
64 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
67 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
69 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE |
78 struct i830_context *i830 = i830_context(ctx);
84 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
85 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
86 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
94 struct i830_context *i830 = i830_context(ctx);
192 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
193 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
194 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
205 struct i830_context *i830 = i830_context(ctx);
213 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
214 i830->state.Ctx[I830_CTXREG_STATE2] &= ~ALPHA_TEST_REF_MASK;
215 i830->state.Ctx[I830_CTXREG_STATE2] |= (ENABLE_ALPHA_TEST_FUNC |
228 * This function is substantially different from the old i830-specific driver.
234 struct i830_context *i830 = i830_context(ctx);
236 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
239 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
241 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (DISABLE_COLOR_BLEND |
245 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
247 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (ENABLE_COLOR_BLEND |
251 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
253 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (DISABLE_COLOR_BLEND |
261 struct i830_context *i830 = i830_context(ctx);
271 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
272 i830->state.Ctx[I830_CTXREG_BLENDCOLOR1] =
277 * Sets both the blend equation (called "function" in i830 docs) and the
278 * blend function (called "factor" in i830 docs). This is done in a single
285 struct i830_context *i830 = i830_context(ctx);
364 if (iab != i830->state.Ctx[I830_CTXREG_IALPHAB] ||
365 s1 != i830->state.Ctx[I830_CTXREG_STATE1]) {
366 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
367 i830->state.Ctx[I830_CTXREG_IALPHAB] = iab;
368 i830->state.Ctx[I830_CTXREG_STATE1] = s1;
381 __FUNCTION__, __LINE__, i830->state.Ctx[I830_CTXREG_STATE1],
382 i830->state.Ctx[I830_CTXREG_IALPHAB],
423 struct i830_context *i830 = i830_context(ctx);
428 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
429 i830->state.Ctx[I830_CTXREG_STATE3] &= ~DEPTH_TEST_FUNC_MASK;
430 i830->state.Ctx[I830_CTXREG_STATE3] |= (ENABLE_DEPTH_TEST_FUNC |
437 struct i830_context *i830 = i830_context(ctx);
444 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
446 i830->state.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DIS_DEPTH_WRITE_MASK;
449 i830->state.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_DEPTH_WRITE;
451 i830->state.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DEPTH_WRITE;
473 * The i830 supports a 4x4 stipple natively, GL wants 32x32.
479 struct i830_context *i830 = i830_context(ctx);
484 i830->intel.reduced_primitive == GL_TRIANGLES);
488 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
489 i830->state.Stipple[I830_STPREG_ST1] &= ~ST1_ENABLE;
511 i830->intel.hw_stipple = 0;
522 i830->intel.hw_stipple = 0;
526 i830->state.Stipple[I830_STPREG_ST1] &= ~0xffff;
527 i830->state.Stipple[I830_STPREG_ST1] |= newMask;
528 i830->intel.hw_stipple = 1;
531 i830->state.Stipple[I830_STPREG_ST1] |= ST1_ENABLE;
541 struct i830_context *i830 = i830_context(ctx);
573 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
574 i830->state.Buffer[I830_DESTREG_SR1] = (y1 << 16) | (x1 & 0xffff);
575 i830->state.Buffer[I830_DESTREG_SR2] = (y2 << 16) | (x2 & 0xffff);
581 struct i830_context *i830 = i830_context(ctx);
586 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
587 i830->state.Ctx[I830_CTXREG_STATE4] &= ~LOGICOP_MASK;
588 i830->state.Ctx[I830_CTXREG_STATE4] |= LOGIC_OP_FUNC(tmp);
596 struct i830_context *i830 = i830_context(ctx);
616 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
617 i830->state.Ctx[I830_CTXREG_STATE3] &= ~CULLMODE_MASK;
618 i830->state.Ctx[I830_CTXREG_STATE3] |= ENABLE_CULL_MODE | mode;
624 struct i830_context *i830 = i830_context(ctx);
633 state5 = i830->state.Ctx[I830_CTXREG_STATE5] & ~FIXED_LINE_WIDTH_MASK;
636 if (state5 != i830->state.Ctx[I830_CTXREG_STATE5]) {
637 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
638 i830->state.Ctx[I830_CTXREG_STATE5] = state5;
645 struct i830_context *i830 = i830_context(ctx);
651 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
652 i830->state.Ctx[I830_CTXREG_STATE5] &= ~FIXED_POINT_WIDTH_MASK;
653 i830->state.Ctx[I830_CTXREG_STATE5] |= (ENABLE_FIXED_POINT_WIDTH |
666 struct i830_context *i830 = i830_context(ctx);
671 tmp = ((i830->state.Ctx[I830_CTXREG_ENABLES_2] & ~WRITEMASK_MASK) |
678 if (tmp != i830->state.Ctx[I830_CTXREG_ENABLES_2]) {
679 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
680 i830->state.Ctx[I830_CTXREG_ENABLES_2] = tmp;
687 struct i830_context *i830 = i830_context(ctx);
689 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
690 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_SPEC_ADD_MASK;
693 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_SPEC_ADD;
695 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_SPEC_ADD;
713 struct i830_context *i830 = i830_context(ctx);
714 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
719 i830->state.Ctx[I830_CTXREG_STATE3] &= ~SHADE_MODE_MASK;
722 i830->state.Ctx[I830_CTXREG_STATE3] |=
728 i830->state.Ctx[I830_CTXREG_STATE3] |=
742 struct i830_context *i830 = i830_context(ctx);
751 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
752 i830->state.Ctx[I830_CTXREG_FOGCOLOR] =
763 struct i830_context *i830 = i830_context(ctx);
772 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
773 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_ALPHA_TEST_MASK;
775 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_ALPHA_TEST;
777 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_ALPHA_TEST;
790 if (i830->intel.ctx.Visual.rgbBits == 16)
791 FALLBACK(&i830->intel, I830_FALLBACK_LOGICOP, state);
795 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
796 i830->state.Ctx[I830_CTXREG_ENABLES_2] &= ~ENABLE_DITHER;
799 i830->state.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_DITHER;
801 i830->state.Ctx[I830_CTXREG_ENABLES_2] |= DISABLE_DITHER;
805 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
806 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_DEPTH_TEST_MASK;
812 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_DEPTH_TEST;
814 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_DEPTH_TEST;
822 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
825 i830->state.Buffer[I830_DESTREG_SENABLE] =
828 i830->state.Buffer[I830_DESTREG_SENABLE] =
834 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
836 i830->state.Ctx[I830_CTXREG_AA] &= ~AA_LINE_ENABLE;
838 i830->state.Ctx[I830_CTXREG_AA] |= AA_LINE_ENABLE;
840 i830->state.Ctx[I830_CTXREG_AA] |= AA_LINE_DISABLE;
844 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
845 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_DIS_FOG_MASK;
847 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_FOG;
849 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_FOG;
868 I830_STATECHANGE(i830, I830_UPLOAD_CTX);
871 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= ENABLE_STENCIL_TEST;
872 i830->state.Ctx[I830_CTXREG_ENABLES_2] |= ENABLE_STENCIL_WRITE;
875 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~ENABLE_STENCIL_TEST;
876 i830->state.Ctx[I830_CTXREG_ENABLES_2] &=
878 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= DISABLE_STENCIL_TEST;
879 i830->state.Ctx[I830_CTXREG_ENABLES_2] |=
884 FALLBACK(&i830->intel, I830_FALLBACK_STENCIL, state);
894 if (i830->intel.hw_stipple &&
895 i830->intel.reduced_primitive == GL_TRIANGLES) {
896 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
897 i830->state.Stipple[I830_STPREG_ST1] &= ~ST1_ENABLE;
899 i830->state.Stipple[I830_STPREG_ST1] |= ST1_ENABLE;
910 i830_init_packets(struct i830_context *i830)
913 memset(&i830->state, 0, sizeof(i830->state));
916 i830->state.TexBlend[0][0] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
924 i830->state.TexBlend[0][1] = (_3DSTATE_MAP_BLEND_OP_CMD(0) |
930 i830->state.TexBlend[0][2] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
935 i830->state.TexBlend[0][3] = (_3DSTATE_MAP_BLEND_ARG_CMD(0) |
941 i830->state.TexBlendWordsUsed[0] = 4;
944 i830->state.Ctx[I830_CTXREG_VF] = 0;
945 i830->state.Ctx[I830_CTXREG_VF2] = 0;
947 i830->state.Ctx[I830_CTXREG_AA] = (_3DSTATE_AA_CMD |
954 i830->state.Ctx[I830_CTXREG_ENABLES_1] = (_3DSTATE_ENABLES_1_CMD |
965 if (i830->intel.hw_stencil) {
966 i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
978 i830->state.Ctx[I830_CTXREG_ENABLES_2] = (_3DSTATE_ENABLES_2_CMD |
988 i830->state.Ctx[I830_CTXREG_STATE1] = (_3DSTATE_MODES_1_CMD |
996 i830->state.Ctx[I830_CTXREG_STATE2] = (_3DSTATE_MODES_2_CMD |
1003 i830->state.Ctx[I830_CTXREG_STATE3] = (_3DSTATE_MODES_3_CMD |
1016 i830->state.Ctx[I830_CTXREG_STATE4] = (_3DSTATE_MODES_4_CMD |
1024 i830->state.Ctx[I830_CTXREG_STENCILTST] = (_3DSTATE_STENCIL_TEST_CMD |
1038 i830->state.Ctx[I830_CTXREG_STATE5] = (_3DSTATE_MODES_5_CMD | FLUSH_TEXTURE_CACHE | ENABLE_SPRITE_POINT_TEX | SPRITE_POINT_TEX_OFF | ENABLE_FIXED_LINE_WIDTH | FIXED_LINE_WIDTH(0x2) | /* 1.0 */
1042 i830->state.Ctx[I830_CTXREG_IALPHAB] = (_3DSTATE_INDPT_ALPHA_BLEND_CMD |
1047 i830->state.Ctx[I830_CTXREG_FOGCOLOR] = (_3DSTATE_FOG_COLOR_CMD |
1052 i830->state.Ctx[I830_CTXREG_BLENDCOLOR0] = _3DSTATE_CONST_BLEND_COLOR_CMD;
1053 i830->state.Ctx[I830_CTXREG_BLENDCOLOR1] = 0;
1055 i830->state.Ctx[I830_CTXREG_MCSB0] = _3DSTATE_MAP_COORD_SETBIND_CMD;
1056 i830->state.Ctx[I830_CTXREG_MCSB1] = (TEXBIND_SET3(TEXCOORDSRC_VTXSET_3) |
1061 i830->state.RasterRules[I830_RASTER_RULES] = (_3DSTATE_RASTER_RULES_CMD |
1072 i830->state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;
1074 i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
1075 i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
1077 i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
1078 i830->state.Buffer[I830_DESTREG_SR1] = 0;
1079 i830->state.Buffer[I830_DESTREG_SR2] = 0;
1085 struct i830_context *i830 = i830_context(ctx);
1087 I830_STATECHANGE(i830, I830_UPLOAD_RASTER_RULES);
1088 i830->state.RasterRules[I830_RASTER_RULES] &= ~(LINE_STRIP_PROVOKE_VRTX_MASK |
1094 i830->state.RasterRules[I830_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(1) |
1098 i830->state.RasterRules[I830_RASTER_RULES] |= (LINE_STRIP_PROVOKE_VRTX(0) |
1143 i830InitState(struct i830_context *i830)
1145 struct gl_context *ctx = &i830->intel.ctx;
1147 i830_init_packets(i830);
1151 i830->state.emitted = 0;
1152 i830->state.active = (I830_UPLOAD_INVARIENT |