Lines Matching defs:t3
17 register uint32_t t0, t1, t2, t3, t4, t5, t6;
38 "shrl.ph %[t3], %[s0], 11 \n\t"
41 "and %[t3], %[t0], %[s5] \n\t"
57 "subu.qb %[t6], %[t6], %[t3] \n\t"
68 "addu.qb %[t6], %[t6], %[t3] \n\t"
87 : [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3),
121 register int32_t t0, t1, t2, t3, t4, t5, t6;
139 "andi %[t3], %[x], 0x3 \n\t"
141 "sll %[t4], %[t3], 2 \n\t"
143 "andi %[t3], %[t5], 0xf \n\t"
149 "ins %[t3], %[t6], 8, 4 \n\t"
155 "muleu_s.ph.qbr %[t4], %[t3], %[t0] \n\t"
156 "preceu.ph.qbla %[t3], %[t4] \n\t"
160 "subu.qb %[t6], %[t3], %[t5] \n\t"
166 "shrl.qb %[t7], %[t3], 1 \n\t"
173 "subu.qb %[t8], %[t3], %[t7] \n\t"
178 "andi %[t3], %[t6], 0xffff \n\t"
188 "sll %[t1], %[t3], 24 \n\t"
190 "andi %[t3], %[t5], 0x7e0 \n\t"
191 "sll %[t6], %[t3], 0x10 \n\t"
210 "andi %[t3], %[t5], 0x7e0 \n\t"
211 "sll %[t6], %[t3], 0x10 \n\t"
231 [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3),
269 register uint32_t t0, t1, t2, t3, t4, t5;
304 "precrq.ph.w %[t3], %[t0], %[t2] \n\t"
305 "preceu.ph.qbra %[t9], %[t3] \n\t"
319 "subu.qb %[t3], %[t0], %[t2] \n\t"
320 "shra.ph %[t6], %[t3], 3 \n\t"
323 "subu.qb %[t3], %[t0], %[t2] \n\t"
324 "shra.ph %[t7], %[t3], 3 \n\t"
327 "addu.qb %[t3], %[t5], %[t0] \n\t"
328 "subu.qb %[t4], %[t3], %[t2] \n\t"
343 "or %[t3], %[t9], %[t0] \n\t"
344 "andi %[t4], %[t3], 0xFFFF \n\t"
348 "or %[t3], %[t9], %[t6] \n\t"
349 "and %[t7], %[t3], 0xFFFF \n\t"
360 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
378 register int32_t t0, t1, t2, t3, t4, t5, t6;
426 "sll %[t3], %[t0], 7 \n\t"
435 "precrq.qb.ph %[t1], %[t3], %[t4] \n\t"
456 "shrl.qb %[t3], %[t4], 5 \n\t"
458 "subu.qb %[t4], %[t4], %[t3] \n\t"
460 "shrl.qb %[t3], %[t5], 5 \n\t"
462 "subu.qb %[t5], %[t5], %[t3] \n\t"
464 "shrl.qb %[t3], %[t6], 6 \n\t"
466 "subu.qb %[t6], %[t6], %[t3] \n\t"
497 "and %[t3], %[s1], 0xFFFF \n\t"
499 "sh %[t3], 2(%[dst]) \n\t"
508 [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3),
550 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8;
585 "preceu.ph.qbra %[t3], %[t0] \n\t"
611 "addq.ph %[t7], %[t0], %[t3] \n\t"
619 "shra.ph %[t3], %[t7], 3 \n\t"
630 "or %[t3], %[t2], %[t3] \n\t"
631 "sra %[t4], %[t3], 16 \n\t"
633 "sh %[t3], 2(%[dst]) \n\t"
642 [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5), [t6]"=&r"(t6),
661 register uint32_t t0, t1, t2, t3, t4, t5, t6, t7, t8, t9;
681 "sll %[t3], %[t9], 8 \n\t"
682 "precrq.qb.ph %[t1], %[t2], %[t3] \n\t"
683 "precrq.qb.ph %[t3], %[t8], %[t9] \n\t"
684 "preceu.ph.qbla %[t8], %[t3] \n\t"
688 "preceu.ph.qbra %[t3], %[t3] \n\t"
705 "shrl.qb %[t3], %[t3], 2 \n\t"
708 "muleu_s.ph.qbl %[t3], %[t0], %[t3] \n\t"
714 "addq.ph %[t3], %[t3], %[t4] \n\t"
717 "addq.ph %[t4], %[t3], %[t6] \n\t"
724 "shra.ph %[t3], %[t4], 8 \n\t"
725 "addq.ph %[t3], %[t3], %[t4] \n\t"
726 "preceu.ph.qbla %[t3], %[t3] \n\t"
728 "shll.ph %[t9], %[t3], 5 \n\t"
744 [t2]"=&r"(t2), [t3]"=&r"(t3), [t4]"=&r"(t4), [t5]"=&r"(t5),
771 register int32_t t0, t1, t2, t3, t4, t5, t6, t7;
786 "preceu.ph.qbl %[t3], %[t0] \n\t"
790 "muleu_s.ph.qbr %[t3], %[t7], %[t3] \n\t"
795 "precrq.qb.ph %[t0], %[t3], %[t2] \n\t"
804 [t0]"=&r"(t0), [t1]"=&r"(t1), [t2]"=&r"(t2), [t3]"=&r"(t3),
833 "lhu $t3, 6(%[device]) \n\t"
841 "replv.ph $t3, $t3 \n\t"
853 "and $t3, $t3, $t9 \n\t"
857 "subu $t7, %[expanded32], $t3 \n\t"
870 "addu $t7, $t3, $t7 \n\t"
878 "srl $t3, $t7, 16 \n\t"
882 "or %[s3], $t3, $t7 \n\t"
897 "subu $t3, %[expanded32], $t2 \n\t"
898 "mul $t3, $t3, $t0 \n\t"
900 "srl $t3, $t3, 5 \n\t"
901 "addu $t3, $t2, $t3 \n\t"
902 "and $t3, $t3, $t9 \n\t"
903 "srl $t4, $t3, 16 \n\t"
904 "or %[s0], $t4, $t3 \n\t"
917 : "memory", "hi", "lo", "t0", "t1", "t2", "t3",