Lines Matching refs:MI
154 MachineInstr *MI;
158 : MI(mi), Def(def), FI(fi) {}
168 void HoistPostRA(MachineInstr *MI, unsigned Def);
172 void ProcessMI(MachineInstr *MI,
196 bool HasLoopPHIUse(const MachineInstr *MI) const;
201 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
204 bool IsCheapInstruction(MachineInstr &MI) const;
213 /// effect of hoisting MI from the current block to the preheader.
214 void UpdateBackTraceRegPressure(const MachineInstr *MI);
218 bool IsProfitableToHoist(MachineInstr &MI);
244 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
247 void getRegisterClassIDAndCost(const MachineInstr *MI,
258 void UpdateRegPressure(const MachineInstr *MI);
264 MachineInstr *ExtractHoistableLoad(MachineInstr *MI);
267 /// duplicate of MI. Return this instruction if it's found.
268 const MachineInstr *LookForDuplicate(const MachineInstr *MI,
275 bool EliminateCSE(MachineInstr *MI,
280 bool MayCSE(MachineInstr *MI);
285 bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader);
391 static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
392 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
393 oe = MI->memoperands_end(); o != oe; ++o) {
407 void MachineLICM::ProcessMI(MachineInstr *MI,
415 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
416 const MachineOperand &MO = MI->getOperand(i);
422 InstructionStoresToFI(MI, FI))
478 // MI defined register is seen defined by another instruction in
487 if ((!HasNonInvariantUse && IsLICMCandidate(*MI)) ||
488 (TII->isLoadFromStackSlot(MI, FI) && MFI->isSpillSlotObjectIndex(FI)))
489 Candidates.push_back(CandidateInfo(MI, Def, FI));
531 MachineInstr *MI = &*MII;
532 ProcessMI(MI, PhysRegDefs, PhysRegClobbers, StoredFIs, Candidates);
568 MachineInstr *MI = Candidates[i].MI;
569 for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
570 const MachineOperand &MO = MI->getOperand(j);
583 HoistPostRA(MI, Candidates[i].Def);
598 MachineInstr *MI = &*MII;
599 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
600 MachineOperand &MO = MI->getOperand(i);
612 void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
618 << MI->getParent()->getNumber() << ": " << *MI);
621 MachineBasicBlock *MBB = MI->getParent();
622 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
765 MachineInstr *MI = &*MII;
766 if (!Hoist(MI, Preheader))
767 UpdateRegPressure(MI);
780 /// getRegisterClassIDAndCost - For a given MI, register, and the operand
783 MachineLICM::getRegisterClassIDAndCost(const MachineInstr *MI,
816 MachineInstr *MI = &*MII;
817 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
818 const MachineOperand &MO = MI->getOperand(i);
827 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
844 void MachineLICM::UpdateRegPressure(const MachineInstr *MI) {
845 if (MI->isImplicitDef())
849 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
850 const MachineOperand &MO = MI->getOperand(i);
862 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
874 getRegisterClassIDAndCost(MI, Reg, Idx, RCId, RCCost);
882 static bool isLoadFromGOTOrConstantPool(MachineInstr &MI) {
883 assert (MI.mayLoad() && "Expected MI that loads!");
884 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
885 E = MI.memoperands_end(); I != E; ++I) {
974 bool MachineLICM::HasLoopPHIUse(const MachineInstr *MI) const {
975 SmallVector<const MachineInstr*, 8> Work(1, MI);
977 MI = Work.pop_back_val();
978 for (ConstMIOperands MO(MI); MO.isValid(); ++MO) {
1010 bool MachineLICM::HasHighOperandLatency(MachineInstr &MI,
1028 if (TII->hasHighOperandLatency(InstrItins, MRI, &MI, DefIdx, &UseMI, i))
1041 bool MachineLICM::IsCheapInstruction(MachineInstr &MI) const {
1042 if (TII->isAsCheapAsAMove(&MI) || MI.isCopyLike())
1048 unsigned NumDefs = MI.getDesc().getNumDefs();
1049 for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
1050 MachineOperand &DefMO = MI.getOperand(i);
1058 if (!TII->hasLowDefLatency(InstrItins, &MI, i))
1097 /// of hoisting MI from the current block to the preheader.
1098 void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
1099 if (MI->isImplicitDef())
1105 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
1106 const MachineOperand &MO = MI->getOperand(i);
1114 getRegisterClassIDAndCost(MI, Reg, i, RCId, RCCost);
1143 bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
1144 if (MI.isImplicitDef())
1159 bool CheapInstr = IsCheapInstruction(MI);
1160 bool CreatesCopy = HasLoopPHIUse(&MI);
1164 DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
1170 if (TII->isTriviallyReMaterializable(&MI, AA))
1182 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
1183 const MachineOperand &MO = MI.getOperand(i);
1191 getRegisterClassIDAndCost(&MI, Reg, i, RCId, RCCost);
1193 if (HasHighOperandLatency(MI, i, Reg)) {
1194 DEBUG(dbgs() << "Hoist High Latency: " << MI);
1210 DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
1217 DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
1225 (!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
1226 DEBUG(dbgs() << "Won't speculate: " << MI);
1232 if (!TII->isTriviallyReMaterializable(&MI, AA) &&
1233 !MI.isInvariantLoad(AA)) {
1234 DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
1241 MachineInstr *MachineLICM::ExtractHoistableLoad(MachineInstr *MI) {
1243 if (MI->canFoldAsLoad())
1249 if (!MI->isInvariantLoad(AA))
1255 TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(),
1262 MachineFunction &MF = *MI->getParent()->getParent();
1269 TII->unfoldMemoryOperand(MF, MI, Reg,
1278 MachineBasicBlock *MBB = MI->getParent();
1279 MachineBasicBlock::iterator Pos = MI;
1294 MI->eraseFromParent();
1300 const MachineInstr *MI = &*I;
1301 unsigned Opcode = MI->getOpcode();
1305 CI->second.push_back(MI);
1308 CSEMIs.push_back(MI);
1315 MachineLICM::LookForDuplicate(const MachineInstr *MI,
1319 if (TII->produceSameValue(MI, PrevMI, (PreRegAlloc ? MRI : nullptr)))
1325 bool MachineLICM::EliminateCSE(MachineInstr *MI,
1329 if (CI == CSEMap.end() || MI->isImplicitDef())
1332 if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
1333 DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
1335 // Replace virtual registers defined by MI by their counterparts defined
1338 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1339 const MachineOperand &MO = MI->getOperand(i);
1355 unsigned Reg = MI->getOperand(Idx).getReg();
1369 unsigned Reg = MI->getOperand(Idx).getReg();
1375 MI->eraseFromParent();
1384 bool MachineLICM::MayCSE(MachineInstr *MI) {
1385 unsigned Opcode = MI->getOpcode();
1390 if (CI == CSEMap.end() || MI->isImplicitDef())
1393 return LookForDuplicate(MI, CI->second) != nullptr;
1399 bool MachineLICM::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
1401 if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
1403 MI = ExtractHoistableLoad(MI);
1404 if (!MI) return false;
1410 dbgs() << "Hoisting " << *MI;
1414 if (MI->getParent()->getBasicBlock())
1416 << MI->getParent()->getName();
1428 unsigned Opcode = MI->getOpcode();
1431 if (!EliminateCSE(MI, CI)) {
1433 Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI);
1436 UpdateBackTraceRegPressure(MI);
1441 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1442 MachineOperand &MO = MI->getOperand(i);
1449 CI->second.push_back(MI);
1452 CSEMIs.push_back(MI);