Lines Matching defs:DefSubReg
168 unsigned DefSubReg;
206 /// \p DefSubReg represents the sub register index the value tracker will
212 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
215 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
454 unsigned DefSubReg,
463 if (SrcSubReg && DefSubReg)
464 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
469 std::swap(DefSubReg, SrcSubReg);
544 unsigned DefSubReg = MODef.getSubReg();
553 ValueTracker ValTracker(*MI, DefIdx, DefSubReg, !DisableAdvCopyOpt, MRI);
572 ShouldRewrite = shareSameRegisterFile(TRI, DefRC, DefSubReg, SrcRC,
586 NewCopy->getOperand(0).setSubReg(DefSubReg);
791 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
812 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
862 if (MOSubIdx.getImm() == DefSubReg) {
889 // 1. DefSubReg == sub1, get v1.
890 // 2. DefSubReg != sub1, the value may be available through v0.
894 if (InsertedSubReg == DefSubReg) {
919 (TRI->getSubRegIndexLaneMask(DefSubReg) &
925 SrcSubReg = DefSubReg;
936 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
937 if (DefSubReg)
957 // If DefSubReg != sub0, we would have to check that all the bits
960 if (DefSubReg != Def->getOperand(3).getImm())
1020 DefSubReg = SrcSubReg;