Cross Reference: /external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

Lines Matching refs:Reg
86                               unsigned &Reg, unsigned &Imm,
513     unsigned Reg = MO.getReg();
514     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
517     switch (Reg) {
538 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
544   Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
866   unsigned Reg, Imm12;
871     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
887       Reg = ARM::PC;
899     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI);
905   Binary |= (Reg << 13);
950   unsigned Reg, Imm8;
955     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
966     isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
978   Binary |= (Reg << 9);
992   unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg());
994   return (Reg << 8) | Imm8;
1243   unsigned Reg, Imm8;
1248     Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC);   // Rn is PC.
1263     EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI);
1271   Binary |= (Reg << 9);
1512   unsigned Reg = MI.getOperand(Op).getReg();
1513   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
1514   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
1520     unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg);
1543   const MCOperand &Reg = MI.getOperand(Op);
1546   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1567   const MCOperand &Reg = MI.getOperand(Op);
1570   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());
1594   const MCOperand &Reg = MI.getOperand(Op);
1597   unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg.getReg());