Lines Matching defs:PredReg
61 unsigned PredReg = 0;
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
109 unsigned PredReg = 0;
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
215 ARMCC::CondCodes Pred, unsigned PredReg,
220 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
244 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
253 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
259 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
452 unsigned PredReg;
453 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
625 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
629 return getInstrPredicate(MI, PredReg);