Lines Matching refs:Reg
191 if (unsigned Reg = State.AllocateReg(RegList, 6)) {
192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
205 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
206 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
216 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
217 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
262 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
263 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
277 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
278 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
720 unsigned Reg =
727 if (Reg == QRI->getRARegister()) {
987 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32));
988 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);