Cross Reference: /external/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp

Lines Matching defs:MBB
58   bool expandInstr(MachineBasicBlock &MBB, Iter I);
59   void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
60   void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
61   void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
62   void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
64   bool expandCopy(MachineBasicBlock &MBB, Iter I);
65   bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
87 bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
90     expandLoadCCond(MBB, I);
93     expandStoreCCond(MBB, I);
97     expandLoadACC(MBB, I, 4);
100     expandLoadACC(MBB, I, 8);
103     expandStoreACC(MBB, I, Mips::PseudoMFHI, Mips::PseudoMFLO, 4);
106     expandStoreACC(MBB, I, Mips::MFHI_DSP, Mips::MFLO_DSP, 4);
109     expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
112     if (!expandCopy(MBB, I))
119   MBB.erase(I);
123 void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
138   TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
139   BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
143 void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
158   BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
160   TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
163 void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
186   TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0);
187   BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
188   TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
189   BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
192 void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
214   BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
215   TII.storeRegToStack(MBB, I, VR0, true, FI, RC, &RegInfo, 0);
216   BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
217   TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
220 bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
227   return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second);
230 bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
252   BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
253   BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
255   BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
256   BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
276   MachineBasicBlock &MBB   = MF.front();
285   MachineBasicBlock::iterator MBBI = MBB.begin();
286   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
303   TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
308   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
339         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
344         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
350         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
362       if (!MBB.isLiveIn(ehDataReg(I)))
363         MBB.addLiveIn(ehDataReg(I));
364       TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
374       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
382     BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
388     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
394                                        MachineBasicBlock &MBB) const {
395   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
419     BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
433       TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
445   TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
449 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
453   MachineFunction *MF = MBB.getParent();
493 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
505     TII.adjustStackPtr(SP, Amount, MBB, I);
508   MBB.erase(I);