Cross Reference: /external/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

Lines Matching defs:Reg
54     RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
97     unsigned Reg = CSRegs[I];
98     if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
140     unsigned Reg = CSI[I].getReg();
141     if (SystemZ::GR64BitRegClass.contains(Reg)) {
142       unsigned Offset = RegSpillOffsets[Reg];
145         LowGPR = Reg;
161       unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
162       unsigned Offset = RegSpillOffsets[Reg];
164         LowGPR = Reg; StartOffset = Offset;
186       unsigned Reg = CSI[I].getReg();
187       if (SystemZ::GR64BitRegClass.contains(Reg))
188         addSavedGPR(MBB, MIB, Reg, true);
199     unsigned Reg = CSI[I].getReg();
200     if (SystemZ::FP64BitRegClass.contains(Reg)) {
201       MBB.addLiveIn(Reg);
202       TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
226     unsigned Reg = CSI[I].getReg();
227     if (SystemZ::FP64BitRegClass.contains(Reg))
228       TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
256       unsigned Reg = CSI[I].getReg();
257       if (Reg != LowGPR && Reg != HighGPR)
258         MIB.addReg(Reg, RegState::ImplicitDefine);
281 // Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
285                           unsigned Reg, int64_t NumBytes,
302     MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
303       .addReg(Reg).addImm(ThisVal);
335       unsigned Reg = Save.getReg();
336       if (SystemZ::GR64BitRegClass.contains(Reg)) {
337         int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
339             nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
382     unsigned Reg = Save.getReg();
383     if (SystemZ::FP64BitRegClass.contains(Reg)) {
392       unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);