1//===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "SystemZFrameLowering.h"
11#include "SystemZCallingConv.h"
12#include "SystemZInstrBuilder.h"
13#include "SystemZInstrInfo.h"
14#include "SystemZMachineFunctionInfo.h"
15#include "SystemZRegisterInfo.h"
16#include "llvm/CodeGen/MachineModuleInfo.h"
17#include "llvm/CodeGen/MachineRegisterInfo.h"
18#include "llvm/CodeGen/RegisterScavenging.h"
19#include "llvm/IR/Function.h"
20
21using namespace llvm;
22
23namespace {
24// The ABI-defined register save slots, relative to the incoming stack
25// pointer.
26static const TargetFrameLowering::SpillSlot SpillOffsetTable[] = {
27  { SystemZ::R2D,  0x10 },
28  { SystemZ::R3D,  0x18 },
29  { SystemZ::R4D,  0x20 },
30  { SystemZ::R5D,  0x28 },
31  { SystemZ::R6D,  0x30 },
32  { SystemZ::R7D,  0x38 },
33  { SystemZ::R8D,  0x40 },
34  { SystemZ::R9D,  0x48 },
35  { SystemZ::R10D, 0x50 },
36  { SystemZ::R11D, 0x58 },
37  { SystemZ::R12D, 0x60 },
38  { SystemZ::R13D, 0x68 },
39  { SystemZ::R14D, 0x70 },
40  { SystemZ::R15D, 0x78 },
41  { SystemZ::F0D,  0x80 },
42  { SystemZ::F2D,  0x88 },
43  { SystemZ::F4D,  0x90 },
44  { SystemZ::F6D,  0x98 }
45};
46} // end anonymous namespace
47
48SystemZFrameLowering::SystemZFrameLowering()
49    : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8,
50                          -SystemZMC::CallFrameSize, 8) {
51  // Create a mapping from register number to save slot offset.
52  RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
53  for (unsigned I = 0, E = array_lengthof(SpillOffsetTable); I != E; ++I)
54    RegSpillOffsets[SpillOffsetTable[I].Reg] = SpillOffsetTable[I].Offset;
55}
56
57const TargetFrameLowering::SpillSlot *
58SystemZFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
59  NumEntries = array_lengthof(SpillOffsetTable);
60  return SpillOffsetTable;
61}
62
63void SystemZFrameLowering::
64processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
65                                     RegScavenger *RS) const {
66  MachineFrameInfo *MFFrame = MF.getFrameInfo();
67  MachineRegisterInfo &MRI = MF.getRegInfo();
68  const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
69  bool HasFP = hasFP(MF);
70  SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
71  bool IsVarArg = MF.getFunction()->isVarArg();
72
73  // va_start stores incoming FPR varargs in the normal way, but delegates
74  // the saving of incoming GPR varargs to spillCalleeSavedRegisters().
75  // Record these pending uses, which typically include the call-saved
76  // argument register R6D.
77  if (IsVarArg)
78    for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
79      MRI.setPhysRegUsed(SystemZ::ArgGPRs[I]);
80
81  // If the function requires a frame pointer, record that the hard
82  // frame pointer will be clobbered.
83  if (HasFP)
84    MRI.setPhysRegUsed(SystemZ::R11D);
85
86  // If the function calls other functions, record that the return
87  // address register will be clobbered.
88  if (MFFrame->hasCalls())
89    MRI.setPhysRegUsed(SystemZ::R14D);
90
91  // If we are saving GPRs other than the stack pointer, we might as well
92  // save and restore the stack pointer at the same time, via STMG and LMG.
93  // This allows the deallocation to be done by the LMG, rather than needing
94  // a separate %r15 addition.
95  const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
96  for (unsigned I = 0; CSRegs[I]; ++I) {
97    unsigned Reg = CSRegs[I];
98    if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
99      MRI.setPhysRegUsed(SystemZ::R15D);
100      break;
101    }
102  }
103}
104
105// Add GPR64 to the save instruction being built by MIB, which is in basic
106// block MBB.  IsImplicit says whether this is an explicit operand to the
107// instruction, or an implicit one that comes between the explicit start
108// and end registers.
109static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
110                        unsigned GPR64, bool IsImplicit) {
111  const TargetRegisterInfo *RI = MBB.getParent()->getTarget().getRegisterInfo();
112  unsigned GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
113  bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32);
114  if (!IsLive || !IsImplicit) {
115    MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
116    if (!IsLive)
117      MBB.addLiveIn(GPR64);
118  }
119}
120
121bool SystemZFrameLowering::
122spillCalleeSavedRegisters(MachineBasicBlock &MBB,
123                          MachineBasicBlock::iterator MBBI,
124                          const std::vector<CalleeSavedInfo> &CSI,
125                          const TargetRegisterInfo *TRI) const {
126  if (CSI.empty())
127    return false;
128
129  MachineFunction &MF = *MBB.getParent();
130  const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
131  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
132  bool IsVarArg = MF.getFunction()->isVarArg();
133  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
134
135  // Scan the call-saved GPRs and find the bounds of the register spill area.
136  unsigned LowGPR = 0;
137  unsigned HighGPR = SystemZ::R15D;
138  unsigned StartOffset = -1U;
139  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
140    unsigned Reg = CSI[I].getReg();
141    if (SystemZ::GR64BitRegClass.contains(Reg)) {
142      unsigned Offset = RegSpillOffsets[Reg];
143      assert(Offset && "Unexpected GPR save");
144      if (StartOffset > Offset) {
145        LowGPR = Reg;
146        StartOffset = Offset;
147      }
148    }
149  }
150
151  // Save the range of call-saved registers, for use by the epilogue inserter.
152  ZFI->setLowSavedGPR(LowGPR);
153  ZFI->setHighSavedGPR(HighGPR);
154
155  // Include the GPR varargs, if any.  R6D is call-saved, so would
156  // be included by the loop above, but we also need to handle the
157  // call-clobbered argument registers.
158  if (IsVarArg) {
159    unsigned FirstGPR = ZFI->getVarArgsFirstGPR();
160    if (FirstGPR < SystemZ::NumArgGPRs) {
161      unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
162      unsigned Offset = RegSpillOffsets[Reg];
163      if (StartOffset > Offset) {
164        LowGPR = Reg; StartOffset = Offset;
165      }
166    }
167  }
168
169  // Save GPRs
170  if (LowGPR) {
171    assert(LowGPR != HighGPR && "Should be saving %r15 and something else");
172
173    // Build an STMG instruction.
174    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
175
176    // Add the explicit register operands.
177    addSavedGPR(MBB, MIB, LowGPR, false);
178    addSavedGPR(MBB, MIB, HighGPR, false);
179
180    // Add the address.
181    MIB.addReg(SystemZ::R15D).addImm(StartOffset);
182
183    // Make sure all call-saved GPRs are included as operands and are
184    // marked as live on entry.
185    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
186      unsigned Reg = CSI[I].getReg();
187      if (SystemZ::GR64BitRegClass.contains(Reg))
188        addSavedGPR(MBB, MIB, Reg, true);
189    }
190
191    // ...likewise GPR varargs.
192    if (IsVarArg)
193      for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
194        addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
195  }
196
197  // Save FPRs in the normal TargetInstrInfo way.
198  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
199    unsigned Reg = CSI[I].getReg();
200    if (SystemZ::FP64BitRegClass.contains(Reg)) {
201      MBB.addLiveIn(Reg);
202      TII->storeRegToStackSlot(MBB, MBBI, Reg, true, CSI[I].getFrameIdx(),
203                               &SystemZ::FP64BitRegClass, TRI);
204    }
205  }
206
207  return true;
208}
209
210bool SystemZFrameLowering::
211restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
212                            MachineBasicBlock::iterator MBBI,
213                            const std::vector<CalleeSavedInfo> &CSI,
214                            const TargetRegisterInfo *TRI) const {
215  if (CSI.empty())
216    return false;
217
218  MachineFunction &MF = *MBB.getParent();
219  const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
220  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
221  bool HasFP = hasFP(MF);
222  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
223
224  // Restore FPRs in the normal TargetInstrInfo way.
225  for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
226    unsigned Reg = CSI[I].getReg();
227    if (SystemZ::FP64BitRegClass.contains(Reg))
228      TII->loadRegFromStackSlot(MBB, MBBI, Reg, CSI[I].getFrameIdx(),
229                                &SystemZ::FP64BitRegClass, TRI);
230  }
231
232  // Restore call-saved GPRs (but not call-clobbered varargs, which at
233  // this point might hold return values).
234  unsigned LowGPR = ZFI->getLowSavedGPR();
235  unsigned HighGPR = ZFI->getHighSavedGPR();
236  unsigned StartOffset = RegSpillOffsets[LowGPR];
237  if (LowGPR) {
238    // If we saved any of %r2-%r5 as varargs, we should also be saving
239    // and restoring %r6.  If we're saving %r6 or above, we should be
240    // restoring it too.
241    assert(LowGPR != HighGPR && "Should be loading %r15 and something else");
242
243    // Build an LMG instruction.
244    MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
245
246    // Add the explicit register operands.
247    MIB.addReg(LowGPR, RegState::Define);
248    MIB.addReg(HighGPR, RegState::Define);
249
250    // Add the address.
251    MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
252    MIB.addImm(StartOffset);
253
254    // Do a second scan adding regs as being defined by instruction
255    for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
256      unsigned Reg = CSI[I].getReg();
257      if (Reg != LowGPR && Reg != HighGPR)
258        MIB.addReg(Reg, RegState::ImplicitDefine);
259    }
260  }
261
262  return true;
263}
264
265void SystemZFrameLowering::
266processFunctionBeforeFrameFinalized(MachineFunction &MF,
267                                    RegScavenger *RS) const {
268  MachineFrameInfo *MFFrame = MF.getFrameInfo();
269  uint64_t MaxReach = (MFFrame->estimateStackSize(MF) +
270                       SystemZMC::CallFrameSize * 2);
271  if (!isUInt<12>(MaxReach)) {
272    // We may need register scavenging slots if some parts of the frame
273    // are outside the reach of an unsigned 12-bit displacement.
274    // Create 2 for the case where both addresses in an MVC are
275    // out of range.
276    RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
277    RS->addScavengingFrameIndex(MFFrame->CreateStackObject(8, 8, false));
278  }
279}
280
281// Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
282static void emitIncrement(MachineBasicBlock &MBB,
283                          MachineBasicBlock::iterator &MBBI,
284                          const DebugLoc &DL,
285                          unsigned Reg, int64_t NumBytes,
286                          const TargetInstrInfo *TII) {
287  while (NumBytes) {
288    unsigned Opcode;
289    int64_t ThisVal = NumBytes;
290    if (isInt<16>(NumBytes))
291      Opcode = SystemZ::AGHI;
292    else {
293      Opcode = SystemZ::AGFI;
294      // Make sure we maintain 8-byte stack alignment.
295      int64_t MinVal = -int64_t(1) << 31;
296      int64_t MaxVal = (int64_t(1) << 31) - 8;
297      if (ThisVal < MinVal)
298        ThisVal = MinVal;
299      else if (ThisVal > MaxVal)
300        ThisVal = MaxVal;
301    }
302    MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
303      .addReg(Reg).addImm(ThisVal);
304    // The CC implicit def is dead.
305    MI->getOperand(3).setIsDead();
306    NumBytes -= ThisVal;
307  }
308}
309
310void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const {
311  MachineBasicBlock &MBB = MF.front();
312  MachineFrameInfo *MFFrame = MF.getFrameInfo();
313  auto *ZII =
314    static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo());
315  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
316  MachineBasicBlock::iterator MBBI = MBB.begin();
317  MachineModuleInfo &MMI = MF.getMMI();
318  const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
319  const std::vector<CalleeSavedInfo> &CSI = MFFrame->getCalleeSavedInfo();
320  bool HasFP = hasFP(MF);
321  DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
322
323  // The current offset of the stack pointer from the CFA.
324  int64_t SPOffsetFromCFA = -SystemZMC::CFAOffsetFromInitialSP;
325
326  if (ZFI->getLowSavedGPR()) {
327    // Skip over the GPR saves.
328    if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
329      ++MBBI;
330    else
331      llvm_unreachable("Couldn't skip over GPR saves");
332
333    // Add CFI for the GPR saves.
334    for (auto &Save : CSI) {
335      unsigned Reg = Save.getReg();
336      if (SystemZ::GR64BitRegClass.contains(Reg)) {
337        int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
338        unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
339            nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
340        BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
341            .addCFIIndex(CFIIndex);
342      }
343    }
344  }
345
346  uint64_t StackSize = getAllocatedStackSize(MF);
347  if (StackSize) {
348    // Allocate StackSize bytes.
349    int64_t Delta = -int64_t(StackSize);
350    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
351
352    // Add CFI for the allocation.
353    unsigned CFIIndex = MMI.addFrameInst(
354        MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
355    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
356        .addCFIIndex(CFIIndex);
357    SPOffsetFromCFA += Delta;
358  }
359
360  if (HasFP) {
361    // Copy the base of the frame to R11.
362    BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
363      .addReg(SystemZ::R15D);
364
365    // Add CFI for the new frame location.
366    unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
367    unsigned CFIIndex = MMI.addFrameInst(
368        MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
369    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
370        .addCFIIndex(CFIIndex);
371
372    // Mark the FramePtr as live at the beginning of every block except
373    // the entry block.  (We'll have marked R11 as live on entry when
374    // saving the GPRs.)
375    for (auto I = std::next(MF.begin()), E = MF.end(); I != E; ++I)
376      I->addLiveIn(SystemZ::R11D);
377  }
378
379  // Skip over the FPR saves.
380  SmallVector<unsigned, 8> CFIIndexes;
381  for (auto &Save : CSI) {
382    unsigned Reg = Save.getReg();
383    if (SystemZ::FP64BitRegClass.contains(Reg)) {
384      if (MBBI != MBB.end() &&
385          (MBBI->getOpcode() == SystemZ::STD ||
386           MBBI->getOpcode() == SystemZ::STDY))
387        ++MBBI;
388      else
389        llvm_unreachable("Couldn't skip over FPR save");
390
391      // Add CFI for the this save.
392      unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
393      int64_t Offset = getFrameIndexOffset(MF, Save.getFrameIdx());
394      unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
395          nullptr, DwarfReg, SPOffsetFromCFA + Offset));
396      CFIIndexes.push_back(CFIIndex);
397    }
398  }
399  // Complete the CFI for the FPR saves, modelling them as taking effect
400  // after the last save.
401  for (auto CFIIndex : CFIIndexes) {
402    BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
403        .addCFIIndex(CFIIndex);
404  }
405}
406
407void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
408                                        MachineBasicBlock &MBB) const {
409  MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
410  auto *ZII =
411    static_cast<const SystemZInstrInfo*>(MF.getTarget().getInstrInfo());
412  SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
413
414  // Skip the return instruction.
415  assert(MBBI->isReturn() && "Can only insert epilogue into returning blocks");
416
417  uint64_t StackSize = getAllocatedStackSize(MF);
418  if (ZFI->getLowSavedGPR()) {
419    --MBBI;
420    unsigned Opcode = MBBI->getOpcode();
421    if (Opcode != SystemZ::LMG)
422      llvm_unreachable("Expected to see callee-save register restore code");
423
424    unsigned AddrOpNo = 2;
425    DebugLoc DL = MBBI->getDebugLoc();
426    uint64_t Offset = StackSize + MBBI->getOperand(AddrOpNo + 1).getImm();
427    unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
428
429    // If the offset is too large, use the largest stack-aligned offset
430    // and add the rest to the base register (the stack or frame pointer).
431    if (!NewOpcode) {
432      uint64_t NumBytes = Offset - 0x7fff8;
433      emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
434                    NumBytes, ZII);
435      Offset -= NumBytes;
436      NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
437      assert(NewOpcode && "No restore instruction available");
438    }
439
440    MBBI->setDesc(ZII->get(NewOpcode));
441    MBBI->getOperand(AddrOpNo + 1).ChangeToImmediate(Offset);
442  } else if (StackSize) {
443    DebugLoc DL = MBBI->getDebugLoc();
444    emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
445  }
446}
447
448bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const {
449  return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
450          MF.getFrameInfo()->hasVarSizedObjects() ||
451          MF.getInfo<SystemZMachineFunctionInfo>()->getManipulatesSP());
452}
453
454int SystemZFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
455                                              int FI) const {
456  const MachineFrameInfo *MFFrame = MF.getFrameInfo();
457
458  // Start with the offset of FI from the top of the caller-allocated frame
459  // (i.e. the top of the 160 bytes allocated by the caller).  This initial
460  // offset is therefore negative.
461  int64_t Offset = (MFFrame->getObjectOffset(FI) +
462                    MFFrame->getOffsetAdjustment());
463
464  // Make the offset relative to the incoming stack pointer.
465  Offset -= getOffsetOfLocalArea();
466
467  // Make the offset relative to the bottom of the frame.
468  Offset += getAllocatedStackSize(MF);
469
470  return Offset;
471}
472
473uint64_t SystemZFrameLowering::
474getAllocatedStackSize(const MachineFunction &MF) const {
475  const MachineFrameInfo *MFFrame = MF.getFrameInfo();
476
477  // Start with the size of the local variables and spill slots.
478  uint64_t StackSize = MFFrame->getStackSize();
479
480  // We need to allocate the ABI-defined 160-byte base area whenever
481  // we allocate stack space for our own use and whenever we call another
482  // function.
483  if (StackSize || MFFrame->hasVarSizedObjects() || MFFrame->hasCalls())
484    StackSize += SystemZMC::CallFrameSize;
485
486  return StackSize;
487}
488
489bool
490SystemZFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
491  // The ABI requires us to allocate 160 bytes of stack space for the callee,
492  // with any outgoing stack arguments being placed above that.  It seems
493  // better to make that area a permanent feature of the frame even if
494  // we're using a frame pointer.
495  return true;
496}
497
498void SystemZFrameLowering::
499eliminateCallFramePseudoInstr(MachineFunction &MF,
500                              MachineBasicBlock &MBB,
501                              MachineBasicBlock::iterator MI) const {
502  switch (MI->getOpcode()) {
503  case SystemZ::ADJCALLSTACKDOWN:
504  case SystemZ::ADJCALLSTACKUP:
505    assert(hasReservedCallFrame(MF) &&
506           "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
507    MBB.erase(MI);
508    break;
509
510  default:
511    llvm_unreachable("Unexpected call frame instruction");
512  }
513}
514