Cross Reference: /external/qemu/disas/ppc.c

Lines Matching defs:SH
753   /* The SH field in an X or M form instruction.  */
754 #define SH RSO + 1
757 #define EVUIMM SH
760   /* The SH field in an MD form instruction.  This is split.  */
761 #define SH6 SH + 1
765   /* The SH field of the tlbwe instruction, which is optional.  */
883   /* SH field starting at bit position 16.  */
1479 /* The SH field in an MD form instruction.  This is split.  */
1693 /* An M_MASK with the SH and ME fields fixed.  */
1703 /* An MD_MASK with the SH field fixed.  */
1795 /* An X form tlb instruction with the SH field specified.  */
3326 { "rlwimi",  M(20,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3327 { "rlimi",   M(20,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3329 { "rlwimi.", M(20,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3330 { "rlimi.",  M(20,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3332 { "rotlwi",  MME(21,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, SH } },
3334 { "rlwinm",  M(21,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3335 { "rlinm",   M(21,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3336 { "rotlwi.", MME(21,31,1), MMBME_MASK,	PPCCOM,		{ RA,RS,SH } },
3338 { "rlwinm.", M(21,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3339 { "rlinm.",  M(21,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3665 { "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
3666 { "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
3746 { "slliq",   XRC(31,248,0), X_MASK,	M601,		{ RA, RS, SH } },
3747 { "slliq.",  XRC(31,248,1), X_MASK,	M601,		{ RA, RS, SH } },
4460 { "sriq",    XRC(31,696,0), X_MASK,	M601,		{ RA, RS, SH } },
4461 { "sriq.",   XRC(31,696,1), X_MASK,	M601,		{ RA, RS, SH } },
4484 { "srliq",   XRC(31,760,0), X_MASK,	M601,		{ RA, RS, SH } },
4485 { "srliq.",  XRC(31,760,1), X_MASK,	M601,		{ RA, RS, SH } },
4518 { "srawi",   XRC(31,824,0), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4519 { "srai",    XRC(31,824,0), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4520 { "srawi.",  XRC(31,824,1), X_MASK,	PPCCOM,		{ RA, RS, SH } },
4521 { "srai.",   XRC(31,824,1), X_MASK,	PWRCOM,		{ RA, RS, SH } },
4566 { "sraiq",   XRC(31,952,0), X_MASK,	M601,		{ RA, RS, SH } },
4567 { "sraiq.",  XRC(31,952,1), X_MASK,	M601,		{ RA, RS, SH } },