1/* ppc-dis.c -- Disassemble PowerPC instructions
2   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
3   Free Software Foundation, Inc.
4   Written by Ian Lance Taylor, Cygnus Support
5
6This file is part of GDB, GAS, and the GNU binutils.
7
8GDB, GAS, and the GNU binutils are free software; you can redistribute
9them and/or modify them under the terms of the GNU General Public
10License as published by the Free Software Foundation; either version
112, or (at your option) any later version.
12
13GDB, GAS, and the GNU binutils are distributed in the hope that they
14will be useful, but WITHOUT ANY WARRANTY; without even the implied
15warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
16the GNU General Public License for more details.
17
18You should have received a copy of the GNU General Public License
19along with this file; see the file COPYING.  If not,
20see <http://www.gnu.org/licenses/>.  */
21#include "disas/bfd.h"
22#define BFD_DEFAULT_TARGET_SIZE 64
23
24/* ppc.h -- Header file for PowerPC opcode table
25   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
26   2007 Free Software Foundation, Inc.
27   Written by Ian Lance Taylor, Cygnus Support
28
29This file is part of GDB, GAS, and the GNU binutils.
30
31GDB, GAS, and the GNU binutils are free software; you can redistribute
32them and/or modify them under the terms of the GNU General Public
33License as published by the Free Software Foundation; either version
341, or (at your option) any later version.
35
36GDB, GAS, and the GNU binutils are distributed in the hope that they
37will be useful, but WITHOUT ANY WARRANTY; without even the implied
38warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
39the GNU General Public License for more details.
40
41You should have received a copy of the GNU General Public License
42along with this file; see the file COPYING.  If not,
43see <http://www.gnu.org/licenses/>.  */
44
45/* The opcode table is an array of struct powerpc_opcode.  */
46
47struct powerpc_opcode
48{
49  /* The opcode name.  */
50  const char *name;
51
52  /* The opcode itself.  Those bits which will be filled in with
53     operands are zeroes.  */
54  unsigned long opcode;
55
56  /* The opcode mask.  This is used by the disassembler.  This is a
57     mask containing ones indicating those bits which must match the
58     opcode field, and zeroes indicating those bits which need not
59     match (and are presumably filled in by operands).  */
60  unsigned long mask;
61
62  /* One bit flags for the opcode.  These are used to indicate which
63     specific processors support the instructions.  The defined values
64     are listed below.  */
65  unsigned long flags;
66
67  /* An array of operand codes.  Each code is an index into the
68     operand table.  They appear in the order which the operands must
69     appear in assembly code, and are terminated by a zero.  */
70  unsigned char operands[8];
71};
72
73/* The table itself is sorted by major opcode number, and is otherwise
74   in the order in which the disassembler should consider
75   instructions.  */
76extern const struct powerpc_opcode powerpc_opcodes[];
77extern const int powerpc_num_opcodes;
78
79/* Values defined for the flags field of a struct powerpc_opcode.  */
80
81/* Opcode is defined for the PowerPC architecture.  */
82#define PPC_OPCODE_PPC			 1
83
84/* Opcode is defined for the POWER (RS/6000) architecture.  */
85#define PPC_OPCODE_POWER		 2
86
87/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
88#define PPC_OPCODE_POWER2		 4
89
90/* Opcode is only defined on 32 bit architectures.  */
91#define PPC_OPCODE_32			 8
92
93/* Opcode is only defined on 64 bit architectures.  */
94#define PPC_OPCODE_64		      0x10
95
96/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
97   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
98   but it also supports many additional POWER instructions.  */
99#define PPC_OPCODE_601		      0x20
100
101/* Opcode is supported in both the Power and PowerPC architectures
102   (ie, compiler's -mcpu=common or assembler's -mcom).  */
103#define PPC_OPCODE_COMMON	      0x40
104
105/* Opcode is supported for any Power or PowerPC platform (this is
106   for the assembler's -many option, and it eliminates duplicates).  */
107#define PPC_OPCODE_ANY		      0x80
108
109/* Opcode is supported as part of the 64-bit bridge.  */
110#define PPC_OPCODE_64_BRIDGE	     0x100
111
112/* Opcode is supported by Altivec Vector Unit */
113#define PPC_OPCODE_ALTIVEC	     0x200
114
115/* Opcode is supported by PowerPC 403 processor.  */
116#define PPC_OPCODE_403		     0x400
117
118/* Opcode is supported by PowerPC BookE processor.  */
119#define PPC_OPCODE_BOOKE	     0x800
120
121/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
122#define PPC_OPCODE_BOOKE64	    0x1000
123
124/* Opcode is supported by PowerPC 440 processor.  */
125#define PPC_OPCODE_440		    0x2000
126
127/* Opcode is only supported by Power4 architecture.  */
128#define PPC_OPCODE_POWER4	    0x4000
129
130/* Opcode isn't supported by Power4 architecture.  */
131#define PPC_OPCODE_NOPOWER4	    0x8000
132
133/* Opcode is only supported by POWERPC Classic architecture.  */
134#define PPC_OPCODE_CLASSIC	   0x10000
135
136/* Opcode is only supported by e500x2 Core.  */
137#define PPC_OPCODE_SPE		   0x20000
138
139/* Opcode is supported by e500x2 Integer select APU.  */
140#define PPC_OPCODE_ISEL		   0x40000
141
142/* Opcode is an e500 SPE floating point instruction.  */
143#define PPC_OPCODE_EFS		   0x80000
144
145/* Opcode is supported by branch locking APU.  */
146#define PPC_OPCODE_BRLOCK	  0x100000
147
148/* Opcode is supported by performance monitor APU.  */
149#define PPC_OPCODE_PMR		  0x200000
150
151/* Opcode is supported by cache locking APU.  */
152#define PPC_OPCODE_CACHELCK	  0x400000
153
154/* Opcode is supported by machine check APU.  */
155#define PPC_OPCODE_RFMCI	  0x800000
156
157/* Opcode is only supported by Power5 architecture.  */
158#define PPC_OPCODE_POWER5	 0x1000000
159
160/* Opcode is supported by PowerPC e300 family.  */
161#define PPC_OPCODE_E300          0x2000000
162
163/* Opcode is only supported by Power6 architecture.  */
164#define PPC_OPCODE_POWER6	 0x4000000
165
166/* Opcode is only supported by PowerPC Cell family.  */
167#define PPC_OPCODE_CELL		 0x8000000
168
169/* A macro to extract the major opcode from an instruction.  */
170#define PPC_OP(i) (((i) >> 26) & 0x3f)
171
172/* The operands table is an array of struct powerpc_operand.  */
173
174struct powerpc_operand
175{
176  /* A bitmask of bits in the operand.  */
177  unsigned int bitm;
178
179  /* How far the operand is left shifted in the instruction.
180     -1 to indicate that BITM and SHIFT cannot be used to determine
181     where the operand goes in the insn.  */
182  int shift;
183
184  /* Insertion function.  This is used by the assembler.  To insert an
185     operand value into an instruction, check this field.
186
187     If it is NULL, execute
188	 i |= (op & o->bitm) << o->shift;
189     (i is the instruction which we are filling in, o is a pointer to
190     this structure, and op is the operand value).
191
192     If this field is not NULL, then simply call it with the
193     instruction and the operand value.  It will return the new value
194     of the instruction.  If the ERRMSG argument is not NULL, then if
195     the operand value is illegal, *ERRMSG will be set to a warning
196     string (the operand will be inserted in any case).  If the
197     operand value is legal, *ERRMSG will be unchanged (most operands
198     can accept any value).  */
199  unsigned long (*insert)
200    (unsigned long instruction, long op, int dialect, const char **errmsg);
201
202  /* Extraction function.  This is used by the disassembler.  To
203     extract this operand type from an instruction, check this field.
204
205     If it is NULL, compute
206	 op = (i >> o->shift) & o->bitm;
207	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
208	   sign_extend (op);
209     (i is the instruction, o is a pointer to this structure, and op
210     is the result).
211
212     If this field is not NULL, then simply call it with the
213     instruction value.  It will return the value of the operand.  If
214     the INVALID argument is not NULL, *INVALID will be set to
215     non-zero if this operand type can not actually be extracted from
216     this operand (i.e., the instruction does not match).  If the
217     operand is valid, *INVALID will not be changed.  */
218  long (*extract) (unsigned long instruction, int dialect, int *invalid);
219
220  /* One bit syntax flags.  */
221  unsigned long flags;
222};
223
224/* Elements in the table are retrieved by indexing with values from
225   the operands field of the powerpc_opcodes table.  */
226
227extern const struct powerpc_operand powerpc_operands[];
228extern const unsigned int num_powerpc_operands;
229
230/* Values defined for the flags field of a struct powerpc_operand.  */
231
232/* This operand takes signed values.  */
233#define PPC_OPERAND_SIGNED (0x1)
234
235/* This operand takes signed values, but also accepts a full positive
236   range of values when running in 32 bit mode.  That is, if bits is
237   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
238   this flag is ignored.  */
239#define PPC_OPERAND_SIGNOPT (0x2)
240
241/* This operand does not actually exist in the assembler input.  This
242   is used to support extended mnemonics such as mr, for which two
243   operands fields are identical.  The assembler should call the
244   insert function with any op value.  The disassembler should call
245   the extract function, ignore the return value, and check the value
246   placed in the valid argument.  */
247#define PPC_OPERAND_FAKE (0x4)
248
249/* The next operand should be wrapped in parentheses rather than
250   separated from this one by a comma.  This is used for the load and
251   store instructions which want their operands to look like
252       reg,displacement(reg)
253   */
254#define PPC_OPERAND_PARENS (0x8)
255
256/* This operand may use the symbolic names for the CR fields, which
257   are
258       lt  0	gt  1	eq  2	so  3	un  3
259       cr0 0	cr1 1	cr2 2	cr3 3
260       cr4 4	cr5 5	cr6 6	cr7 7
261   These may be combined arithmetically, as in cr2*4+gt.  These are
262   only supported on the PowerPC, not the POWER.  */
263#define PPC_OPERAND_CR (0x10)
264
265/* This operand names a register.  The disassembler uses this to print
266   register names with a leading 'r'.  */
267#define PPC_OPERAND_GPR (0x20)
268
269/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
270#define PPC_OPERAND_GPR_0 (0x40)
271
272/* This operand names a floating point register.  The disassembler
273   prints these with a leading 'f'.  */
274#define PPC_OPERAND_FPR (0x80)
275
276/* This operand is a relative branch displacement.  The disassembler
277   prints these symbolically if possible.  */
278#define PPC_OPERAND_RELATIVE (0x100)
279
280/* This operand is an absolute branch address.  The disassembler
281   prints these symbolically if possible.  */
282#define PPC_OPERAND_ABSOLUTE (0x200)
283
284/* This operand is optional, and is zero if omitted.  This is used for
285   example, in the optional BF field in the comparison instructions.  The
286   assembler must count the number of operands remaining on the line,
287   and the number of operands remaining for the opcode, and decide
288   whether this operand is present or not.  The disassembler should
289   print this operand out only if it is not zero.  */
290#define PPC_OPERAND_OPTIONAL (0x400)
291
292/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
293   is omitted, then for the next operand use this operand value plus
294   1, ignoring the next operand field for the opcode.  This wretched
295   hack is needed because the Power rotate instructions can take
296   either 4 or 5 operands.  The disassembler should print this operand
297   out regardless of the PPC_OPERAND_OPTIONAL field.  */
298#define PPC_OPERAND_NEXT (0x800)
299
300/* This operand should be regarded as a negative number for the
301   purposes of overflow checking (i.e., the normal most negative
302   number is disallowed and one more than the normal most positive
303   number is allowed).  This flag will only be set for a signed
304   operand.  */
305#define PPC_OPERAND_NEGATIVE (0x1000)
306
307/* This operand names a vector unit register.  The disassembler
308   prints these with a leading 'v'.  */
309#define PPC_OPERAND_VR (0x2000)
310
311/* This operand is for the DS field in a DS form instruction.  */
312#define PPC_OPERAND_DS (0x4000)
313
314/* This operand is for the DQ field in a DQ form instruction.  */
315#define PPC_OPERAND_DQ (0x8000)
316
317/* Valid range of operand is 0..n rather than 0..n-1.  */
318#define PPC_OPERAND_PLUS1 (0x10000)
319
320/* The POWER and PowerPC assemblers use a few macros.  We keep them
321   with the operands table for simplicity.  The macro table is an
322   array of struct powerpc_macro.  */
323
324struct powerpc_macro
325{
326  /* The macro name.  */
327  const char *name;
328
329  /* The number of operands the macro takes.  */
330  unsigned int operands;
331
332  /* One bit flags for the opcode.  These are used to indicate which
333     specific processors support the instructions.  The values are the
334     same as those for the struct powerpc_opcode flags field.  */
335  unsigned long flags;
336
337  /* A format string to turn the macro into a normal instruction.
338     Each %N in the string is replaced with operand number N (zero
339     based).  */
340  const char *format;
341};
342
343extern const struct powerpc_macro powerpc_macros[];
344extern const int powerpc_num_macros;
345
346/* ppc-opc.c -- PowerPC opcode list
347   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
348   2005, 2006, 2007 Free Software Foundation, Inc.
349   Written by Ian Lance Taylor, Cygnus Support
350
351   This file is part of GDB, GAS, and the GNU binutils.
352
353   GDB, GAS, and the GNU binutils are free software; you can redistribute
354   them and/or modify them under the terms of the GNU General Public
355   License as published by the Free Software Foundation; either version
356   2, or (at your option) any later version.
357
358   GDB, GAS, and the GNU binutils are distributed in the hope that they
359   will be useful, but WITHOUT ANY WARRANTY; without even the implied
360   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
361   the GNU General Public License for more details.
362
363   You should have received a copy of the GNU General Public License
364   along with this file; see the file COPYING.
365   If not, see <http://www.gnu.org/licenses/>.  */
366
367/* This file holds the PowerPC opcode table.  The opcode table
368   includes almost all of the extended instruction mnemonics.  This
369   permits the disassembler to use them, and simplifies the assembler
370   logic, at the cost of increasing the table size.  The table is
371   strictly constant data, so the compiler should be able to put it in
372   the .text section.
373
374   This file also holds the operand table.  All knowledge about
375   inserting operands into instructions and vice-versa is kept in this
376   file.  */
377
378/* Local insertion and extraction functions.  */
379
380static unsigned long insert_bat (unsigned long, long, int, const char **);
381static long extract_bat (unsigned long, int, int *);
382static unsigned long insert_bba (unsigned long, long, int, const char **);
383static long extract_bba (unsigned long, int, int *);
384static unsigned long insert_bdm (unsigned long, long, int, const char **);
385static long extract_bdm (unsigned long, int, int *);
386static unsigned long insert_bdp (unsigned long, long, int, const char **);
387static long extract_bdp (unsigned long, int, int *);
388static unsigned long insert_bo (unsigned long, long, int, const char **);
389static long extract_bo (unsigned long, int, int *);
390static unsigned long insert_boe (unsigned long, long, int, const char **);
391static long extract_boe (unsigned long, int, int *);
392static unsigned long insert_fxm (unsigned long, long, int, const char **);
393static long extract_fxm (unsigned long, int, int *);
394static unsigned long insert_mbe (unsigned long, long, int, const char **);
395static long extract_mbe (unsigned long, int, int *);
396static unsigned long insert_mb6 (unsigned long, long, int, const char **);
397static long extract_mb6 (unsigned long, int, int *);
398static long extract_nb (unsigned long, int, int *);
399static unsigned long insert_nsi (unsigned long, long, int, const char **);
400static long extract_nsi (unsigned long, int, int *);
401static unsigned long insert_ral (unsigned long, long, int, const char **);
402static unsigned long insert_ram (unsigned long, long, int, const char **);
403static unsigned long insert_raq (unsigned long, long, int, const char **);
404static unsigned long insert_ras (unsigned long, long, int, const char **);
405static unsigned long insert_rbs (unsigned long, long, int, const char **);
406static long extract_rbs (unsigned long, int, int *);
407static unsigned long insert_sh6 (unsigned long, long, int, const char **);
408static long extract_sh6 (unsigned long, int, int *);
409static unsigned long insert_spr (unsigned long, long, int, const char **);
410static long extract_spr (unsigned long, int, int *);
411static unsigned long insert_sprg (unsigned long, long, int, const char **);
412static long extract_sprg (unsigned long, int, int *);
413static unsigned long insert_tbr (unsigned long, long, int, const char **);
414static long extract_tbr (unsigned long, int, int *);
415
416/* The operands table.
417
418   The fields are bitm, shift, insert, extract, flags.
419
420   We used to put parens around the various additions, like the one
421   for BA just below.  However, that caused trouble with feeble
422   compilers with a limit on depth of a parenthesized expression, like
423   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
424   omit the parens, since the macros are never used in a context where
425   the addition will be ambiguous.  */
426
427const struct powerpc_operand powerpc_operands[] =
428{
429  /* The zero index is used to indicate the end of the list of
430     operands.  */
431#define UNUSED 0
432  { 0, 0, NULL, NULL, 0 },
433
434  /* The BA field in an XL form instruction.  */
435#define BA UNUSED + 1
436  /* The BI field in a B form or XL form instruction.  */
437#define BI BA
438#define BI_MASK (0x1f << 16)
439  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
440
441  /* The BA field in an XL form instruction when it must be the same
442     as the BT field in the same instruction.  */
443#define BAT BA + 1
444  { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
445
446  /* The BB field in an XL form instruction.  */
447#define BB BAT + 1
448#define BB_MASK (0x1f << 11)
449  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
450
451  /* The BB field in an XL form instruction when it must be the same
452     as the BA field in the same instruction.  */
453#define BBA BB + 1
454  { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
455
456  /* The BD field in a B form instruction.  The lower two bits are
457     forced to zero.  */
458#define BD BBA + 1
459  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
460
461  /* The BD field in a B form instruction when absolute addressing is
462     used.  */
463#define BDA BD + 1
464  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
465
466  /* The BD field in a B form instruction when the - modifier is used.
467     This sets the y bit of the BO field appropriately.  */
468#define BDM BDA + 1
469  { 0xfffc, 0, insert_bdm, extract_bdm,
470      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
471
472  /* The BD field in a B form instruction when the - modifier is used
473     and absolute address is used.  */
474#define BDMA BDM + 1
475  { 0xfffc, 0, insert_bdm, extract_bdm,
476      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
477
478  /* The BD field in a B form instruction when the + modifier is used.
479     This sets the y bit of the BO field appropriately.  */
480#define BDP BDMA + 1
481  { 0xfffc, 0, insert_bdp, extract_bdp,
482      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
483
484  /* The BD field in a B form instruction when the + modifier is used
485     and absolute addressing is used.  */
486#define BDPA BDP + 1
487  { 0xfffc, 0, insert_bdp, extract_bdp,
488      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
489
490  /* The BF field in an X or XL form instruction.  */
491#define BF BDPA + 1
492  /* The CRFD field in an X form instruction.  */
493#define CRFD BF
494  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
495
496  /* The BF field in an X or XL form instruction.  */
497#define BFF BF + 1
498  { 0x7, 23, NULL, NULL, 0 },
499
500  /* An optional BF field.  This is used for comparison instructions,
501     in which an omitted BF field is taken as zero.  */
502#define OBF BFF + 1
503  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
504
505  /* The BFA field in an X or XL form instruction.  */
506#define BFA OBF + 1
507  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
508
509  /* The BO field in a B form instruction.  Certain values are
510     illegal.  */
511#define BO BFA + 1
512#define BO_MASK (0x1f << 21)
513  { 0x1f, 21, insert_bo, extract_bo, 0 },
514
515  /* The BO field in a B form instruction when the + or - modifier is
516     used.  This is like the BO field, but it must be even.  */
517#define BOE BO + 1
518  { 0x1e, 21, insert_boe, extract_boe, 0 },
519
520#define BH BOE + 1
521  { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
522
523  /* The BT field in an X or XL form instruction.  */
524#define BT BH + 1
525  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
526
527  /* The condition register number portion of the BI field in a B form
528     or XL form instruction.  This is used for the extended
529     conditional branch mnemonics, which set the lower two bits of the
530     BI field.  This field is optional.  */
531#define CR BT + 1
532  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
533
534  /* The CRB field in an X form instruction.  */
535#define CRB CR + 1
536  /* The MB field in an M form instruction.  */
537#define MB CRB
538#define MB_MASK (0x1f << 6)
539  { 0x1f, 6, NULL, NULL, 0 },
540
541  /* The CRFS field in an X form instruction.  */
542#define CRFS CRB + 1
543  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
544
545  /* The CT field in an X form instruction.  */
546#define CT CRFS + 1
547  /* The MO field in an mbar instruction.  */
548#define MO CT
549  { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
550
551  /* The D field in a D form instruction.  This is a displacement off
552     a register, and implies that the next operand is a register in
553     parentheses.  */
554#define D CT + 1
555  { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
556
557  /* The DE field in a DE form instruction.  This is like D, but is 12
558     bits only.  */
559#define DE D + 1
560  { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
561
562  /* The DES field in a DES form instruction.  This is like DS, but is 14
563     bits only (12 stored.)  */
564#define DES DE + 1
565  { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
566
567  /* The DQ field in a DQ form instruction.  This is like D, but the
568     lower four bits are forced to zero. */
569#define DQ DES + 1
570  { 0xfff0, 0, NULL, NULL,
571    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
572
573  /* The DS field in a DS form instruction.  This is like D, but the
574     lower two bits are forced to zero.  */
575#undef DS
576#define DS DQ + 1
577  { 0xfffc, 0, NULL, NULL,
578    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
579
580  /* The E field in a wrteei instruction.  */
581#define E DS + 1
582  { 0x1, 15, NULL, NULL, 0 },
583
584  /* The FL1 field in a POWER SC form instruction.  */
585#define FL1 E + 1
586  /* The U field in an X form instruction.  */
587#define U FL1
588  { 0xf, 12, NULL, NULL, 0 },
589
590  /* The FL2 field in a POWER SC form instruction.  */
591#define FL2 FL1 + 1
592  { 0x7, 2, NULL, NULL, 0 },
593
594  /* The FLM field in an XFL form instruction.  */
595#define FLM FL2 + 1
596  { 0xff, 17, NULL, NULL, 0 },
597
598  /* The FRA field in an X or A form instruction.  */
599#define FRA FLM + 1
600#define FRA_MASK (0x1f << 16)
601  { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },
602
603  /* The FRB field in an X or A form instruction.  */
604#define FRB FRA + 1
605#define FRB_MASK (0x1f << 11)
606  { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },
607
608  /* The FRC field in an A form instruction.  */
609#define FRC FRB + 1
610#define FRC_MASK (0x1f << 6)
611  { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },
612
613  /* The FRS field in an X form instruction or the FRT field in a D, X
614     or A form instruction.  */
615#define FRS FRC + 1
616#define FRT FRS
617  { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },
618
619  /* The FXM field in an XFX instruction.  */
620#define FXM FRS + 1
621  { 0xff, 12, insert_fxm, extract_fxm, 0 },
622
623  /* Power4 version for mfcr.  */
624#define FXM4 FXM + 1
625  { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
626
627  /* The L field in a D or X form instruction.  */
628#define L FXM4 + 1
629  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
630
631  /* The LEV field in a POWER SVC form instruction.  */
632#define SVC_LEV L + 1
633  { 0x7f, 5, NULL, NULL, 0 },
634
635  /* The LEV field in an SC form instruction.  */
636#define LEV SVC_LEV + 1
637  { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
638
639  /* The LI field in an I form instruction.  The lower two bits are
640     forced to zero.  */
641#define LI LEV + 1
642  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
643
644  /* The LI field in an I form instruction when used as an absolute
645     address.  */
646#define LIA LI + 1
647  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
648
649  /* The LS field in an X (sync) form instruction.  */
650#define LS LIA + 1
651  { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
652
653  /* The ME field in an M form instruction.  */
654#define ME LS + 1
655#define ME_MASK (0x1f << 1)
656  { 0x1f, 1, NULL, NULL, 0 },
657
658  /* The MB and ME fields in an M form instruction expressed a single
659     operand which is a bitmask indicating which bits to select.  This
660     is a two operand form using PPC_OPERAND_NEXT.  See the
661     description in opcode/ppc.h for what this means.  */
662#define MBE ME + 1
663  { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
664  { -1, 0, insert_mbe, extract_mbe, 0 },
665
666  /* The MB or ME field in an MD or MDS form instruction.  The high
667     bit is wrapped to the low end.  */
668#define MB6 MBE + 2
669#define ME6 MB6
670#define MB6_MASK (0x3f << 5)
671  { 0x3f, 5, insert_mb6, extract_mb6, 0 },
672
673  /* The NB field in an X form instruction.  The value 32 is stored as
674     0.  */
675#define NB MB6 + 1
676  { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },
677
678  /* The NSI field in a D form instruction.  This is the same as the
679     SI field, only negated.  */
680#define NSI NB + 1
681  { 0xffff, 0, insert_nsi, extract_nsi,
682      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
683
684  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
685#define RA NSI + 1
686#define RA_MASK (0x1f << 16)
687  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
688
689  /* As above, but 0 in the RA field means zero, not r0.  */
690#define RA0 RA + 1
691  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },
692
693  /* The RA field in the DQ form lq instruction, which has special
694     value restrictions.  */
695#define RAQ RA0 + 1
696  { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },
697
698  /* The RA field in a D or X form instruction which is an updating
699     load, which means that the RA field may not be zero and may not
700     equal the RT field.  */
701#define RAL RAQ + 1
702  { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },
703
704  /* The RA field in an lmw instruction, which has special value
705     restrictions.  */
706#define RAM RAL + 1
707  { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },
708
709  /* The RA field in a D or X form instruction which is an updating
710     store or an updating floating point load, which means that the RA
711     field may not be zero.  */
712#define RAS RAM + 1
713  { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },
714
715  /* The RA field of the tlbwe instruction, which is optional.  */
716#define RAOPT RAS + 1
717  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
718
719  /* The RB field in an X, XO, M, or MDS form instruction.  */
720#define RB RAOPT + 1
721#define RB_MASK (0x1f << 11)
722  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },
723
724  /* The RB field in an X form instruction when it must be the same as
725     the RS field in the instruction.  This is used for extended
726     mnemonics like mr.  */
727#define RBS RB + 1
728  { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
729
730  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
731     instruction or the RT field in a D, DS, X, XFX or XO form
732     instruction.  */
733#define RS RBS + 1
734#define RT RS
735#define RT_MASK (0x1f << 21)
736  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
737
738  /* The RS and RT fields of the DS form stq instruction, which have
739     special value restrictions.  */
740#define RSQ RS + 1
741#define RTQ RSQ
742  { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },
743
744  /* The RS field of the tlbwe instruction, which is optional.  */
745#define RSO RSQ + 1
746#define RTO RSO
747  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
748
749  /* The SH field in an X or M form instruction.  */
750#define SH RSO + 1
751#define SH_MASK (0x1f << 11)
752  /* The other UIMM field in a EVX form instruction.  */
753#define EVUIMM SH
754  { 0x1f, 11, NULL, NULL, 0 },
755
756  /* The SH field in an MD form instruction.  This is split.  */
757#define SH6 SH + 1
758#define SH6_MASK ((0x1f << 11) | (1 << 1))
759  { 0x3f, -1, insert_sh6, extract_sh6, 0 },
760
761  /* The SH field of the tlbwe instruction, which is optional.  */
762#define SHO SH6 + 1
763  { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },
764
765  /* The SI field in a D form instruction.  */
766#define SI SHO + 1
767  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
768
769  /* The SI field in a D form instruction when we accept a wide range
770     of positive values.  */
771#define SISIGNOPT SI + 1
772  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
773
774  /* The SPR field in an XFX form instruction.  This is flipped--the
775     lower 5 bits are stored in the upper 5 and vice- versa.  */
776#define SPR SISIGNOPT + 1
777#define PMR SPR
778#define SPR_MASK (0x3ff << 11)
779  { 0x3ff, 11, insert_spr, extract_spr, 0 },
780
781  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
782#define SPRBAT SPR + 1
783#define SPRBAT_MASK (0x3 << 17)
784  { 0x3, 17, NULL, NULL, 0 },
785
786  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
787#define SPRG SPRBAT + 1
788  { 0x1f, 16, insert_sprg, extract_sprg, 0 },
789
790  /* The SR field in an X form instruction.  */
791#define SR SPRG + 1
792  { 0xf, 16, NULL, NULL, 0 },
793
794  /* The STRM field in an X AltiVec form instruction.  */
795#define STRM SR + 1
796  { 0x3, 21, NULL, NULL, 0 },
797
798  /* The SV field in a POWER SC form instruction.  */
799#define SV STRM + 1
800  { 0x3fff, 2, NULL, NULL, 0 },
801
802  /* The TBR field in an XFX form instruction.  This is like the SPR
803     field, but it is optional.  */
804#define TBR SV + 1
805  { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
806
807  /* The TO field in a D or X form instruction.  */
808#define TO TBR + 1
809#define TO_MASK (0x1f << 21)
810  { 0x1f, 21, NULL, NULL, 0 },
811
812  /* The UI field in a D form instruction.  */
813#define UI TO + 1
814  { 0xffff, 0, NULL, NULL, 0 },
815
816  /* The VA field in a VA, VX or VXR form instruction.  */
817#define VA UI + 1
818  { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
819
820  /* The VB field in a VA, VX or VXR form instruction.  */
821#define VB VA + 1
822  { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },
823
824  /* The VC field in a VA form instruction.  */
825#define VC VB + 1
826  { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },
827
828  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
829#define VD VC + 1
830#define VS VD
831  { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },
832
833  /* The SIMM field in a VX form instruction.  */
834#define SIMM VD + 1
835  { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},
836
837  /* The UIMM field in a VX form instruction, and TE in Z form.  */
838#define UIMM SIMM + 1
839#define TE UIMM
840  { 0x1f, 16, NULL, NULL, 0 },
841
842  /* The SHB field in a VA form instruction.  */
843#define SHB UIMM + 1
844  { 0xf, 6, NULL, NULL, 0 },
845
846  /* The other UIMM field in a half word EVX form instruction.  */
847#define EVUIMM_2 SHB + 1
848  { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },
849
850  /* The other UIMM field in a word EVX form instruction.  */
851#define EVUIMM_4 EVUIMM_2 + 1
852  { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },
853
854  /* The other UIMM field in a double EVX form instruction.  */
855#define EVUIMM_8 EVUIMM_4 + 1
856  { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },
857
858  /* The WS field.  */
859#define WS EVUIMM_8 + 1
860  { 0x7, 11, NULL, NULL, 0 },
861
862  /* The L field in an mtmsrd or A form instruction or W in an X form.  */
863#define A_L WS + 1
864#define W A_L
865  { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
866
867#define RMC A_L + 1
868  { 0x3, 9, NULL, NULL, 0 },
869
870#define R RMC + 1
871  { 0x1, 16, NULL, NULL, 0 },
872
873#define SP R + 1
874  { 0x3, 19, NULL, NULL, 0 },
875
876#define S SP + 1
877  { 0x1, 20, NULL, NULL, 0 },
878
879  /* SH field starting at bit position 16.  */
880#define SH16 S + 1
881  /* The DCM and DGM fields in a Z form instruction.  */
882#define DCM SH16
883#define DGM DCM
884  { 0x3f, 10, NULL, NULL, 0 },
885
886  /* The EH field in larx instruction.  */
887#define EH SH16 + 1
888  { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
889
890  /* The L field in an mtfsf or XFL form instruction.  */
891#define XFL_L EH + 1
892  { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
893};
894
895const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
896					   / sizeof (powerpc_operands[0]));
897
898/* The functions used to insert and extract complicated operands.  */
899
900/* The BA field in an XL form instruction when it must be the same as
901   the BT field in the same instruction.  This operand is marked FAKE.
902   The insertion function just copies the BT field into the BA field,
903   and the extraction function just checks that the fields are the
904   same.  */
905
906static unsigned long
907insert_bat (unsigned long insn,
908	    long value ATTRIBUTE_UNUSED,
909	    int dialect ATTRIBUTE_UNUSED,
910	    const char **errmsg ATTRIBUTE_UNUSED)
911{
912  return insn | (((insn >> 21) & 0x1f) << 16);
913}
914
915static long
916extract_bat (unsigned long insn,
917	     int dialect ATTRIBUTE_UNUSED,
918	     int *invalid)
919{
920  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
921    *invalid = 1;
922  return 0;
923}
924
925/* The BB field in an XL form instruction when it must be the same as
926   the BA field in the same instruction.  This operand is marked FAKE.
927   The insertion function just copies the BA field into the BB field,
928   and the extraction function just checks that the fields are the
929   same.  */
930
931static unsigned long
932insert_bba (unsigned long insn,
933	    long value ATTRIBUTE_UNUSED,
934	    int dialect ATTRIBUTE_UNUSED,
935	    const char **errmsg ATTRIBUTE_UNUSED)
936{
937  return insn | (((insn >> 16) & 0x1f) << 11);
938}
939
940static long
941extract_bba (unsigned long insn,
942	     int dialect ATTRIBUTE_UNUSED,
943	     int *invalid)
944{
945  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
946    *invalid = 1;
947  return 0;
948}
949
950/* The BD field in a B form instruction when the - modifier is used.
951   This modifier means that the branch is not expected to be taken.
952   For chips built to versions of the architecture prior to version 2
953   (ie. not Power4 compatible), we set the y bit of the BO field to 1
954   if the offset is negative.  When extracting, we require that the y
955   bit be 1 and that the offset be positive, since if the y bit is 0
956   we just want to print the normal form of the instruction.
957   Power4 compatible targets use two bits, "a", and "t", instead of
958   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
959   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
960   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
961   for branch on CTR.  We only handle the taken/not-taken hint here.
962   Note that we don't relax the conditions tested here when
963   disassembling with -Many because insns using extract_bdm and
964   extract_bdp always occur in pairs.  One or the other will always
965   be valid.  */
966
967static unsigned long
968insert_bdm (unsigned long insn,
969	    long value,
970	    int dialect,
971	    const char **errmsg ATTRIBUTE_UNUSED)
972{
973  if ((dialect & PPC_OPCODE_POWER4) == 0)
974    {
975      if ((value & 0x8000) != 0)
976	insn |= 1 << 21;
977    }
978  else
979    {
980      if ((insn & (0x14 << 21)) == (0x04 << 21))
981	insn |= 0x02 << 21;
982      else if ((insn & (0x14 << 21)) == (0x10 << 21))
983	insn |= 0x08 << 21;
984    }
985  return insn | (value & 0xfffc);
986}
987
988static long
989extract_bdm (unsigned long insn,
990	     int dialect,
991	     int *invalid)
992{
993  if ((dialect & PPC_OPCODE_POWER4) == 0)
994    {
995      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
996	*invalid = 1;
997    }
998  else
999    {
1000      if ((insn & (0x17 << 21)) != (0x06 << 21)
1001	  && (insn & (0x1d << 21)) != (0x18 << 21))
1002	*invalid = 1;
1003    }
1004
1005  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1006}
1007
1008/* The BD field in a B form instruction when the + modifier is used.
1009   This is like BDM, above, except that the branch is expected to be
1010   taken.  */
1011
1012static unsigned long
1013insert_bdp (unsigned long insn,
1014	    long value,
1015	    int dialect,
1016	    const char **errmsg ATTRIBUTE_UNUSED)
1017{
1018  if ((dialect & PPC_OPCODE_POWER4) == 0)
1019    {
1020      if ((value & 0x8000) == 0)
1021	insn |= 1 << 21;
1022    }
1023  else
1024    {
1025      if ((insn & (0x14 << 21)) == (0x04 << 21))
1026	insn |= 0x03 << 21;
1027      else if ((insn & (0x14 << 21)) == (0x10 << 21))
1028	insn |= 0x09 << 21;
1029    }
1030  return insn | (value & 0xfffc);
1031}
1032
1033static long
1034extract_bdp (unsigned long insn,
1035	     int dialect,
1036	     int *invalid)
1037{
1038  if ((dialect & PPC_OPCODE_POWER4) == 0)
1039    {
1040      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
1041	*invalid = 1;
1042    }
1043  else
1044    {
1045      if ((insn & (0x17 << 21)) != (0x07 << 21)
1046	  && (insn & (0x1d << 21)) != (0x19 << 21))
1047	*invalid = 1;
1048    }
1049
1050  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1051}
1052
1053/* Check for legal values of a BO field.  */
1054
1055static int
1056valid_bo (long value, int dialect, int extract)
1057{
1058  if ((dialect & PPC_OPCODE_POWER4) == 0)
1059    {
1060      int valid;
1061      /* Certain encodings have bits that are required to be zero.
1062	 These are (z must be zero, y may be anything):
1063	     001zy
1064	     011zy
1065	     1z00y
1066	     1z01y
1067	     1z1zz
1068      */
1069      switch (value & 0x14)
1070	{
1071	default:
1072	case 0:
1073	  valid = 1;
1074	  break;
1075	case 0x4:
1076	  valid = (value & 0x2) == 0;
1077	  break;
1078	case 0x10:
1079	  valid = (value & 0x8) == 0;
1080	  break;
1081	case 0x14:
1082	  valid = value == 0x14;
1083	  break;
1084	}
1085      /* When disassembling with -Many, accept power4 encodings too.  */
1086      if (valid
1087	  || (dialect & PPC_OPCODE_ANY) == 0
1088	  || !extract)
1089	return valid;
1090    }
1091
1092  /* Certain encodings have bits that are required to be zero.
1093     These are (z must be zero, a & t may be anything):
1094	 0000z
1095	 0001z
1096	 0100z
1097	 0101z
1098	 001at
1099	 011at
1100	 1a00t
1101	 1a01t
1102	 1z1zz
1103  */
1104  if ((value & 0x14) == 0)
1105    return (value & 0x1) == 0;
1106  else if ((value & 0x14) == 0x14)
1107    return value == 0x14;
1108  else
1109    return 1;
1110}
1111
1112/* The BO field in a B form instruction.  Warn about attempts to set
1113   the field to an illegal value.  */
1114
1115static unsigned long
1116insert_bo (unsigned long insn,
1117	   long value,
1118	   int dialect,
1119	   const char **errmsg)
1120{
1121  if (!valid_bo (value, dialect, 0))
1122    *errmsg = _("invalid conditional option");
1123  return insn | ((value & 0x1f) << 21);
1124}
1125
1126static long
1127extract_bo (unsigned long insn,
1128	    int dialect,
1129	    int *invalid)
1130{
1131  long value;
1132
1133  value = (insn >> 21) & 0x1f;
1134  if (!valid_bo (value, dialect, 1))
1135    *invalid = 1;
1136  return value;
1137}
1138
1139/* The BO field in a B form instruction when the + or - modifier is
1140   used.  This is like the BO field, but it must be even.  When
1141   extracting it, we force it to be even.  */
1142
1143static unsigned long
1144insert_boe (unsigned long insn,
1145	    long value,
1146	    int dialect,
1147	    const char **errmsg)
1148{
1149  if (!valid_bo (value, dialect, 0))
1150    *errmsg = _("invalid conditional option");
1151  else if ((value & 1) != 0)
1152    *errmsg = _("attempt to set y bit when using + or - modifier");
1153
1154  return insn | ((value & 0x1f) << 21);
1155}
1156
1157static long
1158extract_boe (unsigned long insn,
1159	     int dialect,
1160	     int *invalid)
1161{
1162  long value;
1163
1164  value = (insn >> 21) & 0x1f;
1165  if (!valid_bo (value, dialect, 1))
1166    *invalid = 1;
1167  return value & 0x1e;
1168}
1169
1170/* FXM mask in mfcr and mtcrf instructions.  */
1171
1172static unsigned long
1173insert_fxm (unsigned long insn,
1174	    long value,
1175	    int dialect,
1176	    const char **errmsg)
1177{
1178  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
1179     one bit of the mask field is set.  */
1180  if ((insn & (1 << 20)) != 0)
1181    {
1182      if (value == 0 || (value & -value) != value)
1183	{
1184	  *errmsg = _("invalid mask field");
1185	  value = 0;
1186	}
1187    }
1188
1189  /* If the optional field on mfcr is missing that means we want to use
1190     the old form of the instruction that moves the whole cr.  In that
1191     case we'll have VALUE zero.  There doesn't seem to be a way to
1192     distinguish this from the case where someone writes mfcr %r3,0.  */
1193  else if (value == 0)
1194    ;
1195
1196  /* If only one bit of the FXM field is set, we can use the new form
1197     of the instruction, which is faster.  Unlike the Power4 branch hint
1198     encoding, this is not backward compatible.  Do not generate the
1199     new form unless -mpower4 has been given, or -many and the two
1200     operand form of mfcr was used.  */
1201  else if ((value & -value) == value
1202	   && ((dialect & PPC_OPCODE_POWER4) != 0
1203	       || ((dialect & PPC_OPCODE_ANY) != 0
1204		   && (insn & (0x3ff << 1)) == 19 << 1)))
1205    insn |= 1 << 20;
1206
1207  /* Any other value on mfcr is an error.  */
1208  else if ((insn & (0x3ff << 1)) == 19 << 1)
1209    {
1210      *errmsg = _("ignoring invalid mfcr mask");
1211      value = 0;
1212    }
1213
1214  return insn | ((value & 0xff) << 12);
1215}
1216
1217static long
1218extract_fxm (unsigned long insn,
1219	     int dialect ATTRIBUTE_UNUSED,
1220	     int *invalid)
1221{
1222  long mask = (insn >> 12) & 0xff;
1223
1224  /* Is this a Power4 insn?  */
1225  if ((insn & (1 << 20)) != 0)
1226    {
1227      /* Exactly one bit of MASK should be set.  */
1228      if (mask == 0 || (mask & -mask) != mask)
1229	*invalid = 1;
1230    }
1231
1232  /* Check that non-power4 form of mfcr has a zero MASK.  */
1233  else if ((insn & (0x3ff << 1)) == 19 << 1)
1234    {
1235      if (mask != 0)
1236	*invalid = 1;
1237    }
1238
1239  return mask;
1240}
1241
1242/* The MB and ME fields in an M form instruction expressed as a single
1243   operand which is itself a bitmask.  The extraction function always
1244   marks it as invalid, since we never want to recognize an
1245   instruction which uses a field of this type.  */
1246
1247static unsigned long
1248insert_mbe (unsigned long insn,
1249	    long value,
1250	    int dialect ATTRIBUTE_UNUSED,
1251	    const char **errmsg)
1252{
1253  unsigned long uval, mask;
1254  int mb, me, mx, count, last;
1255
1256  uval = value;
1257
1258  if (uval == 0)
1259    {
1260      *errmsg = _("illegal bitmask");
1261      return insn;
1262    }
1263
1264  mb = 0;
1265  me = 32;
1266  if ((uval & 1) != 0)
1267    last = 1;
1268  else
1269    last = 0;
1270  count = 0;
1271
1272  /* mb: location of last 0->1 transition */
1273  /* me: location of last 1->0 transition */
1274  /* count: # transitions */
1275
1276  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1277    {
1278      if ((uval & mask) && !last)
1279	{
1280	  ++count;
1281	  mb = mx;
1282	  last = 1;
1283	}
1284      else if (!(uval & mask) && last)
1285	{
1286	  ++count;
1287	  me = mx;
1288	  last = 0;
1289	}
1290    }
1291  if (me == 0)
1292    me = 32;
1293
1294  if (count != 2 && (count != 0 || ! last))
1295    *errmsg = _("illegal bitmask");
1296
1297  return insn | (mb << 6) | ((me - 1) << 1);
1298}
1299
1300static long
1301extract_mbe (unsigned long insn,
1302	     int dialect ATTRIBUTE_UNUSED,
1303	     int *invalid)
1304{
1305  long ret;
1306  int mb, me;
1307  int i;
1308
1309  *invalid = 1;
1310
1311  mb = (insn >> 6) & 0x1f;
1312  me = (insn >> 1) & 0x1f;
1313  if (mb < me + 1)
1314    {
1315      ret = 0;
1316      for (i = mb; i <= me; i++)
1317	ret |= 1L << (31 - i);
1318    }
1319  else if (mb == me + 1)
1320    ret = ~0;
1321  else /* (mb > me + 1) */
1322    {
1323      ret = ~0;
1324      for (i = me + 1; i < mb; i++)
1325	ret &= ~(1L << (31 - i));
1326    }
1327  return ret;
1328}
1329
1330/* The MB or ME field in an MD or MDS form instruction.  The high bit
1331   is wrapped to the low end.  */
1332
1333static unsigned long
1334insert_mb6 (unsigned long insn,
1335	    long value,
1336	    int dialect ATTRIBUTE_UNUSED,
1337	    const char **errmsg ATTRIBUTE_UNUSED)
1338{
1339  return insn | ((value & 0x1f) << 6) | (value & 0x20);
1340}
1341
1342static long
1343extract_mb6 (unsigned long insn,
1344	     int dialect ATTRIBUTE_UNUSED,
1345	     int *invalid ATTRIBUTE_UNUSED)
1346{
1347  return ((insn >> 6) & 0x1f) | (insn & 0x20);
1348}
1349
1350/* The NB field in an X form instruction.  The value 32 is stored as
1351   0.  */
1352
1353static long
1354extract_nb (unsigned long insn,
1355	    int dialect ATTRIBUTE_UNUSED,
1356	    int *invalid ATTRIBUTE_UNUSED)
1357{
1358  long ret;
1359
1360  ret = (insn >> 11) & 0x1f;
1361  if (ret == 0)
1362    ret = 32;
1363  return ret;
1364}
1365
1366/* The NSI field in a D form instruction.  This is the same as the SI
1367   field, only negated.  The extraction function always marks it as
1368   invalid, since we never want to recognize an instruction which uses
1369   a field of this type.  */
1370
1371static unsigned long
1372insert_nsi (unsigned long insn,
1373	    long value,
1374	    int dialect ATTRIBUTE_UNUSED,
1375	    const char **errmsg ATTRIBUTE_UNUSED)
1376{
1377  return insn | (-value & 0xffff);
1378}
1379
1380static long
1381extract_nsi (unsigned long insn,
1382	     int dialect ATTRIBUTE_UNUSED,
1383	     int *invalid)
1384{
1385  *invalid = 1;
1386  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1387}
1388
1389/* The RA field in a D or X form instruction which is an updating
1390   load, which means that the RA field may not be zero and may not
1391   equal the RT field.  */
1392
1393static unsigned long
1394insert_ral (unsigned long insn,
1395	    long value,
1396	    int dialect ATTRIBUTE_UNUSED,
1397	    const char **errmsg)
1398{
1399  if (value == 0
1400      || (unsigned long) value == ((insn >> 21) & 0x1f))
1401    *errmsg = "invalid register operand when updating";
1402  return insn | ((value & 0x1f) << 16);
1403}
1404
1405/* The RA field in an lmw instruction, which has special value
1406   restrictions.  */
1407
1408static unsigned long
1409insert_ram (unsigned long insn,
1410	    long value,
1411	    int dialect ATTRIBUTE_UNUSED,
1412	    const char **errmsg)
1413{
1414  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1415    *errmsg = _("index register in load range");
1416  return insn | ((value & 0x1f) << 16);
1417}
1418
1419/* The RA field in the DQ form lq instruction, which has special
1420   value restrictions.  */
1421
1422static unsigned long
1423insert_raq (unsigned long insn,
1424	    long value,
1425	    int dialect ATTRIBUTE_UNUSED,
1426	    const char **errmsg)
1427{
1428  long rtvalue = (insn & RT_MASK) >> 21;
1429
1430  if (value == rtvalue)
1431    *errmsg = _("source and target register operands must be different");
1432  return insn | ((value & 0x1f) << 16);
1433}
1434
1435/* The RA field in a D or X form instruction which is an updating
1436   store or an updating floating point load, which means that the RA
1437   field may not be zero.  */
1438
1439static unsigned long
1440insert_ras (unsigned long insn,
1441	    long value,
1442	    int dialect ATTRIBUTE_UNUSED,
1443	    const char **errmsg)
1444{
1445  if (value == 0)
1446    *errmsg = _("invalid register operand when updating");
1447  return insn | ((value & 0x1f) << 16);
1448}
1449
1450/* The RB field in an X form instruction when it must be the same as
1451   the RS field in the instruction.  This is used for extended
1452   mnemonics like mr.  This operand is marked FAKE.  The insertion
1453   function just copies the BT field into the BA field, and the
1454   extraction function just checks that the fields are the same.  */
1455
1456static unsigned long
1457insert_rbs (unsigned long insn,
1458	    long value ATTRIBUTE_UNUSED,
1459	    int dialect ATTRIBUTE_UNUSED,
1460	    const char **errmsg ATTRIBUTE_UNUSED)
1461{
1462  return insn | (((insn >> 21) & 0x1f) << 11);
1463}
1464
1465static long
1466extract_rbs (unsigned long insn,
1467	     int dialect ATTRIBUTE_UNUSED,
1468	     int *invalid)
1469{
1470  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1471    *invalid = 1;
1472  return 0;
1473}
1474
1475/* The SH field in an MD form instruction.  This is split.  */
1476
1477static unsigned long
1478insert_sh6 (unsigned long insn,
1479	    long value,
1480	    int dialect ATTRIBUTE_UNUSED,
1481	    const char **errmsg ATTRIBUTE_UNUSED)
1482{
1483  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1484}
1485
1486static long
1487extract_sh6 (unsigned long insn,
1488	     int dialect ATTRIBUTE_UNUSED,
1489	     int *invalid ATTRIBUTE_UNUSED)
1490{
1491  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1492}
1493
1494/* The SPR field in an XFX form instruction.  This is flipped--the
1495   lower 5 bits are stored in the upper 5 and vice- versa.  */
1496
1497static unsigned long
1498insert_spr (unsigned long insn,
1499	    long value,
1500	    int dialect ATTRIBUTE_UNUSED,
1501	    const char **errmsg ATTRIBUTE_UNUSED)
1502{
1503  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1504}
1505
1506static long
1507extract_spr (unsigned long insn,
1508	     int dialect ATTRIBUTE_UNUSED,
1509	     int *invalid ATTRIBUTE_UNUSED)
1510{
1511  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1512}
1513
1514/* Some dialects have 8 SPRG registers instead of the standard 4.  */
1515
1516static unsigned long
1517insert_sprg (unsigned long insn,
1518	     long value,
1519	     int dialect,
1520	     const char **errmsg)
1521{
1522  /* This check uses PPC_OPCODE_403 because PPC405 is later defined
1523     as a synonym.  If ever a 405 specific dialect is added this
1524     check should use that instead.  */
1525  if (value > 7
1526      || (value > 3
1527	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1528    *errmsg = _("invalid sprg number");
1529
1530  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
1531     user mode.  Anything else must use spr 272..279.  */
1532  if (value <= 3 || (insn & 0x100) != 0)
1533    value |= 0x10;
1534
1535  return insn | ((value & 0x17) << 16);
1536}
1537
1538static long
1539extract_sprg (unsigned long insn,
1540	      int dialect,
1541	      int *invalid)
1542{
1543  unsigned long val = (insn >> 16) & 0x1f;
1544
1545  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
1546     If not BOOKE or 405, then both use only 272..275.  */
1547  if (val <= 3
1548      || (val < 0x10 && (insn & 0x100) != 0)
1549      || (val - 0x10 > 3
1550	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
1551    *invalid = 1;
1552  return val & 7;
1553}
1554
1555/* The TBR field in an XFX instruction.  This is just like SPR, but it
1556   is optional.  When TBR is omitted, it must be inserted as 268 (the
1557   magic number of the TB register).  These functions treat 0
1558   (indicating an omitted optional operand) as 268.  This means that
1559   ``mftb 4,0'' is not handled correctly.  This does not matter very
1560   much, since the architecture manual does not define mftb as
1561   accepting any values other than 268 or 269.  */
1562
1563#define TB (268)
1564
1565static unsigned long
1566insert_tbr (unsigned long insn,
1567	    long value,
1568	    int dialect ATTRIBUTE_UNUSED,
1569	    const char **errmsg ATTRIBUTE_UNUSED)
1570{
1571  if (value == 0)
1572    value = TB;
1573  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1574}
1575
1576static long
1577extract_tbr (unsigned long insn,
1578	     int dialect ATTRIBUTE_UNUSED,
1579	     int *invalid ATTRIBUTE_UNUSED)
1580{
1581  long ret;
1582
1583  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1584  if (ret == TB)
1585    ret = 0;
1586  return ret;
1587}
1588
1589/* Macros used to form opcodes.  */
1590
1591/* The main opcode.  */
1592#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1593#define OP_MASK OP (0x3f)
1594
1595/* The main opcode combined with a trap code in the TO field of a D
1596   form instruction.  Used for extended mnemonics for the trap
1597   instructions.  */
1598#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1599#define OPTO_MASK (OP_MASK | TO_MASK)
1600
1601/* The main opcode combined with a comparison size bit in the L field
1602   of a D form or X form instruction.  Used for extended mnemonics for
1603   the comparison instructions.  */
1604#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1605#define OPL_MASK OPL (0x3f,1)
1606
1607/* An A form instruction.  */
1608#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1609#define A_MASK A (0x3f, 0x1f, 1)
1610
1611/* An A_MASK with the FRB field fixed.  */
1612#define AFRB_MASK (A_MASK | FRB_MASK)
1613
1614/* An A_MASK with the FRC field fixed.  */
1615#define AFRC_MASK (A_MASK | FRC_MASK)
1616
1617/* An A_MASK with the FRA and FRC fields fixed.  */
1618#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1619
1620/* An AFRAFRC_MASK, but with L bit clear.  */
1621#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))
1622
1623/* A B form instruction.  */
1624#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1625#define B_MASK B (0x3f, 1, 1)
1626
1627/* A B form instruction setting the BO field.  */
1628#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1629#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1630
1631/* A BBO_MASK with the y bit of the BO field removed.  This permits
1632   matching a conditional branch regardless of the setting of the y
1633   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
1634#define Y_MASK   (((unsigned long) 1) << 21)
1635#define AT1_MASK (((unsigned long) 3) << 21)
1636#define AT2_MASK (((unsigned long) 9) << 21)
1637#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
1638#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1639
1640/* A B form instruction setting the BO field and the condition bits of
1641   the BI field.  */
1642#define BBOCB(op, bo, cb, aa, lk) \
1643  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1644#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1645
1646/* A BBOCB_MASK with the y bit of the BO field removed.  */
1647#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1648#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1649#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1650
1651/* A BBOYCB_MASK in which the BI field is fixed.  */
1652#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1653#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1654
1655/* An Context form instruction.  */
1656#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
1657#define CTX_MASK CTX(0x3f, 0x7)
1658
1659/* An User Context form instruction.  */
1660#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1661#define UCTX_MASK UCTX(0x3f, 0x1f)
1662
1663/* The main opcode mask with the RA field clear.  */
1664#define DRA_MASK (OP_MASK | RA_MASK)
1665
1666/* A DS form instruction.  */
1667#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1668#define DS_MASK DSO (0x3f, 3)
1669
1670/* A DE form instruction.  */
1671#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1672#define DE_MASK DEO (0x3e, 0xf)
1673
1674/* An EVSEL form instruction.  */
1675#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1676#define EVSEL_MASK EVSEL(0x3f, 0xff)
1677
1678/* An M form instruction.  */
1679#define M(op, rc) (OP (op) | ((rc) & 1))
1680#define M_MASK M (0x3f, 1)
1681
1682/* An M form instruction with the ME field specified.  */
1683#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1684
1685/* An M_MASK with the MB and ME fields fixed.  */
1686#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1687
1688/* An M_MASK with the SH and ME fields fixed.  */
1689#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1690
1691/* An MD form instruction.  */
1692#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1693#define MD_MASK MD (0x3f, 0x7, 1)
1694
1695/* An MD_MASK with the MB field fixed.  */
1696#define MDMB_MASK (MD_MASK | MB6_MASK)
1697
1698/* An MD_MASK with the SH field fixed.  */
1699#define MDSH_MASK (MD_MASK | SH6_MASK)
1700
1701/* An MDS form instruction.  */
1702#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1703#define MDS_MASK MDS (0x3f, 0xf, 1)
1704
1705/* An MDS_MASK with the MB field fixed.  */
1706#define MDSMB_MASK (MDS_MASK | MB6_MASK)
1707
1708/* An SC form instruction.  */
1709#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1710#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1711
1712/* An VX form instruction.  */
1713#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1714
1715/* The mask for an VX form instruction.  */
1716#define VX_MASK	VX(0x3f, 0x7ff)
1717
1718/* An VA form instruction.  */
1719#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1720
1721/* The mask for an VA form instruction.  */
1722#define VXA_MASK VXA(0x3f, 0x3f)
1723
1724/* An VXR form instruction.  */
1725#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1726
1727/* The mask for a VXR form instruction.  */
1728#define VXR_MASK VXR(0x3f, 0x3ff, 1)
1729
1730/* An X form instruction.  */
1731#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1732
1733/* A Z form instruction.  */
1734#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
1735
1736/* An X form instruction with the RC bit specified.  */
1737#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1738
1739/* A Z form instruction with the RC bit specified.  */
1740#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))
1741
1742/* The mask for an X form instruction.  */
1743#define X_MASK XRC (0x3f, 0x3ff, 1)
1744
1745/* The mask for a Z form instruction.  */
1746#define Z_MASK ZRC (0x3f, 0x1ff, 1)
1747#define Z2_MASK ZRC (0x3f, 0xff, 1)
1748
1749/* An X_MASK with the RA field fixed.  */
1750#define XRA_MASK (X_MASK | RA_MASK)
1751
1752/* An XRA_MASK with the W field clear.  */
1753#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
1754
1755/* An X_MASK with the RB field fixed.  */
1756#define XRB_MASK (X_MASK | RB_MASK)
1757
1758/* An X_MASK with the RT field fixed.  */
1759#define XRT_MASK (X_MASK | RT_MASK)
1760
1761/* An XRT_MASK mask with the L bits clear.  */
1762#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))
1763
1764/* An X_MASK with the RA and RB fields fixed.  */
1765#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1766
1767/* An XRARB_MASK, but with the L bit clear.  */
1768#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1769
1770/* An X_MASK with the RT and RA fields fixed.  */
1771#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1772
1773/* An XRTRA_MASK, but with L bit clear.  */
1774#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1775
1776/* An X form instruction with the L bit specified.  */
1777#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1778
1779/* The mask for an X form comparison instruction.  */
1780#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1781
1782/* The mask for an X form comparison instruction with the L field
1783   fixed.  */
1784#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1785
1786/* An X form trap instruction with the TO field specified.  */
1787#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1788#define XTO_MASK (X_MASK | TO_MASK)
1789
1790/* An X form tlb instruction with the SH field specified.  */
1791#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1792#define XTLB_MASK (X_MASK | SH_MASK)
1793
1794/* An X form sync instruction.  */
1795#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1796
1797/* An X form sync instruction with everything filled in except the LS field.  */
1798#define XSYNC_MASK (0xff9fffff)
1799
1800/* An X_MASK, but with the EH bit clear.  */
1801#define XEH_MASK (X_MASK & ~((unsigned long )1))
1802
1803/* An X form AltiVec dss instruction.  */
1804#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1805#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1806
1807/* An XFL form instruction.  */
1808#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1809#define XFL_MASK XFL (0x3f, 0x3ff, 1)
1810
1811/* An X form isel instruction.  */
1812#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1813#define XISEL_MASK      XISEL(0x3f, 0x1f)
1814
1815/* An XL form instruction with the LK field set to 0.  */
1816#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1817
1818/* An XL form instruction which uses the LK field.  */
1819#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1820
1821/* The mask for an XL form instruction.  */
1822#define XL_MASK XLLK (0x3f, 0x3ff, 1)
1823
1824/* An XL form instruction which explicitly sets the BO field.  */
1825#define XLO(op, bo, xop, lk) \
1826  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1827#define XLO_MASK (XL_MASK | BO_MASK)
1828
1829/* An XL form instruction which explicitly sets the y bit of the BO
1830   field.  */
1831#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1832#define XLYLK_MASK (XL_MASK | Y_MASK)
1833
1834/* An XL form instruction which sets the BO field and the condition
1835   bits of the BI field.  */
1836#define XLOCB(op, bo, cb, xop, lk) \
1837  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1838#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1839
1840/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
1841#define XLBB_MASK (XL_MASK | BB_MASK)
1842#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1843#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1844
1845/* A mask for branch instructions using the BH field.  */
1846#define XLBH_MASK (XL_MASK | (0x1c << 11))
1847
1848/* An XL_MASK with the BO and BB fields fixed.  */
1849#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1850
1851/* An XL_MASK with the BO, BI and BB fields fixed.  */
1852#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1853
1854/* An XO form instruction.  */
1855#define XO(op, xop, oe, rc) \
1856  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1857#define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1858
1859/* An XO_MASK with the RB field fixed.  */
1860#define XORB_MASK (XO_MASK | RB_MASK)
1861
1862/* An XS form instruction.  */
1863#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1864#define XS_MASK XS (0x3f, 0x1ff, 1)
1865
1866/* A mask for the FXM version of an XFX form instruction.  */
1867#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))
1868
1869/* An XFX form instruction with the FXM field filled in.  */
1870#define XFXM(op, xop, fxm, p4) \
1871  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
1872   | ((unsigned long)(p4) << 20))
1873
1874/* An XFX form instruction with the SPR field filled in.  */
1875#define XSPR(op, xop, spr) \
1876  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1877#define XSPR_MASK (X_MASK | SPR_MASK)
1878
1879/* An XFX form instruction with the SPR field filled in except for the
1880   SPRBAT field.  */
1881#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1882
1883/* An XFX form instruction with the SPR field filled in except for the
1884   SPRG field.  */
1885#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))
1886
1887/* An X form instruction with everything filled in except the E field.  */
1888#define XE_MASK (0xffff7fff)
1889
1890/* An X form user context instruction.  */
1891#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
1892#define XUC_MASK      XUC(0x3f, 0x1f)
1893
1894/* The BO encodings used in extended conditional branch mnemonics.  */
1895#define BODNZF	(0x0)
1896#define BODNZFP	(0x1)
1897#define BODZF	(0x2)
1898#define BODZFP	(0x3)
1899#define BODNZT	(0x8)
1900#define BODNZTP	(0x9)
1901#define BODZT	(0xa)
1902#define BODZTP	(0xb)
1903
1904#define BOF	(0x4)
1905#define BOFP	(0x5)
1906#define BOFM4	(0x6)
1907#define BOFP4	(0x7)
1908#define BOT	(0xc)
1909#define BOTP	(0xd)
1910#define BOTM4	(0xe)
1911#define BOTP4	(0xf)
1912
1913#define BODNZ	(0x10)
1914#define BODNZP	(0x11)
1915#define BODZ	(0x12)
1916#define BODZP	(0x13)
1917#define BODNZM4 (0x18)
1918#define BODNZP4 (0x19)
1919#define BODZM4	(0x1a)
1920#define BODZP4	(0x1b)
1921
1922#define BOU	(0x14)
1923
1924/* The BI condition bit encodings used in extended conditional branch
1925   mnemonics.  */
1926#define CBLT	(0)
1927#define CBGT	(1)
1928#define CBEQ	(2)
1929#define CBSO	(3)
1930
1931/* The TO encodings used in extended trap mnemonics.  */
1932#define TOLGT	(0x1)
1933#define TOLLT	(0x2)
1934#define TOEQ	(0x4)
1935#define TOLGE	(0x5)
1936#define TOLNL	(0x5)
1937#define TOLLE	(0x6)
1938#define TOLNG	(0x6)
1939#define TOGT	(0x8)
1940#define TOGE	(0xc)
1941#define TONL	(0xc)
1942#define TOLT	(0x10)
1943#define TOLE	(0x14)
1944#define TONG	(0x14)
1945#define TONE	(0x18)
1946#define TOU	(0x1f)
1947
1948/* Smaller names for the flags so each entry in the opcodes table will
1949   fit on a single line.  */
1950#undef	PPC
1951#define PPC     PPC_OPCODE_PPC
1952#define PPCCOM	PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1953#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1954#define POWER4	PPC_OPCODE_POWER4
1955#define POWER5	PPC_OPCODE_POWER5
1956#define POWER6	PPC_OPCODE_POWER6
1957#define CELL	PPC_OPCODE_CELL
1958#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
1959#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
1960#define PPC403	PPC_OPCODE_403
1961#define PPC405	PPC403
1962#define PPC440	PPC_OPCODE_440
1963#define PPC750	PPC
1964#define PPC860	PPC
1965#define PPCVEC	PPC_OPCODE_ALTIVEC
1966#define	POWER   PPC_OPCODE_POWER
1967#define	POWER2	PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1968#define PPCPWR2	PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1969#define	POWER32	PPC_OPCODE_POWER | PPC_OPCODE_32
1970#define	COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1971#define	COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1972#define	M601    PPC_OPCODE_POWER | PPC_OPCODE_601
1973#define PWRCOM	PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1974#define	MFDEC1	PPC_OPCODE_POWER
1975#define	MFDEC2	PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1976#define BOOKE	PPC_OPCODE_BOOKE
1977#define BOOKE64	PPC_OPCODE_BOOKE64
1978#define CLASSIC	PPC_OPCODE_CLASSIC
1979#define PPCE300 PPC_OPCODE_E300
1980#define PPCSPE	PPC_OPCODE_SPE
1981#define PPCISEL	PPC_OPCODE_ISEL
1982#define PPCEFS	PPC_OPCODE_EFS
1983#define PPCBRLK	PPC_OPCODE_BRLOCK
1984#define PPCPMR	PPC_OPCODE_PMR
1985#define PPCCHLK	PPC_OPCODE_CACHELCK
1986#define PPCCHLK64	PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1987#define PPCRFMCI	PPC_OPCODE_RFMCI
1988
1989/* The opcode table.
1990
1991   The format of the opcode table is:
1992
1993   NAME	     OPCODE	MASK		FLAGS		{ OPERANDS }
1994
1995   NAME is the name of the instruction.
1996   OPCODE is the instruction opcode.
1997   MASK is the opcode mask; this is used to tell the disassembler
1998     which bits in the actual opcode must match OPCODE.
1999   FLAGS are flags indicated what processors support the instruction.
2000   OPERANDS is the list of operands.
2001
2002   The disassembler reads the table in order and prints the first
2003   instruction which matches, so this table is sorted to put more
2004   specific instructions before more general instructions.  It is also
2005   sorted by major opcode.  */
2006
2007const struct powerpc_opcode powerpc_opcodes[] = {
2008{ "attn",    X(0,256), X_MASK,		POWER4,		{ 0 } },
2009{ "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,	PPC64,		{ RA, SI } },
2010{ "tdllti",  OPTO(2,TOLLT), OPTO_MASK,	PPC64,		{ RA, SI } },
2011{ "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,	PPC64,		{ RA, SI } },
2012{ "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,	PPC64,		{ RA, SI } },
2013{ "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,	PPC64,		{ RA, SI } },
2014{ "tdllei",  OPTO(2,TOLLE), OPTO_MASK,	PPC64,		{ RA, SI } },
2015{ "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,	PPC64,		{ RA, SI } },
2016{ "tdgti",   OPTO(2,TOGT), OPTO_MASK,	PPC64,		{ RA, SI } },
2017{ "tdgei",   OPTO(2,TOGE), OPTO_MASK,	PPC64,		{ RA, SI } },
2018{ "tdnli",   OPTO(2,TONL), OPTO_MASK,	PPC64,		{ RA, SI } },
2019{ "tdlti",   OPTO(2,TOLT), OPTO_MASK,	PPC64,		{ RA, SI } },
2020{ "tdlei",   OPTO(2,TOLE), OPTO_MASK,	PPC64,		{ RA, SI } },
2021{ "tdngi",   OPTO(2,TONG), OPTO_MASK,	PPC64,		{ RA, SI } },
2022{ "tdnei",   OPTO(2,TONE), OPTO_MASK,	PPC64,		{ RA, SI } },
2023{ "tdi",     OP(2),	OP_MASK,	PPC64,		{ TO, RA, SI } },
2024
2025{ "twlgti",  OPTO(3,TOLGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2026{ "tlgti",   OPTO(3,TOLGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2027{ "twllti",  OPTO(3,TOLLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2028{ "tllti",   OPTO(3,TOLLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2029{ "tweqi",   OPTO(3,TOEQ), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2030{ "teqi",    OPTO(3,TOEQ), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2031{ "twlgei",  OPTO(3,TOLGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2032{ "tlgei",   OPTO(3,TOLGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2033{ "twlnli",  OPTO(3,TOLNL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2034{ "tlnli",   OPTO(3,TOLNL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2035{ "twllei",  OPTO(3,TOLLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2036{ "tllei",   OPTO(3,TOLLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2037{ "twlngi",  OPTO(3,TOLNG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2038{ "tlngi",   OPTO(3,TOLNG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2039{ "twgti",   OPTO(3,TOGT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2040{ "tgti",    OPTO(3,TOGT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2041{ "twgei",   OPTO(3,TOGE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2042{ "tgei",    OPTO(3,TOGE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2043{ "twnli",   OPTO(3,TONL), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2044{ "tnli",    OPTO(3,TONL), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2045{ "twlti",   OPTO(3,TOLT), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2046{ "tlti",    OPTO(3,TOLT), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2047{ "twlei",   OPTO(3,TOLE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2048{ "tlei",    OPTO(3,TOLE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2049{ "twngi",   OPTO(3,TONG), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2050{ "tngi",    OPTO(3,TONG), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2051{ "twnei",   OPTO(3,TONE), OPTO_MASK,	PPCCOM,		{ RA, SI } },
2052{ "tnei",    OPTO(3,TONE), OPTO_MASK,	PWRCOM,		{ RA, SI } },
2053{ "twi",     OP(3),	OP_MASK,	PPCCOM,		{ TO, RA, SI } },
2054{ "ti",      OP(3),	OP_MASK,	PWRCOM,		{ TO, RA, SI } },
2055
2056{ "macchw",	XO(4,172,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2057{ "macchw.",	XO(4,172,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2058{ "macchwo",	XO(4,172,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2059{ "macchwo.",	XO(4,172,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2060{ "macchws",	XO(4,236,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2061{ "macchws.",	XO(4,236,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2062{ "macchwso",	XO(4,236,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2063{ "macchwso.",	XO(4,236,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2064{ "macchwsu",	XO(4,204,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2065{ "macchwsu.",	XO(4,204,0,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2066{ "macchwsuo",	XO(4,204,1,0), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2067{ "macchwsuo.",	XO(4,204,1,1), XO_MASK, PPC405|PPC440,	{ RT, RA, RB } },
2068{ "macchwu",	XO(4,140,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2069{ "macchwu.",	XO(4,140,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2070{ "macchwuo",	XO(4,140,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2071{ "macchwuo.",	XO(4,140,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2072{ "machhw",	XO(4,44,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2073{ "machhw.",	XO(4,44,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2074{ "machhwo",	XO(4,44,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2075{ "machhwo.",	XO(4,44,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2076{ "machhws",	XO(4,108,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2077{ "machhws.",	XO(4,108,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2078{ "machhwso",	XO(4,108,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2079{ "machhwso.",	XO(4,108,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2080{ "machhwsu",	XO(4,76,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2081{ "machhwsu.",	XO(4,76,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2082{ "machhwsuo",	XO(4,76,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2083{ "machhwsuo.",	XO(4,76,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2084{ "machhwu",	XO(4,12,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2085{ "machhwu.",	XO(4,12,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2086{ "machhwuo",	XO(4,12,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2087{ "machhwuo.",	XO(4,12,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2088{ "maclhw",	XO(4,428,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2089{ "maclhw.",	XO(4,428,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2090{ "maclhwo",	XO(4,428,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2091{ "maclhwo.",	XO(4,428,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2092{ "maclhws",	XO(4,492,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2093{ "maclhws.",	XO(4,492,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2094{ "maclhwso",	XO(4,492,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2095{ "maclhwso.",	XO(4,492,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2096{ "maclhwsu",	XO(4,460,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2097{ "maclhwsu.",	XO(4,460,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2098{ "maclhwsuo",	XO(4,460,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2099{ "maclhwsuo.",	XO(4,460,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2100{ "maclhwu",	XO(4,396,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2101{ "maclhwu.",	XO(4,396,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2102{ "maclhwuo",	XO(4,396,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2103{ "maclhwuo.",	XO(4,396,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2104{ "mulchw",	XRC(4,168,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2105{ "mulchw.",	XRC(4,168,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2106{ "mulchwu",	XRC(4,136,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2107{ "mulchwu.",	XRC(4,136,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2108{ "mulhhw",	XRC(4,40,0),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2109{ "mulhhw.",	XRC(4,40,1),   X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2110{ "mulhhwu",	XRC(4,8,0),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2111{ "mulhhwu.",	XRC(4,8,1),    X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2112{ "mullhw",	XRC(4,424,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2113{ "mullhw.",	XRC(4,424,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2114{ "mullhwu",	XRC(4,392,0),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2115{ "mullhwu.",	XRC(4,392,1),  X_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2116{ "nmacchw",	XO(4,174,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2117{ "nmacchw.",	XO(4,174,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2118{ "nmacchwo",	XO(4,174,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2119{ "nmacchwo.",	XO(4,174,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2120{ "nmacchws",	XO(4,238,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2121{ "nmacchws.",	XO(4,238,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2122{ "nmacchwso",	XO(4,238,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2123{ "nmacchwso.",	XO(4,238,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2124{ "nmachhw",	XO(4,46,0,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2125{ "nmachhw.",	XO(4,46,0,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2126{ "nmachhwo",	XO(4,46,1,0),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2127{ "nmachhwo.",	XO(4,46,1,1),  XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2128{ "nmachhws",	XO(4,110,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2129{ "nmachhws.",	XO(4,110,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2130{ "nmachhwso",	XO(4,110,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2131{ "nmachhwso.",	XO(4,110,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2132{ "nmaclhw",	XO(4,430,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2133{ "nmaclhw.",	XO(4,430,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2134{ "nmaclhwo",	XO(4,430,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2135{ "nmaclhwo.",	XO(4,430,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2136{ "nmaclhws",	XO(4,494,0,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2137{ "nmaclhws.",	XO(4,494,0,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2138{ "nmaclhwso",	XO(4,494,1,0), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2139{ "nmaclhwso.",	XO(4,494,1,1), XO_MASK,	PPC405|PPC440,	{ RT, RA, RB } },
2140{ "mfvscr",  VX(4, 1540), VX_MASK,	PPCVEC,		{ VD } },
2141{ "mtvscr",  VX(4, 1604), VX_MASK,	PPCVEC,		{ VB } },
2142
2143  /* Double-precision opcodes.  */
2144  /* Some of these conflict with AltiVec, so move them before, since
2145     PPCVEC includes the PPC_OPCODE_PPC set.  */
2146{ "efscfd",   VX(4, 719), VX_MASK,	PPCEFS,		{ RS, RB } },
2147{ "efdabs",   VX(4, 740), VX_MASK,	PPCEFS,		{ RS, RA } },
2148{ "efdnabs",  VX(4, 741), VX_MASK,	PPCEFS,		{ RS, RA } },
2149{ "efdneg",   VX(4, 742), VX_MASK,	PPCEFS,		{ RS, RA } },
2150{ "efdadd",   VX(4, 736), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2151{ "efdsub",   VX(4, 737), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2152{ "efdmul",   VX(4, 744), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2153{ "efddiv",   VX(4, 745), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2154{ "efdcmpgt", VX(4, 748), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2155{ "efdcmplt", VX(4, 749), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2156{ "efdcmpeq", VX(4, 750), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2157{ "efdtstgt", VX(4, 764), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2158{ "efdtstlt", VX(4, 765), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2159{ "efdtsteq", VX(4, 766), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2160{ "efdcfsi",  VX(4, 753), VX_MASK,	PPCEFS,		{ RS, RB } },
2161{ "efdcfsid", VX(4, 739), VX_MASK,	PPCEFS,		{ RS, RB } },
2162{ "efdcfui",  VX(4, 752), VX_MASK,	PPCEFS,		{ RS, RB } },
2163{ "efdcfuid", VX(4, 738), VX_MASK,	PPCEFS,		{ RS, RB } },
2164{ "efdcfsf",  VX(4, 755), VX_MASK,	PPCEFS,		{ RS, RB } },
2165{ "efdcfuf",  VX(4, 754), VX_MASK,	PPCEFS,		{ RS, RB } },
2166{ "efdctsi",  VX(4, 757), VX_MASK,	PPCEFS,		{ RS, RB } },
2167{ "efdctsidz",VX(4, 747), VX_MASK,	PPCEFS,		{ RS, RB } },
2168{ "efdctsiz", VX(4, 762), VX_MASK,	PPCEFS,		{ RS, RB } },
2169{ "efdctui",  VX(4, 756), VX_MASK,	PPCEFS,		{ RS, RB } },
2170{ "efdctuidz",VX(4, 746), VX_MASK,	PPCEFS,		{ RS, RB } },
2171{ "efdctuiz", VX(4, 760), VX_MASK,	PPCEFS,		{ RS, RB } },
2172{ "efdctsf",  VX(4, 759), VX_MASK,	PPCEFS,		{ RS, RB } },
2173{ "efdctuf",  VX(4, 758), VX_MASK,	PPCEFS,		{ RS, RB } },
2174{ "efdcfs",   VX(4, 751), VX_MASK,	PPCEFS,		{ RS, RB } },
2175  /* End of double-precision opcodes.  */
2176
2177{ "vaddcuw", VX(4,  384), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2178{ "vaddfp",  VX(4,   10), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2179{ "vaddsbs", VX(4,  768), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2180{ "vaddshs", VX(4,  832), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2181{ "vaddsws", VX(4,  896), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2182{ "vaddubm", VX(4,    0), VX_MASK, 	PPCVEC,		{ VD, VA, VB } },
2183{ "vaddubs", VX(4,  512), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2184{ "vadduhm", VX(4,   64), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2185{ "vadduhs", VX(4,  576), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2186{ "vadduwm", VX(4,  128), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2187{ "vadduws", VX(4,  640), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2188{ "vand",    VX(4, 1028), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2189{ "vandc",   VX(4, 1092), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2190{ "vavgsb",  VX(4, 1282), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2191{ "vavgsh",  VX(4, 1346), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2192{ "vavgsw",  VX(4, 1410), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2193{ "vavgub",  VX(4, 1026), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2194{ "vavguh",  VX(4, 1090), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2195{ "vavguw",  VX(4, 1154), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2196{ "vcfsx",   VX(4,  842), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2197{ "vcfux",   VX(4,  778), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2198{ "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2199{ "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2200{ "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2201{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2202{ "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2203{ "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2204{ "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2205{ "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2206{ "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2207{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2208{ "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2209{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2210{ "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2211{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2212{ "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2213{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2214{ "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2215{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2216{ "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2217{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2218{ "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2219{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2220{ "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2221{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2222{ "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2223{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,	{ VD, VA, VB } },
2224{ "vctsxs",    VX(4,  970), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2225{ "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2226{ "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
2227{ "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
2228{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2229{ "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2230{ "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2231{ "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2232{ "vmaxsw",    VX(4,  386), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2233{ "vmaxub",    VX(4,    2), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2234{ "vmaxuh",    VX(4,   66), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2235{ "vmaxuw",    VX(4,  130), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2236{ "vmhaddshs", VXA(4,  32), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2237{ "vmhraddshs", VXA(4, 33), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2238{ "vminfp",    VX(4, 1098), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2239{ "vminsb",    VX(4,  770), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2240{ "vminsh",    VX(4,  834), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2241{ "vminsw",    VX(4,  898), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2242{ "vminub",    VX(4,  514), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2243{ "vminuh",    VX(4,  578), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2244{ "vminuw",    VX(4,  642), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2245{ "vmladduhm", VXA(4,  34), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2246{ "vmrghb",    VX(4,   12), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2247{ "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,		{ VD, VA, VB } },
2248{ "vmrghw",    VX(4,  140), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2249{ "vmrglb",    VX(4,  268), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2250{ "vmrglh",    VX(4,  332), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2251{ "vmrglw",    VX(4,  396), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2252{ "vmsummbm",  VXA(4,  37), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2253{ "vmsumshm",  VXA(4,  40), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2254{ "vmsumshs",  VXA(4,  41), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2255{ "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2256{ "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2257{ "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,		{ VD, VA, VB, VC } },
2258{ "vmulesb",   VX(4,  776), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2259{ "vmulesh",   VX(4,  840), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2260{ "vmuleub",   VX(4,  520), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2261{ "vmuleuh",   VX(4,  584), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2262{ "vmulosb",   VX(4,  264), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2263{ "vmulosh",   VX(4,  328), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2264{ "vmuloub",   VX(4,    8), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2265{ "vmulouh",   VX(4,   72), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2266{ "vnmsubfp",  VXA(4,  47), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
2267{ "vnor",      VX(4, 1284), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2268{ "vor",       VX(4, 1156), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2269{ "vperm",     VXA(4,  43), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2270{ "vpkpx",     VX(4,  782), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2271{ "vpkshss",   VX(4,  398), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2272{ "vpkshus",   VX(4,  270), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2273{ "vpkswss",   VX(4,  462), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2274{ "vpkswus",   VX(4,  334), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2275{ "vpkuhum",   VX(4,   14), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2276{ "vpkuhus",   VX(4,  142), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2277{ "vpkuwum",   VX(4,   78), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2278{ "vpkuwus",   VX(4,  206), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2279{ "vrefp",     VX(4,  266), VX_MASK,	PPCVEC,		{ VD, VB } },
2280{ "vrfim",     VX(4,  714), VX_MASK,	PPCVEC,		{ VD, VB } },
2281{ "vrfin",     VX(4,  522), VX_MASK,	PPCVEC,		{ VD, VB } },
2282{ "vrfip",     VX(4,  650), VX_MASK,	PPCVEC,		{ VD, VB } },
2283{ "vrfiz",     VX(4,  586), VX_MASK,	PPCVEC,		{ VD, VB } },
2284{ "vrlb",      VX(4,    4), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2285{ "vrlh",      VX(4,   68), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2286{ "vrlw",      VX(4,  132), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2287{ "vrsqrtefp", VX(4,  330), VX_MASK,	PPCVEC,		{ VD, VB } },
2288{ "vsel",      VXA(4,  42), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
2289{ "vsl",       VX(4,  452), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2290{ "vslb",      VX(4,  260), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2291{ "vsldoi",    VXA(4,  44), VXA_MASK,	PPCVEC,		{ VD, VA, VB, SHB } },
2292{ "vslh",      VX(4,  324), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2293{ "vslo",      VX(4, 1036), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2294{ "vslw",      VX(4,  388), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2295{ "vspltb",    VX(4,  524), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2296{ "vsplth",    VX(4,  588), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2297{ "vspltisb",  VX(4,  780), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2298{ "vspltish",  VX(4,  844), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2299{ "vspltisw",  VX(4,  908), VX_MASK,	PPCVEC,		{ VD, SIMM } },
2300{ "vspltw",    VX(4,  652), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
2301{ "vsr",       VX(4,  708), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2302{ "vsrab",     VX(4,  772), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2303{ "vsrah",     VX(4,  836), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2304{ "vsraw",     VX(4,  900), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2305{ "vsrb",      VX(4,  516), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2306{ "vsrh",      VX(4,  580), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2307{ "vsro",      VX(4, 1100), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2308{ "vsrw",      VX(4,  644), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2309{ "vsubcuw",   VX(4, 1408), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2310{ "vsubfp",    VX(4,   74), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2311{ "vsubsbs",   VX(4, 1792), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2312{ "vsubshs",   VX(4, 1856), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2313{ "vsubsws",   VX(4, 1920), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2314{ "vsububm",   VX(4, 1024), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2315{ "vsububs",   VX(4, 1536), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2316{ "vsubuhm",   VX(4, 1088), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2317{ "vsubuhs",   VX(4, 1600), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2318{ "vsubuwm",   VX(4, 1152), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2319{ "vsubuws",   VX(4, 1664), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2320{ "vsumsws",   VX(4, 1928), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2321{ "vsum2sws",  VX(4, 1672), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2322{ "vsum4sbs",  VX(4, 1800), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2323{ "vsum4shs",  VX(4, 1608), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2324{ "vsum4ubs",  VX(4, 1544), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2325{ "vupkhpx",   VX(4,  846), VX_MASK,	PPCVEC,		{ VD, VB } },
2326{ "vupkhsb",   VX(4,  526), VX_MASK,	PPCVEC,		{ VD, VB } },
2327{ "vupkhsh",   VX(4,  590), VX_MASK,	PPCVEC,		{ VD, VB } },
2328{ "vupklpx",   VX(4,  974), VX_MASK,	PPCVEC,		{ VD, VB } },
2329{ "vupklsb",   VX(4,  654), VX_MASK,	PPCVEC,		{ VD, VB } },
2330{ "vupklsh",   VX(4,  718), VX_MASK,	PPCVEC,		{ VD, VB } },
2331{ "vxor",      VX(4, 1220), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
2332
2333{ "evaddw",    VX(4, 512), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2334{ "evaddiw",   VX(4, 514), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2335{ "evsubfw",   VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2336{ "evsubw",    VX(4, 516), VX_MASK,	PPCSPE,		{ RS, RB, RA } },
2337{ "evsubifw",  VX(4, 518), VX_MASK,	PPCSPE,		{ RS, UIMM, RB } },
2338{ "evsubiw",   VX(4, 518), VX_MASK,	PPCSPE,		{ RS, RB, UIMM } },
2339{ "evabs",     VX(4, 520), VX_MASK,	PPCSPE,		{ RS, RA } },
2340{ "evneg",     VX(4, 521), VX_MASK,	PPCSPE,		{ RS, RA } },
2341{ "evextsb",   VX(4, 522), VX_MASK,	PPCSPE,		{ RS, RA } },
2342{ "evextsh",   VX(4, 523), VX_MASK,	PPCSPE,		{ RS, RA } },
2343{ "evrndw",    VX(4, 524), VX_MASK,	PPCSPE,		{ RS, RA } },
2344{ "evcntlzw",  VX(4, 525), VX_MASK,	PPCSPE,		{ RS, RA } },
2345{ "evcntlsw",  VX(4, 526), VX_MASK,	PPCSPE,		{ RS, RA } },
2346
2347{ "brinc",     VX(4, 527), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2348
2349{ "evand",     VX(4, 529), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2350{ "evandc",    VX(4, 530), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2351{ "evmr",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2352{ "evor",      VX(4, 535), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2353{ "evorc",     VX(4, 539), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2354{ "evxor",     VX(4, 534), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2355{ "eveqv",     VX(4, 537), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2356{ "evnand",    VX(4, 542), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2357{ "evnot",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, BBA } },
2358{ "evnor",     VX(4, 536), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2359
2360{ "evrlw",     VX(4, 552), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2361{ "evrlwi",    VX(4, 554), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2362{ "evslw",     VX(4, 548), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2363{ "evslwi",    VX(4, 550), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2364{ "evsrws",    VX(4, 545), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2365{ "evsrwu",    VX(4, 544), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2366{ "evsrwis",   VX(4, 547), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2367{ "evsrwiu",   VX(4, 546), VX_MASK,	PPCSPE,		{ RS, RA, EVUIMM } },
2368{ "evsplati",  VX(4, 553), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2369{ "evsplatfi", VX(4, 555), VX_MASK,	PPCSPE,		{ RS, SIMM } },
2370{ "evmergehi", VX(4, 556), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2371{ "evmergelo", VX(4, 557), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2372{ "evmergehilo",VX(4,558), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2373{ "evmergelohi",VX(4,559), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2374
2375{ "evcmpgts",  VX(4, 561), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2376{ "evcmpgtu",  VX(4, 560), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2377{ "evcmplts",  VX(4, 563), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2378{ "evcmpltu",  VX(4, 562), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2379{ "evcmpeq",   VX(4, 564), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2380{ "evsel",     EVSEL(4,79),EVSEL_MASK,	PPCSPE,		{ RS, RA, RB, CRFS } },
2381
2382{ "evldd",     VX(4, 769), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2383{ "evlddx",    VX(4, 768), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2384{ "evldw",     VX(4, 771), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2385{ "evldwx",    VX(4, 770), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2386{ "evldh",     VX(4, 773), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2387{ "evldhx",    VX(4, 772), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2388{ "evlwhe",    VX(4, 785), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2389{ "evlwhex",   VX(4, 784), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2390{ "evlwhou",   VX(4, 789), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2391{ "evlwhoux",  VX(4, 788), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2392{ "evlwhos",   VX(4, 791), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2393{ "evlwhosx",  VX(4, 790), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2394{ "evlwwsplat",VX(4, 793), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2395{ "evlwwsplatx",VX(4, 792), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2396{ "evlwhsplat",VX(4, 797), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2397{ "evlwhsplatx",VX(4, 796), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2398{ "evlhhesplat",VX(4, 777), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2399{ "evlhhesplatx",VX(4, 776), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2400{ "evlhhousplat",VX(4, 781), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2401{ "evlhhousplatx",VX(4, 780), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2402{ "evlhhossplat",VX(4, 783), VX_MASK,	PPCSPE,		{ RS, EVUIMM_2, RA } },
2403{ "evlhhossplatx",VX(4, 782), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2404
2405{ "evstdd",    VX(4, 801), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2406{ "evstddx",   VX(4, 800), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2407{ "evstdw",    VX(4, 803), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2408{ "evstdwx",   VX(4, 802), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2409{ "evstdh",    VX(4, 805), VX_MASK,	PPCSPE,		{ RS, EVUIMM_8, RA } },
2410{ "evstdhx",   VX(4, 804), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2411{ "evstwwe",   VX(4, 825), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2412{ "evstwwex",  VX(4, 824), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2413{ "evstwwo",   VX(4, 829), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2414{ "evstwwox",  VX(4, 828), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2415{ "evstwhe",   VX(4, 817), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2416{ "evstwhex",  VX(4, 816), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2417{ "evstwho",   VX(4, 821), VX_MASK,	PPCSPE,		{ RS, EVUIMM_4, RA } },
2418{ "evstwhox",  VX(4, 820), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2419
2420{ "evfsabs",   VX(4, 644), VX_MASK,	PPCSPE,		{ RS, RA } },
2421{ "evfsnabs",  VX(4, 645), VX_MASK,	PPCSPE,		{ RS, RA } },
2422{ "evfsneg",   VX(4, 646), VX_MASK,	PPCSPE,		{ RS, RA } },
2423{ "evfsadd",   VX(4, 640), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2424{ "evfssub",   VX(4, 641), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2425{ "evfsmul",   VX(4, 648), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2426{ "evfsdiv",   VX(4, 649), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2427{ "evfscmpgt", VX(4, 652), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2428{ "evfscmplt", VX(4, 653), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2429{ "evfscmpeq", VX(4, 654), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2430{ "evfststgt", VX(4, 668), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2431{ "evfststlt", VX(4, 669), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2432{ "evfststeq", VX(4, 670), VX_MASK,	PPCSPE,		{ CRFD, RA, RB } },
2433{ "evfscfui",  VX(4, 656), VX_MASK,	PPCSPE,		{ RS, RB } },
2434{ "evfsctuiz", VX(4, 664), VX_MASK,	PPCSPE,		{ RS, RB } },
2435{ "evfscfsi",  VX(4, 657), VX_MASK,	PPCSPE,		{ RS, RB } },
2436{ "evfscfuf",  VX(4, 658), VX_MASK,	PPCSPE,		{ RS, RB } },
2437{ "evfscfsf",  VX(4, 659), VX_MASK,	PPCSPE,		{ RS, RB } },
2438{ "evfsctui",  VX(4, 660), VX_MASK,	PPCSPE,		{ RS, RB } },
2439{ "evfsctsi",  VX(4, 661), VX_MASK,	PPCSPE,		{ RS, RB } },
2440{ "evfsctsiz", VX(4, 666), VX_MASK,	PPCSPE,		{ RS, RB } },
2441{ "evfsctuf",  VX(4, 662), VX_MASK,	PPCSPE,		{ RS, RB } },
2442{ "evfsctsf",  VX(4, 663), VX_MASK,	PPCSPE,		{ RS, RB } },
2443
2444{ "efsabs",   VX(4, 708), VX_MASK,	PPCEFS,		{ RS, RA } },
2445{ "efsnabs",  VX(4, 709), VX_MASK,	PPCEFS,		{ RS, RA } },
2446{ "efsneg",   VX(4, 710), VX_MASK,	PPCEFS,		{ RS, RA } },
2447{ "efsadd",   VX(4, 704), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2448{ "efssub",   VX(4, 705), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2449{ "efsmul",   VX(4, 712), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2450{ "efsdiv",   VX(4, 713), VX_MASK,	PPCEFS,		{ RS, RA, RB } },
2451{ "efscmpgt", VX(4, 716), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2452{ "efscmplt", VX(4, 717), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2453{ "efscmpeq", VX(4, 718), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2454{ "efststgt", VX(4, 732), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2455{ "efststlt", VX(4, 733), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2456{ "efststeq", VX(4, 734), VX_MASK,	PPCEFS,		{ CRFD, RA, RB } },
2457{ "efscfui",  VX(4, 720), VX_MASK,	PPCEFS,		{ RS, RB } },
2458{ "efsctuiz", VX(4, 728), VX_MASK,	PPCEFS,		{ RS, RB } },
2459{ "efscfsi",  VX(4, 721), VX_MASK,	PPCEFS,		{ RS, RB } },
2460{ "efscfuf",  VX(4, 722), VX_MASK,	PPCEFS,		{ RS, RB } },
2461{ "efscfsf",  VX(4, 723), VX_MASK,	PPCEFS,		{ RS, RB } },
2462{ "efsctui",  VX(4, 724), VX_MASK,	PPCEFS,		{ RS, RB } },
2463{ "efsctsi",  VX(4, 725), VX_MASK,	PPCEFS,		{ RS, RB } },
2464{ "efsctsiz", VX(4, 730), VX_MASK,	PPCEFS,		{ RS, RB } },
2465{ "efsctuf",  VX(4, 726), VX_MASK,	PPCEFS,		{ RS, RB } },
2466{ "efsctsf",  VX(4, 727), VX_MASK,	PPCEFS,		{ RS, RB } },
2467
2468{ "evmhossf",  VX(4, 1031), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2469{ "evmhossfa", VX(4, 1063), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2470{ "evmhosmf",  VX(4, 1039), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2471{ "evmhosmfa", VX(4, 1071), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2472{ "evmhosmi",  VX(4, 1037), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2473{ "evmhosmia", VX(4, 1069), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2474{ "evmhoumi",  VX(4, 1036), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2475{ "evmhoumia", VX(4, 1068), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2476{ "evmhessf",  VX(4, 1027), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2477{ "evmhessfa", VX(4, 1059), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2478{ "evmhesmf",  VX(4, 1035), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2479{ "evmhesmfa", VX(4, 1067), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2480{ "evmhesmi",  VX(4, 1033), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2481{ "evmhesmia", VX(4, 1065), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2482{ "evmheumi",  VX(4, 1032), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2483{ "evmheumia", VX(4, 1064), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2484
2485{ "evmhossfaaw",VX(4, 1287), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2486{ "evmhossiaaw",VX(4, 1285), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2487{ "evmhosmfaaw",VX(4, 1295), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2488{ "evmhosmiaaw",VX(4, 1293), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2489{ "evmhousiaaw",VX(4, 1284), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2490{ "evmhoumiaaw",VX(4, 1292), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2491{ "evmhessfaaw",VX(4, 1283), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2492{ "evmhessiaaw",VX(4, 1281), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2493{ "evmhesmfaaw",VX(4, 1291), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2494{ "evmhesmiaaw",VX(4, 1289), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2495{ "evmheusiaaw",VX(4, 1280), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2496{ "evmheumiaaw",VX(4, 1288), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2497
2498{ "evmhossfanw",VX(4, 1415), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2499{ "evmhossianw",VX(4, 1413), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2500{ "evmhosmfanw",VX(4, 1423), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2501{ "evmhosmianw",VX(4, 1421), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2502{ "evmhousianw",VX(4, 1412), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2503{ "evmhoumianw",VX(4, 1420), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2504{ "evmhessfanw",VX(4, 1411), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2505{ "evmhessianw",VX(4, 1409), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2506{ "evmhesmfanw",VX(4, 1419), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2507{ "evmhesmianw",VX(4, 1417), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2508{ "evmheusianw",VX(4, 1408), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2509{ "evmheumianw",VX(4, 1416), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2510
2511{ "evmhogsmfaa",VX(4, 1327), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2512{ "evmhogsmiaa",VX(4, 1325), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2513{ "evmhogumiaa",VX(4, 1324), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2514{ "evmhegsmfaa",VX(4, 1323), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2515{ "evmhegsmiaa",VX(4, 1321), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2516{ "evmhegumiaa",VX(4, 1320), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2517
2518{ "evmhogsmfan",VX(4, 1455), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2519{ "evmhogsmian",VX(4, 1453), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2520{ "evmhogumian",VX(4, 1452), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2521{ "evmhegsmfan",VX(4, 1451), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2522{ "evmhegsmian",VX(4, 1449), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2523{ "evmhegumian",VX(4, 1448), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2524
2525{ "evmwhssf",  VX(4, 1095), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2526{ "evmwhssfa", VX(4, 1127), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2527{ "evmwhsmf",  VX(4, 1103), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2528{ "evmwhsmfa", VX(4, 1135), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2529{ "evmwhsmi",  VX(4, 1101), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2530{ "evmwhsmia", VX(4, 1133), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2531{ "evmwhumi",  VX(4, 1100), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2532{ "evmwhumia", VX(4, 1132), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2533
2534{ "evmwlumi",  VX(4, 1096), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2535{ "evmwlumia", VX(4, 1128), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2536
2537{ "evmwlssiaaw",VX(4, 1345), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2538{ "evmwlsmiaaw",VX(4, 1353), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2539{ "evmwlusiaaw",VX(4, 1344), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2540{ "evmwlumiaaw",VX(4, 1352), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2541
2542{ "evmwlssianw",VX(4, 1473), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2543{ "evmwlsmianw",VX(4, 1481), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2544{ "evmwlusianw",VX(4, 1472), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2545{ "evmwlumianw",VX(4, 1480), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2546
2547{ "evmwssf",   VX(4, 1107), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2548{ "evmwssfa",  VX(4, 1139), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2549{ "evmwsmf",   VX(4, 1115), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2550{ "evmwsmfa",  VX(4, 1147), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2551{ "evmwsmi",   VX(4, 1113), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2552{ "evmwsmia",  VX(4, 1145), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2553{ "evmwumi",   VX(4, 1112), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2554{ "evmwumia",  VX(4, 1144), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2555
2556{ "evmwssfaa", VX(4, 1363), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2557{ "evmwsmfaa", VX(4, 1371), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2558{ "evmwsmiaa", VX(4, 1369), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2559{ "evmwumiaa", VX(4, 1368), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2560
2561{ "evmwssfan", VX(4, 1491), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2562{ "evmwsmfan", VX(4, 1499), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2563{ "evmwsmian", VX(4, 1497), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2564{ "evmwumian", VX(4, 1496), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2565
2566{ "evaddssiaaw",VX(4, 1217), VX_MASK,	PPCSPE,		{ RS, RA } },
2567{ "evaddsmiaaw",VX(4, 1225), VX_MASK,	PPCSPE,		{ RS, RA } },
2568{ "evaddusiaaw",VX(4, 1216), VX_MASK,	PPCSPE,		{ RS, RA } },
2569{ "evaddumiaaw",VX(4, 1224), VX_MASK,	PPCSPE,		{ RS, RA } },
2570
2571{ "evsubfssiaaw",VX(4, 1219), VX_MASK,	PPCSPE,		{ RS, RA } },
2572{ "evsubfsmiaaw",VX(4, 1227), VX_MASK,	PPCSPE,		{ RS, RA } },
2573{ "evsubfusiaaw",VX(4, 1218), VX_MASK,	PPCSPE,		{ RS, RA } },
2574{ "evsubfumiaaw",VX(4, 1226), VX_MASK,	PPCSPE,		{ RS, RA } },
2575
2576{ "evmra",    VX(4, 1220), VX_MASK,	PPCSPE,		{ RS, RA } },
2577
2578{ "evdivws",  VX(4, 1222), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2579{ "evdivwu",  VX(4, 1223), VX_MASK,	PPCSPE,		{ RS, RA, RB } },
2580
2581{ "mulli",   OP(7),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2582{ "muli",    OP(7),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2583
2584{ "subfic",  OP(8),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2585{ "sfi",     OP(8),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2586
2587{ "dozi",    OP(9),	OP_MASK,	M601,		{ RT, RA, SI } },
2588
2589{ "bce",     B(9,0,0),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2590{ "bcel",    B(9,0,1),	B_MASK,		BOOKE64,	{ BO, BI, BD } },
2591{ "bcea",    B(9,1,0),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2592{ "bcela",   B(9,1,1),	B_MASK,		BOOKE64,	{ BO, BI, BDA } },
2593
2594{ "cmplwi",  OPL(10,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, UI } },
2595{ "cmpldi",  OPL(10,1), OPL_MASK,	PPC64,		{ OBF, RA, UI } },
2596{ "cmpli",   OP(10),	OP_MASK,	PPC,		{ BF, L, RA, UI } },
2597{ "cmpli",   OP(10),	OP_MASK,	PWRCOM,		{ BF, RA, UI } },
2598
2599{ "cmpwi",   OPL(11,0),	OPL_MASK,	PPCCOM,		{ OBF, RA, SI } },
2600{ "cmpdi",   OPL(11,1),	OPL_MASK,	PPC64,		{ OBF, RA, SI } },
2601{ "cmpi",    OP(11),	OP_MASK,	PPC,		{ BF, L, RA, SI } },
2602{ "cmpi",    OP(11),	OP_MASK,	PWRCOM,		{ BF, RA, SI } },
2603
2604{ "addic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2605{ "ai",	     OP(12),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2606{ "subic",   OP(12),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2607
2608{ "addic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, SI } },
2609{ "ai.",     OP(13),	OP_MASK,	PWRCOM,		{ RT, RA, SI } },
2610{ "subic.",  OP(13),	OP_MASK,	PPCCOM,		{ RT, RA, NSI } },
2611
2612{ "li",	     OP(14),	DRA_MASK,	PPCCOM,		{ RT, SI } },
2613{ "lil",     OP(14),	DRA_MASK,	PWRCOM,		{ RT, SI } },
2614{ "addi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, SI } },
2615{ "cal",     OP(14),	OP_MASK,	PWRCOM,		{ RT, D, RA0 } },
2616{ "subi",    OP(14),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2617{ "la",	     OP(14),	OP_MASK,	PPCCOM,		{ RT, D, RA0 } },
2618
2619{ "lis",     OP(15),	DRA_MASK,	PPCCOM,		{ RT, SISIGNOPT } },
2620{ "liu",     OP(15),	DRA_MASK,	PWRCOM,		{ RT, SISIGNOPT } },
2621{ "addis",   OP(15),	OP_MASK,	PPCCOM,		{ RT,RA0,SISIGNOPT } },
2622{ "cau",     OP(15),	OP_MASK,	PWRCOM,		{ RT,RA0,SISIGNOPT } },
2623{ "subis",   OP(15),	OP_MASK,	PPCCOM,		{ RT, RA0, NSI } },
2624
2625{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2626{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2627{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,	{ BD } },
2628{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,	{ BD } },
2629{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDM } },
2630{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BDP } },
2631{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,	{ BD } },
2632{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,	{ BD } },
2633{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2634{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2635{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2636{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2637{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDMA } },
2638{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDPA } },
2639{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,	{ BDA } },
2640{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,	{ BDA } },
2641{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2642{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2643{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,		{ BD } },
2644{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDM } },
2645{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,	{ BDP } },
2646{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,		{ BD } },
2647{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2648{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2649{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,		{ BDA } },
2650{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDMA } },
2651{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,	{ BDPA } },
2652{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,		{ BDA } },
2653{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2654{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2655{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2656{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2657{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2658{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2659{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2660{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2661{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2662{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2663{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2664{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2665{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2666{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2667{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2668{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2669{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2670{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2671{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2672{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2673{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2674{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2675{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2676{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2677{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2678{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2679{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2680{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2681{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2682{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2683{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2684{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2685{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2686{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2687{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2688{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2689{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2690{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2691{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2692{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2693{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2694{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2695{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2696{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2697{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2698{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2699{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2700{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2701{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2702{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2703{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2704{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2705{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2706{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2707{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2708{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2709{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2710{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2711{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2712{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2713{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2714{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2715{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2716{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2717{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2718{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2719{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2720{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2721{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2722{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2723{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2724{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2725{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2726{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2727{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2728{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2729{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2730{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2731{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2732{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2733{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2734{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2735{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2736{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2737{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2738{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2739{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2740{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2741{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2742{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2743{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2744{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2745{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2746{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2747{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2748{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2749{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2750{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2751{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2752{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2753{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2754{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2755{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2756{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2757{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2758{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2759{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2760{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2761{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2762{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2763{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2764{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2765{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2766{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2767{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2768{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2769{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2770{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2771{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2772{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2773{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2774{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2775{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,		{ CR, BD } },
2776{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2777{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2778{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,		{ CR, BD } },
2779{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2780{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2781{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,		{ CR, BDA } },
2782{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2783{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2784{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,		{ CR, BDA } },
2785{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2786{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2787{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2788{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDM } },
2789{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BDP } },
2790{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,	{ CR, BD } },
2791{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2792{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2793{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2794{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDMA } },
2795{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDPA } },
2796{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,	{ CR, BDA } },
2797{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2798{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2799{ "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2800{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2801{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2802{ "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2803{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2804{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2805{ "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2806{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2807{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2808{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2809{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2810{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2811{ "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2812{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2813{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2814{ "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2815{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2816{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2817{ "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2818{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2819{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2820{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2821{ "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2822{ "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2823{ "bt",	     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2824{ "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2825{ "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2826{ "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2827{ "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2828{ "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2829{ "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2830{ "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2831{ "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2832{ "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2833{ "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2834{ "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2835{ "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2836{ "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2837{ "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2838{ "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2839{ "bf",	     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2840{ "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2841{ "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDM } },
2842{ "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BDP } },
2843{ "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,	{ BI, BD } },
2844{ "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,	{ BI, BD } },
2845{ "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2846{ "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2847{ "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2848{ "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2849{ "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDMA } },
2850{ "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDPA } },
2851{ "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,	{ BI, BDA } },
2852{ "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,	{ BI, BDA } },
2853{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2854{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2855{ "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2856{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2857{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2858{ "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2859{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2860{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2861{ "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2862{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2863{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2864{ "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2865{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2866{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2867{ "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,	{ BI, BD } },
2868{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDM } },
2869{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,	{ BI, BDP } },
2870{ "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,	{ BI, BD } },
2871{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2872{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2873{ "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2874{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDMA } },
2875{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,	{ BI, BDPA } },
2876{ "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,	{ BI, BDA } },
2877{ "bc-",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
2878{ "bc+",     B(16,0,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
2879{ "bc",	     B(16,0,0),	B_MASK,		COM,		{ BO, BI, BD } },
2880{ "bcl-",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDM } },
2881{ "bcl+",    B(16,0,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDP } },
2882{ "bcl",     B(16,0,1),	B_MASK,		COM,		{ BO, BI, BD } },
2883{ "bca-",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
2884{ "bca+",    B(16,1,0),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
2885{ "bca",     B(16,1,0),	B_MASK,		COM,		{ BO, BI, BDA } },
2886{ "bcla-",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDMA } },
2887{ "bcla+",   B(16,1,1),	B_MASK,		PPCCOM,		{ BOE, BI, BDPA } },
2888{ "bcla",    B(16,1,1),	B_MASK,		COM,		{ BO, BI, BDA } },
2889
2890{ "sc",      SC(17,1,0), SC_MASK,	PPC,		{ LEV } },
2891{ "svc",     SC(17,0,0), SC_MASK,	POWER,		{ SVC_LEV, FL1, FL2 } },
2892{ "svcl",    SC(17,0,1), SC_MASK,	POWER,		{ SVC_LEV, FL1, FL2 } },
2893{ "svca",    SC(17,1,0), SC_MASK,	PWRCOM,		{ SV } },
2894{ "svcla",   SC(17,1,1), SC_MASK,	POWER,		{ SV } },
2895
2896{ "b",	     B(18,0,0),	B_MASK,		COM,		{ LI } },
2897{ "bl",      B(18,0,1),	B_MASK,		COM,		{ LI } },
2898{ "ba",      B(18,1,0),	B_MASK,		COM,		{ LIA } },
2899{ "bla",     B(18,1,1),	B_MASK,		COM,		{ LIA } },
2900
2901{ "mcrf",    XL(19,0),	XLBB_MASK|(3 << 21)|(3 << 16), COM,	{ BF, BFA } },
2902
2903{ "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2904{ "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,	{ 0 } },
2905{ "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2906{ "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,	{ 0 } },
2907{ "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2908{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2909{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2910{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2911{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2912{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2913{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2914{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2915{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2916{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2917{ "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2918{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2919{ "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2920{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2921{ "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,	{ 0 } },
2922{ "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,	{ 0 } },
2923{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2924{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2925{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,	{ 0 } },
2926{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,	{ 0 } },
2927{ "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2928{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2929{ "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2930{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2931{ "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2932{ "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2933{ "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2934{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2935{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2936{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2937{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2938{ "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2939{ "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2940{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2941{ "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2942{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943{ "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2944{ "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2945{ "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2946{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2947{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2948{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2949{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2950{ "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2951{ "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2952{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953{ "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2954{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955{ "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2956{ "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2957{ "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2958{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2959{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2960{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2961{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2962{ "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2963{ "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2964{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965{ "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2966{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2967{ "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2968{ "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2969{ "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2970{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2971{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2972{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2974{ "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2975{ "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2976{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2977{ "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2978{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2979{ "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2980{ "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2981{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2982{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2983{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2984{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2985{ "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2986{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2987{ "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2988{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2989{ "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2990{ "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2991{ "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2992{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2994{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2996{ "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2997{ "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2998{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2999{ "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3000{ "bnllr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3001{ "bnllr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3002{ "bnlr",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3003{ "bnllrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3004{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3006{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3007{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3008{ "bnlrl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3009{ "blelr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3010{ "blelr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3011{ "blelr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3012{ "blelr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013{ "blelr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3014{ "bler",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3015{ "blelrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3016{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3017{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3018{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3019{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3020{ "blerl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3021{ "bnglr",   XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3022{ "bnglr-",  XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023{ "bnglr-",  XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3024{ "bnglr+",  XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025{ "bnglr+",  XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3026{ "bngr",    XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3027{ "bnglrl",  XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3028{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3029{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3030{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3031{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3032{ "bngrl",   XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3033{ "bnelr",   XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3034{ "bnelr-",  XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035{ "bnelr-",  XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3036{ "bnelr+",  XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3037{ "bnelr+",  XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3038{ "bner",    XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3039{ "bnelrl",  XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3040{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3041{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3042{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3044{ "bnerl",   XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3045{ "bnslr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3046{ "bnslr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3047{ "bnslr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3048{ "bnslr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3049{ "bnslr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3050{ "bnsr",    XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
3051{ "bnslrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3052{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3054{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3056{ "bnsrl",   XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
3057{ "bnulr",   XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3058{ "bnulr-",  XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3059{ "bnulr-",  XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3060{ "bnulr+",  XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3061{ "bnulr+",  XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
3062{ "bnulrl",  XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3063{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3064{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3065{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3066{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
3067{ "btlr",    XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3068{ "btlr-",   XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3069{ "btlr-",   XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3070{ "btlr+",   XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3071{ "btlr+",   XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3072{ "bbtr",    XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
3073{ "btlrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3074{ "btlrl-",  XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3075{ "btlrl-",  XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3076{ "btlrl+",  XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3077{ "btlrl+",  XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3078{ "bbtrl",   XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
3079{ "bflr",    XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3080{ "bflr-",   XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3081{ "bflr-",   XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3082{ "bflr+",   XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3083{ "bflr+",   XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4,	{ BI } },
3084{ "bbfr",    XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM,	{ BI } },
3085{ "bflrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3086{ "bflrl-",  XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3087{ "bflrl-",  XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3088{ "bflrl+",  XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3089{ "bflrl+",  XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4,	{ BI } },
3090{ "bbfrl",   XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM,	{ BI } },
3091{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3092{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3093{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3094{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3095{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3096{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3097{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3098{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3099{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3100{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3101{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3102{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3103{ "bdztlr",  XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3104{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3105{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3106{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3107{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3108{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3109{ "bdzflr",  XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM,	{ BI } },
3110{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3111{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
3112{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM,	{ BI } },
3113{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3114{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
3115{ "bclr+",   XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3116{ "bclrl+",  XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3117{ "bclr-",   XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3118{ "bclrl-",  XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM,	{ BOE, BI } },
3119{ "bclr",    XLLK(19,16,0), XLBH_MASK,	PPCCOM,		{ BO, BI, BH } },
3120{ "bclrl",   XLLK(19,16,1), XLBH_MASK,	PPCCOM,		{ BO, BI, BH } },
3121{ "bcr",     XLLK(19,16,0), XLBB_MASK,	PWRCOM,		{ BO, BI } },
3122{ "bcrl",    XLLK(19,16,1), XLBB_MASK,	PWRCOM,		{ BO, BI } },
3123{ "bclre",   XLLK(19,17,0), XLBB_MASK,	BOOKE64,	{ BO, BI } },
3124{ "bclrel",  XLLK(19,17,1), XLBB_MASK,	BOOKE64,	{ BO, BI } },
3125
3126{ "rfid",    XL(19,18),	0xffffffff,	PPC64,		{ 0 } },
3127
3128{ "crnot",   XL(19,33), XL_MASK,	PPCCOM,		{ BT, BA, BBA } },
3129{ "crnor",   XL(19,33),	XL_MASK,	COM,		{ BT, BA, BB } },
3130{ "rfmci",    X(19,38), 0xffffffff,	PPCRFMCI,	{ 0 } },
3131
3132{ "rfi",     XL(19,50),	0xffffffff,	COM,		{ 0 } },
3133{ "rfci",    XL(19,51),	0xffffffff,	PPC403 | BOOKE,	{ 0 } },
3134
3135{ "rfsvc",   XL(19,82),	0xffffffff,	POWER,		{ 0 } },
3136
3137{ "crandc",  XL(19,129), XL_MASK,	COM,		{ BT, BA, BB } },
3138
3139{ "isync",   XL(19,150), 0xffffffff,	PPCCOM,		{ 0 } },
3140{ "ics",     XL(19,150), 0xffffffff,	PWRCOM,		{ 0 } },
3141
3142{ "crclr",   XL(19,193), XL_MASK,	PPCCOM,		{ BT, BAT, BBA } },
3143{ "crxor",   XL(19,193), XL_MASK,	COM,		{ BT, BA, BB } },
3144
3145{ "crnand",  XL(19,225), XL_MASK,	COM,		{ BT, BA, BB } },
3146
3147{ "crand",   XL(19,257), XL_MASK,	COM,		{ BT, BA, BB } },
3148
3149{ "hrfid",   XL(19,274), 0xffffffff,	POWER5 | CELL,	{ 0 } },
3150
3151{ "crset",   XL(19,289), XL_MASK,	PPCCOM,		{ BT, BAT, BBA } },
3152{ "creqv",   XL(19,289), XL_MASK,	COM,		{ BT, BA, BB } },
3153
3154{ "doze",    XL(19,402), 0xffffffff,	POWER6,		{ 0 } },
3155
3156{ "crorc",   XL(19,417), XL_MASK,	COM,		{ BT, BA, BB } },
3157
3158{ "nap",     XL(19,434), 0xffffffff,	POWER6,		{ 0 } },
3159
3160{ "crmove",  XL(19,449), XL_MASK,	PPCCOM,		{ BT, BA, BBA } },
3161{ "cror",    XL(19,449), XL_MASK,	COM,		{ BT, BA, BB } },
3162
3163{ "sleep",   XL(19,466), 0xffffffff,	POWER6,		{ 0 } },
3164{ "rvwinkle", XL(19,498), 0xffffffff,	POWER6,		{ 0 } },
3165
3166{ "bctr",    XLO(19,BOU,528,0), XLBOBIBB_MASK, COM,	{ 0 } },
3167{ "bctrl",   XLO(19,BOU,528,1), XLBOBIBB_MASK, COM,	{ 0 } },
3168{ "bltctr",  XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3169{ "bltctr-", XLOCB(19,BOT,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3170{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3171{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3172{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3173{ "bltctrl", XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3174{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3175{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3176{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3177{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3178{ "bgtctr",  XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3179{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3180{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3181{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3182{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3183{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3184{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3185{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3186{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3187{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3188{ "beqctr",  XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3189{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3190{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3191{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3192{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3193{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3194{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3195{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3196{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3197{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3198{ "bsoctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3199{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3200{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3201{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3202{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3203{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3204{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3205{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3206{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3207{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3208{ "bunctr",  XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3209{ "bunctr-", XLOCB(19,BOT,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3210{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3211{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3212{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3213{ "bunctrl", XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3214{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3215{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3216{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3217{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3218{ "bgectr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3219{ "bgectr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3220{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3221{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3222{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3223{ "bgectrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3224{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3225{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3226{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3227{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3228{ "bnlctr",  XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3229{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3230{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3231{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3232{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3233{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3234{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3235{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3236{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3237{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3238{ "blectr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3239{ "blectr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3240{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3241{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3242{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3243{ "blectrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3244{ "blectrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3245{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3246{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3247{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3248{ "bngctr",  XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3249{ "bngctr-", XLOCB(19,BOF,CBGT,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3250{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3251{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3252{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3253{ "bngctrl", XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3254{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3255{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3256{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3257{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3258{ "bnectr",  XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3259{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3260{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3261{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3262{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3263{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3264{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3265{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3266{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3267{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3268{ "bnsctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3269{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3270{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3271{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3272{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3273{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3274{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3275{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3276{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3277{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3278{ "bnuctr",  XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3279{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3280{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3281{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3282{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3283{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, PPCCOM,	{ CR } },
3284{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1),  XLBOCBBB_MASK, NOPOWER4, { CR } },
3285{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3286{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3287{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3288{ "btctr",   XLO(19,BOT,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
3289{ "btctr-",  XLO(19,BOT,528,0),  XLBOBB_MASK, NOPOWER4,	{ BI } },
3290{ "btctr-",  XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3291{ "btctr+",  XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4,	{ BI } },
3292{ "btctr+",  XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3293{ "btctrl",  XLO(19,BOT,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
3294{ "btctrl-", XLO(19,BOT,528,1),  XLBOBB_MASK, NOPOWER4,	{ BI } },
3295{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3296{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4,	{ BI } },
3297{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3298{ "bfctr",   XLO(19,BOF,528,0),  XLBOBB_MASK, PPCCOM,	{ BI } },
3299{ "bfctr-",  XLO(19,BOF,528,0),  XLBOBB_MASK, NOPOWER4, { BI } },
3300{ "bfctr-",  XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3301{ "bfctr+",  XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3302{ "bfctr+",  XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3303{ "bfctrl",  XLO(19,BOF,528,1),  XLBOBB_MASK, PPCCOM,	{ BI } },
3304{ "bfctrl-", XLO(19,BOF,528,1),  XLBOBB_MASK, NOPOWER4, { BI } },
3305{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3306{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3307{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3308{ "bcctr-",  XLYLK(19,528,0,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3309{ "bcctr+",  XLYLK(19,528,1,0),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3310{ "bcctrl-", XLYLK(19,528,0,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3311{ "bcctrl+", XLYLK(19,528,1,1),  XLYBB_MASK,  PPCCOM,	{ BOE, BI } },
3312{ "bcctr",   XLLK(19,528,0),     XLBH_MASK,   PPCCOM,	{ BO, BI, BH } },
3313{ "bcctrl",  XLLK(19,528,1),     XLBH_MASK,   PPCCOM,	{ BO, BI, BH } },
3314{ "bcc",     XLLK(19,528,0),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
3315{ "bccl",    XLLK(19,528,1),     XLBB_MASK,   PWRCOM,	{ BO, BI } },
3316{ "bcctre",  XLLK(19,529,0),     XLBB_MASK,   BOOKE64,	{ BO, BI } },
3317{ "bcctrel", XLLK(19,529,1),     XLBB_MASK,   BOOKE64,	{ BO, BI } },
3318
3319{ "rlwimi",  M(20,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3320{ "rlimi",   M(20,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3321
3322{ "rlwimi.", M(20,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3323{ "rlimi.",  M(20,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3324
3325{ "rotlwi",  MME(21,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, SH } },
3326{ "clrlwi",  MME(21,31,0), MSHME_MASK,	PPCCOM,		{ RA, RS, MB } },
3327{ "rlwinm",  M(21,0),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3328{ "rlinm",   M(21,0),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3329{ "rotlwi.", MME(21,31,1), MMBME_MASK,	PPCCOM,		{ RA,RS,SH } },
3330{ "clrlwi.", MME(21,31,1), MSHME_MASK,	PPCCOM,		{ RA, RS, MB } },
3331{ "rlwinm.", M(21,1),	M_MASK,		PPCCOM,		{ RA,RS,SH,MBE,ME } },
3332{ "rlinm.",  M(21,1),	M_MASK,		PWRCOM,		{ RA,RS,SH,MBE,ME } },
3333
3334{ "rlmi",    M(22,0),	M_MASK,		M601,		{ RA,RS,RB,MBE,ME } },
3335{ "rlmi.",   M(22,1),	M_MASK,		M601,		{ RA,RS,RB,MBE,ME } },
3336
3337{ "be",	     B(22,0,0),	B_MASK,		BOOKE64,	{ LI } },
3338{ "bel",     B(22,0,1),	B_MASK,		BOOKE64,	{ LI } },
3339{ "bea",     B(22,1,0),	B_MASK,		BOOKE64,	{ LIA } },
3340{ "bela",    B(22,1,1),	B_MASK,		BOOKE64,	{ LIA } },
3341
3342{ "rotlw",   MME(23,31,0), MMBME_MASK,	PPCCOM,		{ RA, RS, RB } },
3343{ "rlwnm",   M(23,0),	M_MASK,		PPCCOM,		{ RA,RS,RB,MBE,ME } },
3344{ "rlnm",    M(23,0),	M_MASK,		PWRCOM,		{ RA,RS,RB,MBE,ME } },
3345{ "rotlw.",  MME(23,31,1), MMBME_MASK,	PPCCOM,		{ RA, RS, RB } },
3346{ "rlwnm.",  M(23,1),	M_MASK,		PPCCOM,		{ RA,RS,RB,MBE,ME } },
3347{ "rlnm.",   M(23,1),	M_MASK,		PWRCOM,		{ RA,RS,RB,MBE,ME } },
3348
3349{ "nop",     OP(24),	0xffffffff,	PPCCOM,		{ 0 } },
3350{ "ori",     OP(24),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3351{ "oril",    OP(24),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3352
3353{ "oris",    OP(25),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3354{ "oriu",    OP(25),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3355
3356{ "xori",    OP(26),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3357{ "xoril",   OP(26),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3358
3359{ "xoris",   OP(27),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3360{ "xoriu",   OP(27),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3361
3362{ "andi.",   OP(28),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3363{ "andil.",  OP(28),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3364
3365{ "andis.",  OP(29),	OP_MASK,	PPCCOM,		{ RA, RS, UI } },
3366{ "andiu.",  OP(29),	OP_MASK,	PWRCOM,		{ RA, RS, UI } },
3367
3368{ "rotldi",  MD(30,0,0), MDMB_MASK,	PPC64,		{ RA, RS, SH6 } },
3369{ "clrldi",  MD(30,0,0), MDSH_MASK,	PPC64,		{ RA, RS, MB6 } },
3370{ "rldicl",  MD(30,0,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3371{ "rotldi.", MD(30,0,1), MDMB_MASK,	PPC64,		{ RA, RS, SH6 } },
3372{ "clrldi.", MD(30,0,1), MDSH_MASK,	PPC64,		{ RA, RS, MB6 } },
3373{ "rldicl.", MD(30,0,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3374
3375{ "rldicr",  MD(30,1,0), MD_MASK,	PPC64,		{ RA, RS, SH6, ME6 } },
3376{ "rldicr.", MD(30,1,1), MD_MASK,	PPC64,		{ RA, RS, SH6, ME6 } },
3377
3378{ "rldic",   MD(30,2,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3379{ "rldic.",  MD(30,2,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3380
3381{ "rldimi",  MD(30,3,0), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3382{ "rldimi.", MD(30,3,1), MD_MASK,	PPC64,		{ RA, RS, SH6, MB6 } },
3383
3384{ "rotld",   MDS(30,8,0), MDSMB_MASK,	PPC64,		{ RA, RS, RB } },
3385{ "rldcl",   MDS(30,8,0), MDS_MASK,	PPC64,		{ RA, RS, RB, MB6 } },
3386{ "rotld.",  MDS(30,8,1), MDSMB_MASK,	PPC64,		{ RA, RS, RB } },
3387{ "rldcl.",  MDS(30,8,1), MDS_MASK,	PPC64,		{ RA, RS, RB, MB6 } },
3388
3389{ "rldcr",   MDS(30,9,0), MDS_MASK,	PPC64,		{ RA, RS, RB, ME6 } },
3390{ "rldcr.",  MDS(30,9,1), MDS_MASK,	PPC64,		{ RA, RS, RB, ME6 } },
3391
3392{ "cmpw",    XOPL(31,0,0), XCMPL_MASK, PPCCOM,		{ OBF, RA, RB } },
3393{ "cmpd",    XOPL(31,0,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
3394{ "cmp",     X(31,0),	XCMP_MASK,	PPC,		{ BF, L, RA, RB } },
3395{ "cmp",     X(31,0),	XCMPL_MASK,	PWRCOM,		{ BF, RA, RB } },
3396
3397{ "twlgt",   XTO(31,4,TOLGT), XTO_MASK, PPCCOM,		{ RA, RB } },
3398{ "tlgt",    XTO(31,4,TOLGT), XTO_MASK, PWRCOM,		{ RA, RB } },
3399{ "twllt",   XTO(31,4,TOLLT), XTO_MASK, PPCCOM,		{ RA, RB } },
3400{ "tllt",    XTO(31,4,TOLLT), XTO_MASK, PWRCOM,		{ RA, RB } },
3401{ "tweq",    XTO(31,4,TOEQ), XTO_MASK,	PPCCOM,		{ RA, RB } },
3402{ "teq",     XTO(31,4,TOEQ), XTO_MASK,	PWRCOM,		{ RA, RB } },
3403{ "twlge",   XTO(31,4,TOLGE), XTO_MASK, PPCCOM,		{ RA, RB } },
3404{ "tlge",    XTO(31,4,TOLGE), XTO_MASK, PWRCOM,		{ RA, RB } },
3405{ "twlnl",   XTO(31,4,TOLNL), XTO_MASK, PPCCOM,		{ RA, RB } },
3406{ "tlnl",    XTO(31,4,TOLNL), XTO_MASK, PWRCOM,		{ RA, RB } },
3407{ "twlle",   XTO(31,4,TOLLE), XTO_MASK, PPCCOM,		{ RA, RB } },
3408{ "tlle",    XTO(31,4,TOLLE), XTO_MASK, PWRCOM,		{ RA, RB } },
3409{ "twlng",   XTO(31,4,TOLNG), XTO_MASK, PPCCOM,		{ RA, RB } },
3410{ "tlng",    XTO(31,4,TOLNG), XTO_MASK, PWRCOM,		{ RA, RB } },
3411{ "twgt",    XTO(31,4,TOGT), XTO_MASK,	PPCCOM,		{ RA, RB } },
3412{ "tgt",     XTO(31,4,TOGT), XTO_MASK,	PWRCOM,		{ RA, RB } },
3413{ "twge",    XTO(31,4,TOGE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3414{ "tge",     XTO(31,4,TOGE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3415{ "twnl",    XTO(31,4,TONL), XTO_MASK,	PPCCOM,		{ RA, RB } },
3416{ "tnl",     XTO(31,4,TONL), XTO_MASK,	PWRCOM,		{ RA, RB } },
3417{ "twlt",    XTO(31,4,TOLT), XTO_MASK,	PPCCOM,		{ RA, RB } },
3418{ "tlt",     XTO(31,4,TOLT), XTO_MASK,	PWRCOM,		{ RA, RB } },
3419{ "twle",    XTO(31,4,TOLE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3420{ "tle",     XTO(31,4,TOLE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3421{ "twng",    XTO(31,4,TONG), XTO_MASK,	PPCCOM,		{ RA, RB } },
3422{ "tng",     XTO(31,4,TONG), XTO_MASK,	PWRCOM,		{ RA, RB } },
3423{ "twne",    XTO(31,4,TONE), XTO_MASK,	PPCCOM,		{ RA, RB } },
3424{ "tne",     XTO(31,4,TONE), XTO_MASK,	PWRCOM,		{ RA, RB } },
3425{ "trap",    XTO(31,4,TOU), 0xffffffff,	PPCCOM,		{ 0 } },
3426{ "tw",      X(31,4),	X_MASK,		PPCCOM,		{ TO, RA, RB } },
3427{ "t",       X(31,4),	X_MASK,		PWRCOM,		{ TO, RA, RB } },
3428
3429{ "subfc",   XO(31,8,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3430{ "sf",      XO(31,8,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3431{ "subc",    XO(31,8,0,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3432{ "subfc.",  XO(31,8,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3433{ "sf.",     XO(31,8,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3434{ "subc.",   XO(31,8,0,1), XO_MASK,	PPCCOM,		{ RT, RB, RA } },
3435{ "subfco",  XO(31,8,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3436{ "sfo",     XO(31,8,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3437{ "subco",   XO(31,8,1,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3438{ "subfco.", XO(31,8,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3439{ "sfo.",    XO(31,8,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3440{ "subco.",  XO(31,8,1,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3441
3442{ "mulhdu",  XO(31,9,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3443{ "mulhdu.", XO(31,9,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3444
3445{ "addc",    XO(31,10,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3446{ "a",       XO(31,10,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3447{ "addc.",   XO(31,10,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3448{ "a.",      XO(31,10,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3449{ "addco",   XO(31,10,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3450{ "ao",      XO(31,10,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3451{ "addco.",  XO(31,10,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3452{ "ao.",     XO(31,10,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3453
3454{ "mulhwu",  XO(31,11,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3455{ "mulhwu.", XO(31,11,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3456
3457{ "isellt",  X(31,15),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3458{ "iselgt",  X(31,47),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3459{ "iseleq",  X(31,79),      X_MASK,	PPCISEL,	{ RT, RA, RB } },
3460{ "isel",    XISEL(31,15),  XISEL_MASK,	PPCISEL,	{ RT, RA, RB, CRB } },
3461
3462{ "mfocrf",  XFXM(31,19,0,1), XFXFXM_MASK, COM,		{ RT, FXM } },
3463{ "mfcr",    X(31,19),	XRARB_MASK,	NOPOWER4 | COM,	{ RT } },
3464{ "mfcr",    X(31,19),	XFXFXM_MASK,	POWER4,		{ RT, FXM4 } },
3465
3466{ "lwarx",   X(31,20),	XEH_MASK,	PPC,		{ RT, RA0, RB, EH } },
3467
3468{ "ldx",     X(31,21),	X_MASK,		PPC64,		{ RT, RA0, RB } },
3469
3470{ "icbt",    X(31,22),	X_MASK,		BOOKE|PPCE300,	{ CT, RA, RB } },
3471{ "icbt",    X(31,262),	XRT_MASK,	PPC403,		{ RA, RB } },
3472
3473{ "lwzx",    X(31,23),	X_MASK,		PPCCOM,		{ RT, RA0, RB } },
3474{ "lx",      X(31,23),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
3475
3476{ "slw",     XRC(31,24,0), X_MASK,	PPCCOM,		{ RA, RS, RB } },
3477{ "sl",      XRC(31,24,0), X_MASK,	PWRCOM,		{ RA, RS, RB } },
3478{ "slw.",    XRC(31,24,1), X_MASK,	PPCCOM,		{ RA, RS, RB } },
3479{ "sl.",     XRC(31,24,1), X_MASK,	PWRCOM,		{ RA, RS, RB } },
3480
3481{ "cntlzw",  XRC(31,26,0), XRB_MASK,	PPCCOM,		{ RA, RS } },
3482{ "cntlz",   XRC(31,26,0), XRB_MASK,	PWRCOM,		{ RA, RS } },
3483{ "cntlzw.", XRC(31,26,1), XRB_MASK,	PPCCOM,		{ RA, RS } },
3484{ "cntlz.",  XRC(31,26,1), XRB_MASK, 	PWRCOM,		{ RA, RS } },
3485
3486{ "sld",     XRC(31,27,0), X_MASK,	PPC64,		{ RA, RS, RB } },
3487{ "sld.",    XRC(31,27,1), X_MASK,	PPC64,		{ RA, RS, RB } },
3488
3489{ "and",     XRC(31,28,0), X_MASK,	COM,		{ RA, RS, RB } },
3490{ "and.",    XRC(31,28,1), X_MASK,	COM,		{ RA, RS, RB } },
3491
3492{ "maskg",   XRC(31,29,0), X_MASK,	M601,		{ RA, RS, RB } },
3493{ "maskg.",  XRC(31,29,1), X_MASK,	M601,		{ RA, RS, RB } },
3494
3495{ "icbte",   X(31,30),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3496
3497{ "lwzxe",   X(31,31),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3498
3499{ "cmplw",   XOPL(31,32,0), XCMPL_MASK, PPCCOM,	{ OBF, RA, RB } },
3500{ "cmpld",   XOPL(31,32,1), XCMPL_MASK, PPC64,		{ OBF, RA, RB } },
3501{ "cmpl",    X(31,32),	XCMP_MASK,	 PPC,		{ BF, L, RA, RB } },
3502{ "cmpl",    X(31,32),	XCMPL_MASK,	 PWRCOM,	{ BF, RA, RB } },
3503
3504{ "subf",    XO(31,40,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3505{ "sub",     XO(31,40,0,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3506{ "subf.",   XO(31,40,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3507{ "sub.",    XO(31,40,0,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3508{ "subfo",   XO(31,40,1,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3509{ "subo",    XO(31,40,1,0), XO_MASK,	PPC,		{ RT, RB, RA } },
3510{ "subfo.",  XO(31,40,1,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3511{ "subo.",   XO(31,40,1,1), XO_MASK,	PPC,		{ RT, RB, RA } },
3512
3513{ "ldux",    X(31,53),	X_MASK,		PPC64,		{ RT, RAL, RB } },
3514
3515{ "dcbst",   X(31,54),	XRT_MASK,	PPC,		{ RA, RB } },
3516
3517{ "lwzux",   X(31,55),	X_MASK,		PPCCOM,		{ RT, RAL, RB } },
3518{ "lux",     X(31,55),	X_MASK,		PWRCOM,		{ RT, RA, RB } },
3519
3520{ "dcbste",  X(31,62),	XRT_MASK,	BOOKE64,	{ RA, RB } },
3521
3522{ "lwzuxe",  X(31,63),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3523
3524{ "cntlzd",  XRC(31,58,0), XRB_MASK,	PPC64,		{ RA, RS } },
3525{ "cntlzd.", XRC(31,58,1), XRB_MASK,	PPC64,		{ RA, RS } },
3526
3527{ "andc",    XRC(31,60,0), X_MASK,	COM,		{ RA, RS, RB } },
3528{ "andc.",   XRC(31,60,1), X_MASK,	COM,		{ RA, RS, RB } },
3529
3530{ "tdlgt",   XTO(31,68,TOLGT), XTO_MASK, PPC64,		{ RA, RB } },
3531{ "tdllt",   XTO(31,68,TOLLT), XTO_MASK, PPC64,		{ RA, RB } },
3532{ "tdeq",    XTO(31,68,TOEQ), XTO_MASK,  PPC64,		{ RA, RB } },
3533{ "tdlge",   XTO(31,68,TOLGE), XTO_MASK, PPC64,		{ RA, RB } },
3534{ "tdlnl",   XTO(31,68,TOLNL), XTO_MASK, PPC64,		{ RA, RB } },
3535{ "tdlle",   XTO(31,68,TOLLE), XTO_MASK, PPC64,		{ RA, RB } },
3536{ "tdlng",   XTO(31,68,TOLNG), XTO_MASK, PPC64,		{ RA, RB } },
3537{ "tdgt",    XTO(31,68,TOGT), XTO_MASK,  PPC64,		{ RA, RB } },
3538{ "tdge",    XTO(31,68,TOGE), XTO_MASK,  PPC64,		{ RA, RB } },
3539{ "tdnl",    XTO(31,68,TONL), XTO_MASK,  PPC64,		{ RA, RB } },
3540{ "tdlt",    XTO(31,68,TOLT), XTO_MASK,  PPC64,		{ RA, RB } },
3541{ "tdle",    XTO(31,68,TOLE), XTO_MASK,  PPC64,		{ RA, RB } },
3542{ "tdng",    XTO(31,68,TONG), XTO_MASK,  PPC64,		{ RA, RB } },
3543{ "tdne",    XTO(31,68,TONE), XTO_MASK,  PPC64,		{ RA, RB } },
3544{ "td",	     X(31,68),	X_MASK,		 PPC64,		{ TO, RA, RB } },
3545
3546{ "mulhd",   XO(31,73,0,0), XO_MASK,	 PPC64,		{ RT, RA, RB } },
3547{ "mulhd.",  XO(31,73,0,1), XO_MASK,	 PPC64,		{ RT, RA, RB } },
3548
3549{ "mulhw",   XO(31,75,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
3550{ "mulhw.",  XO(31,75,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
3551
3552{ "dlmzb",   XRC(31,78,0),  X_MASK,	PPC403|PPC440,	{ RA, RS, RB } },
3553{ "dlmzb.",  XRC(31,78,1),  X_MASK,	PPC403|PPC440,	{ RA, RS, RB } },
3554
3555{ "mtsrd",   X(31,82),	XRB_MASK|(1<<20), PPC64,	{ SR, RS } },
3556
3557{ "mfmsr",   X(31,83),	XRARB_MASK,	COM,		{ RT } },
3558
3559{ "ldarx",   X(31,84),	XEH_MASK,	PPC64,		{ RT, RA0, RB, EH } },
3560
3561{ "dcbfl",   XOPL(31,86,1), XRT_MASK,	POWER5,		{ RA, RB } },
3562{ "dcbf",    X(31,86),	XLRT_MASK,	PPC,		{ RA, RB, L } },
3563
3564{ "lbzx",    X(31,87),	X_MASK,		COM,		{ RT, RA0, RB } },
3565
3566{ "dcbfe",   X(31,94),	XRT_MASK,	BOOKE64,	{ RA, RB } },
3567
3568{ "lbzxe",   X(31,95),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3569
3570{ "neg",     XO(31,104,0,0), XORB_MASK,	COM,		{ RT, RA } },
3571{ "neg.",    XO(31,104,0,1), XORB_MASK,	COM,		{ RT, RA } },
3572{ "nego",    XO(31,104,1,0), XORB_MASK,	COM,		{ RT, RA } },
3573{ "nego.",   XO(31,104,1,1), XORB_MASK,	COM,		{ RT, RA } },
3574
3575{ "mul",     XO(31,107,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3576{ "mul.",    XO(31,107,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3577{ "mulo",    XO(31,107,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3578{ "mulo.",   XO(31,107,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3579
3580{ "mtsrdin", X(31,114),	XRA_MASK,	PPC64,		{ RS, RB } },
3581
3582{ "clf",     X(31,118), XTO_MASK,	POWER,		{ RA, RB } },
3583
3584{ "lbzux",   X(31,119),	X_MASK,		COM,		{ RT, RAL, RB } },
3585
3586{ "popcntb", X(31,122), XRB_MASK,	POWER5,		{ RA, RS } },
3587
3588{ "not",     XRC(31,124,0), X_MASK,	COM,		{ RA, RS, RBS } },
3589{ "nor",     XRC(31,124,0), X_MASK,	COM,		{ RA, RS, RB } },
3590{ "not.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RBS } },
3591{ "nor.",    XRC(31,124,1), X_MASK,	COM,		{ RA, RS, RB } },
3592
3593{ "lwarxe",  X(31,126),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3594
3595{ "lbzuxe",  X(31,127),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3596
3597{ "wrtee",   X(31,131),	XRARB_MASK,	PPC403 | BOOKE,	{ RS } },
3598
3599{ "dcbtstls",X(31,134),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3600
3601{ "subfe",   XO(31,136,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3602{ "sfe",     XO(31,136,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3603{ "subfe.",  XO(31,136,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3604{ "sfe.",    XO(31,136,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3605{ "subfeo",  XO(31,136,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3606{ "sfeo",    XO(31,136,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3607{ "subfeo.", XO(31,136,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3608{ "sfeo.",   XO(31,136,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3609
3610{ "adde",    XO(31,138,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3611{ "ae",      XO(31,138,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3612{ "adde.",   XO(31,138,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3613{ "ae.",     XO(31,138,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3614{ "addeo",   XO(31,138,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3615{ "aeo",     XO(31,138,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3616{ "addeo.",  XO(31,138,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3617{ "aeo.",    XO(31,138,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3618
3619{ "dcbtstlse",X(31,142),X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3620
3621{ "mtocrf",  XFXM(31,144,0,1), XFXFXM_MASK, COM,	{ FXM, RS } },
3622{ "mtcr",    XFXM(31,144,0xff,0), XRARB_MASK, COM,	{ RS }},
3623{ "mtcrf",   X(31,144),	XFXFXM_MASK,	COM,		{ FXM, RS } },
3624
3625{ "mtmsr",   X(31,146),	XRARB_MASK,	COM,		{ RS } },
3626
3627{ "stdx",    X(31,149), X_MASK,		PPC64,		{ RS, RA0, RB } },
3628
3629{ "stwcx.",  XRC(31,150,1), X_MASK,	PPC,		{ RS, RA0, RB } },
3630
3631{ "stwx",    X(31,151), X_MASK,		PPCCOM,		{ RS, RA0, RB } },
3632{ "stx",     X(31,151), X_MASK,		PWRCOM,		{ RS, RA, RB } },
3633
3634{ "stwcxe.", XRC(31,158,1), X_MASK,	BOOKE64,	{ RS, RA0, RB } },
3635
3636{ "stwxe",   X(31,159), X_MASK,		BOOKE64,	{ RS, RA0, RB } },
3637
3638{ "slq",     XRC(31,152,0), X_MASK,	M601,		{ RA, RS, RB } },
3639{ "slq.",    XRC(31,152,1), X_MASK,	M601,		{ RA, RS, RB } },
3640
3641{ "sle",     XRC(31,153,0), X_MASK,	M601,		{ RA, RS, RB } },
3642{ "sle.",    XRC(31,153,1), X_MASK,	M601,		{ RA, RS, RB } },
3643
3644{ "prtyw",   X(31,154),	XRB_MASK,	POWER6,		{ RA, RS } },
3645
3646{ "wrteei",  X(31,163),	XE_MASK,	PPC403 | BOOKE,	{ E } },
3647
3648{ "dcbtls",  X(31,166),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3649{ "dcbtlse", X(31,174),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3650
3651{ "mtmsrd",  X(31,178),	XRLARB_MASK,	PPC64,		{ RS, A_L } },
3652
3653{ "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
3654
3655{ "stwux",   X(31,183),	X_MASK,		PPCCOM,		{ RS, RAS, RB } },
3656{ "stux",    X(31,183),	X_MASK,		PWRCOM,		{ RS, RA0, RB } },
3657
3658{ "sliq",    XRC(31,184,0), X_MASK,	M601,		{ RA, RS, SH } },
3659{ "sliq.",   XRC(31,184,1), X_MASK,	M601,		{ RA, RS, SH } },
3660
3661{ "prtyd",   X(31,186),	XRB_MASK,	POWER6,		{ RA, RS } },
3662
3663{ "stwuxe",  X(31,191),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
3664
3665{ "subfze",  XO(31,200,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3666{ "sfze",    XO(31,200,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3667{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3668{ "sfze.",   XO(31,200,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3669{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3670{ "sfzeo",   XO(31,200,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3671{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3672{ "sfzeo.",  XO(31,200,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3673
3674{ "addze",   XO(31,202,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3675{ "aze",     XO(31,202,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3676{ "addze.",  XO(31,202,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3677{ "aze.",    XO(31,202,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3678{ "addzeo",  XO(31,202,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3679{ "azeo",    XO(31,202,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3680{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3681{ "azeo.",   XO(31,202,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3682
3683{ "mtsr",    X(31,210),	XRB_MASK|(1<<20), COM32,	{ SR, RS } },
3684
3685{ "stdcx.",  XRC(31,214,1), X_MASK,	PPC64,		{ RS, RA0, RB } },
3686
3687{ "stbx",    X(31,215),	X_MASK,		COM,		{ RS, RA0, RB } },
3688
3689{ "sllq",    XRC(31,216,0), X_MASK,	M601,		{ RA, RS, RB } },
3690{ "sllq.",   XRC(31,216,1), X_MASK,	M601,		{ RA, RS, RB } },
3691
3692{ "sleq",    XRC(31,217,0), X_MASK,	M601,		{ RA, RS, RB } },
3693{ "sleq.",   XRC(31,217,1), X_MASK,	M601,		{ RA, RS, RB } },
3694
3695{ "stbxe",   X(31,223),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
3696
3697{ "icblc",   X(31,230),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
3698
3699{ "subfme",  XO(31,232,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3700{ "sfme",    XO(31,232,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3701{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3702{ "sfme.",   XO(31,232,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3703{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3704{ "sfmeo",   XO(31,232,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3705{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3706{ "sfmeo.",  XO(31,232,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3707
3708{ "mulld",   XO(31,233,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3709{ "mulld.",  XO(31,233,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3710{ "mulldo",  XO(31,233,1,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
3711{ "mulldo.", XO(31,233,1,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
3712
3713{ "addme",   XO(31,234,0,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3714{ "ame",     XO(31,234,0,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3715{ "addme.",  XO(31,234,0,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3716{ "ame.",    XO(31,234,0,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3717{ "addmeo",  XO(31,234,1,0), XORB_MASK, PPCCOM,		{ RT, RA } },
3718{ "ameo",    XO(31,234,1,0), XORB_MASK, PWRCOM,		{ RT, RA } },
3719{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM,		{ RT, RA } },
3720{ "ameo.",   XO(31,234,1,1), XORB_MASK, PWRCOM,		{ RT, RA } },
3721
3722{ "mullw",   XO(31,235,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3723{ "muls",    XO(31,235,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3724{ "mullw.",  XO(31,235,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3725{ "muls.",   XO(31,235,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3726{ "mullwo",  XO(31,235,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3727{ "mulso",   XO(31,235,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3728{ "mullwo.", XO(31,235,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3729{ "mulso.",  XO(31,235,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3730
3731{ "icblce",  X(31,238),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
3732{ "mtsrin",  X(31,242),	XRA_MASK,	PPC32,		{ RS, RB } },
3733{ "mtsri",   X(31,242),	XRA_MASK,	POWER32,	{ RS, RB } },
3734
3735{ "dcbtst",  X(31,246),	X_MASK,	PPC,			{ CT, RA, RB } },
3736
3737{ "stbux",   X(31,247),	X_MASK,		COM,		{ RS, RAS, RB } },
3738
3739{ "slliq",   XRC(31,248,0), X_MASK,	M601,		{ RA, RS, SH } },
3740{ "slliq.",  XRC(31,248,1), X_MASK,	M601,		{ RA, RS, SH } },
3741
3742{ "dcbtste", X(31,253),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3743
3744{ "stbuxe",  X(31,255),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
3745
3746{ "mfdcrx",  X(31,259),	X_MASK,		BOOKE,		{ RS, RA } },
3747
3748{ "doz",     XO(31,264,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3749{ "doz.",    XO(31,264,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3750{ "dozo",    XO(31,264,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3751{ "dozo.",   XO(31,264,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3752
3753{ "add",     XO(31,266,0,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3754{ "cax",     XO(31,266,0,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3755{ "add.",    XO(31,266,0,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3756{ "cax.",    XO(31,266,0,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3757{ "addo",    XO(31,266,1,0), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3758{ "caxo",    XO(31,266,1,0), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3759{ "addo.",   XO(31,266,1,1), XO_MASK,	PPCCOM,		{ RT, RA, RB } },
3760{ "caxo.",   XO(31,266,1,1), XO_MASK,	PWRCOM,		{ RT, RA, RB } },
3761
3762{ "tlbiel",  X(31,274), XRTLRA_MASK,	POWER4,		{ RB, L } },
3763
3764{ "mfapidi", X(31,275), X_MASK,		BOOKE,		{ RT, RA } },
3765
3766{ "lscbx",   XRC(31,277,0), X_MASK,	M601,		{ RT, RA, RB } },
3767{ "lscbx.",  XRC(31,277,1), X_MASK,	M601,		{ RT, RA, RB } },
3768
3769{ "dcbt",    X(31,278),	X_MASK,		PPC,		{ CT, RA, RB } },
3770
3771{ "lhzx",    X(31,279),	X_MASK,		COM,		{ RT, RA0, RB } },
3772
3773{ "eqv",     XRC(31,284,0), X_MASK,	COM,		{ RA, RS, RB } },
3774{ "eqv.",    XRC(31,284,1), X_MASK,	COM,		{ RA, RS, RB } },
3775
3776{ "dcbte",   X(31,286),	X_MASK,		BOOKE64,	{ CT, RA, RB } },
3777
3778{ "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
3779
3780{ "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
3781{ "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA0, RB } },
3782
3783{ "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
3784
3785{ "lhzux",   X(31,311),	X_MASK,		COM,		{ RT, RAL, RB } },
3786
3787{ "xor",     XRC(31,316,0), X_MASK,	COM,		{ RA, RS, RB } },
3788{ "xor.",    XRC(31,316,1), X_MASK,	COM,		{ RA, RS, RB } },
3789
3790{ "lhzuxe",  X(31,319),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
3791
3792{ "mfexisr",  XSPR(31,323,64),  XSPR_MASK, PPC403,	{ RT } },
3793{ "mfexier",  XSPR(31,323,66),  XSPR_MASK, PPC403,	{ RT } },
3794{ "mfbr0",    XSPR(31,323,128), XSPR_MASK, PPC403,	{ RT } },
3795{ "mfbr1",    XSPR(31,323,129), XSPR_MASK, PPC403,	{ RT } },
3796{ "mfbr2",    XSPR(31,323,130), XSPR_MASK, PPC403,	{ RT } },
3797{ "mfbr3",    XSPR(31,323,131), XSPR_MASK, PPC403,	{ RT } },
3798{ "mfbr4",    XSPR(31,323,132), XSPR_MASK, PPC403,	{ RT } },
3799{ "mfbr5",    XSPR(31,323,133), XSPR_MASK, PPC403,	{ RT } },
3800{ "mfbr6",    XSPR(31,323,134), XSPR_MASK, PPC403,	{ RT } },
3801{ "mfbr7",    XSPR(31,323,135), XSPR_MASK, PPC403,	{ RT } },
3802{ "mfbear",   XSPR(31,323,144), XSPR_MASK, PPC403,	{ RT } },
3803{ "mfbesr",   XSPR(31,323,145), XSPR_MASK, PPC403,	{ RT } },
3804{ "mfiocr",   XSPR(31,323,160), XSPR_MASK, PPC403,	{ RT } },
3805{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403,	{ RT } },
3806{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403,	{ RT } },
3807{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403,	{ RT } },
3808{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403,	{ RT } },
3809{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403,	{ RT } },
3810{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403,	{ RT } },
3811{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403,	{ RT } },
3812{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403,	{ RT } },
3813{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403,	{ RT } },
3814{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403,	{ RT } },
3815{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403,	{ RT } },
3816{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403,	{ RT } },
3817{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403,	{ RT } },
3818{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403,	{ RT } },
3819{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403,	{ RT } },
3820{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403,	{ RT } },
3821{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403,	{ RT } },
3822{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403,	{ RT } },
3823{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403,	{ RT } },
3824{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403,	{ RT } },
3825{ "mfdmasr",  XSPR(31,323,224), XSPR_MASK, PPC403,	{ RT } },
3826{ "mfdcr",    X(31,323),	X_MASK,	PPC403 | BOOKE,	{ RT, SPR } },
3827
3828{ "div",     XO(31,331,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
3829{ "div.",    XO(31,331,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
3830{ "divo",    XO(31,331,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
3831{ "divo.",   XO(31,331,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
3832
3833{ "mfpmr",   X(31,334),	X_MASK,		PPCPMR,		{ RT, PMR }},
3834
3835{ "mfmq",       XSPR(31,339,0),    XSPR_MASK, M601,	{ RT } },
3836{ "mfxer",      XSPR(31,339,1),    XSPR_MASK, COM,	{ RT } },
3837{ "mfrtcu",     XSPR(31,339,4),    XSPR_MASK, COM,	{ RT } },
3838{ "mfrtcl",     XSPR(31,339,5),    XSPR_MASK, COM,	{ RT } },
3839{ "mfdec",      XSPR(31,339,6),    XSPR_MASK, MFDEC1,	{ RT } },
3840{ "mfdec",      XSPR(31,339,22),   XSPR_MASK, MFDEC2,	{ RT } },
3841{ "mflr",       XSPR(31,339,8),    XSPR_MASK, COM,	{ RT } },
3842{ "mfctr",      XSPR(31,339,9),    XSPR_MASK, COM,	{ RT } },
3843{ "mftid",      XSPR(31,339,17),   XSPR_MASK, POWER,	{ RT } },
3844{ "mfdsisr",    XSPR(31,339,18),   XSPR_MASK, COM,	{ RT } },
3845{ "mfdar",      XSPR(31,339,19),   XSPR_MASK, COM,	{ RT } },
3846{ "mfsdr0",     XSPR(31,339,24),   XSPR_MASK, POWER,	{ RT } },
3847{ "mfsdr1",     XSPR(31,339,25),   XSPR_MASK, COM,	{ RT } },
3848{ "mfsrr0",     XSPR(31,339,26),   XSPR_MASK, COM,	{ RT } },
3849{ "mfsrr1",     XSPR(31,339,27),   XSPR_MASK, COM,	{ RT } },
3850{ "mfcfar",     XSPR(31,339,28),   XSPR_MASK, POWER6,	{ RT } },
3851{ "mfpid",      XSPR(31,339,48),   XSPR_MASK, BOOKE,    { RT } },
3852{ "mfpid",      XSPR(31,339,945),  XSPR_MASK, PPC403,	{ RT } },
3853{ "mfcsrr0",    XSPR(31,339,58),   XSPR_MASK, BOOKE,    { RT } },
3854{ "mfcsrr1",    XSPR(31,339,59),   XSPR_MASK, BOOKE,    { RT } },
3855{ "mfdear",     XSPR(31,339,61),   XSPR_MASK, BOOKE,    { RT } },
3856{ "mfdear",     XSPR(31,339,981),  XSPR_MASK, PPC403,	{ RT } },
3857{ "mfesr",      XSPR(31,339,62),   XSPR_MASK, BOOKE,    { RT } },
3858{ "mfesr",      XSPR(31,339,980),  XSPR_MASK, PPC403,	{ RT } },
3859{ "mfivpr",     XSPR(31,339,63),   XSPR_MASK, BOOKE,    { RT } },
3860{ "mfcmpa",     XSPR(31,339,144),  XSPR_MASK, PPC860,	{ RT } },
3861{ "mfcmpb",     XSPR(31,339,145),  XSPR_MASK, PPC860,	{ RT } },
3862{ "mfcmpc",     XSPR(31,339,146),  XSPR_MASK, PPC860,	{ RT } },
3863{ "mfcmpd",     XSPR(31,339,147),  XSPR_MASK, PPC860,	{ RT } },
3864{ "mficr",      XSPR(31,339,148),  XSPR_MASK, PPC860,	{ RT } },
3865{ "mfder",      XSPR(31,339,149),  XSPR_MASK, PPC860,	{ RT } },
3866{ "mfcounta",   XSPR(31,339,150),  XSPR_MASK, PPC860,	{ RT } },
3867{ "mfcountb",   XSPR(31,339,151),  XSPR_MASK, PPC860,	{ RT } },
3868{ "mfcmpe",     XSPR(31,339,152),  XSPR_MASK, PPC860,	{ RT } },
3869{ "mfcmpf",     XSPR(31,339,153),  XSPR_MASK, PPC860,	{ RT } },
3870{ "mfcmpg",     XSPR(31,339,154),  XSPR_MASK, PPC860,	{ RT } },
3871{ "mfcmph",     XSPR(31,339,155),  XSPR_MASK, PPC860,	{ RT } },
3872{ "mflctrl1",   XSPR(31,339,156),  XSPR_MASK, PPC860,	{ RT } },
3873{ "mflctrl2",   XSPR(31,339,157),  XSPR_MASK, PPC860,	{ RT } },
3874{ "mfictrl",    XSPR(31,339,158),  XSPR_MASK, PPC860,	{ RT } },
3875{ "mfbar",      XSPR(31,339,159),  XSPR_MASK, PPC860,	{ RT } },
3876{ "mfvrsave",   XSPR(31,339,256),  XSPR_MASK, PPCVEC,	{ RT } },
3877{ "mfusprg0",   XSPR(31,339,256),  XSPR_MASK, BOOKE,    { RT } },
3878{ "mftb",       X(31,371),	   X_MASK,    CLASSIC,	{ RT, TBR } },
3879{ "mftb",       XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3880{ "mftbl",      XSPR(31,371,268),  XSPR_MASK, CLASSIC,	{ RT } },
3881{ "mftbl",      XSPR(31,339,268),  XSPR_MASK, BOOKE,    { RT } },
3882{ "mftbu",      XSPR(31,371,269),  XSPR_MASK, CLASSIC,	{ RT } },
3883{ "mftbu",      XSPR(31,339,269),  XSPR_MASK, BOOKE,    { RT } },
3884{ "mfsprg",     XSPR(31,339,256),  XSPRG_MASK, PPC,	{ RT, SPRG } },
3885{ "mfsprg0",    XSPR(31,339,272),  XSPR_MASK, PPC,	{ RT } },
3886{ "mfsprg1",    XSPR(31,339,273),  XSPR_MASK, PPC,	{ RT } },
3887{ "mfsprg2",    XSPR(31,339,274),  XSPR_MASK, PPC,	{ RT } },
3888{ "mfsprg3",    XSPR(31,339,275),  XSPR_MASK, PPC,	{ RT } },
3889{ "mfsprg4",    XSPR(31,339,260),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3890{ "mfsprg5",    XSPR(31,339,261),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3891{ "mfsprg6",    XSPR(31,339,262),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3892{ "mfsprg7",    XSPR(31,339,263),  XSPR_MASK, PPC405 | BOOKE,	{ RT } },
3893{ "mfasr",      XSPR(31,339,280),  XSPR_MASK, PPC64,	{ RT } },
3894{ "mfear",      XSPR(31,339,282),  XSPR_MASK, PPC,	{ RT } },
3895{ "mfpir",      XSPR(31,339,286),  XSPR_MASK, BOOKE,    { RT } },
3896{ "mfpvr",      XSPR(31,339,287),  XSPR_MASK, PPC,	{ RT } },
3897{ "mfdbsr",     XSPR(31,339,304),  XSPR_MASK, BOOKE,    { RT } },
3898{ "mfdbsr",     XSPR(31,339,1008), XSPR_MASK, PPC403,	{ RT } },
3899{ "mfdbcr0",    XSPR(31,339,308),  XSPR_MASK, BOOKE,    { RT } },
3900{ "mfdbcr0",    XSPR(31,339,1010), XSPR_MASK, PPC405,	{ RT } },
3901{ "mfdbcr1",    XSPR(31,339,309),  XSPR_MASK, BOOKE,    { RT } },
3902{ "mfdbcr1",    XSPR(31,339,957),  XSPR_MASK, PPC405,	{ RT } },
3903{ "mfdbcr2",    XSPR(31,339,310),  XSPR_MASK, BOOKE,    { RT } },
3904{ "mfiac1",     XSPR(31,339,312),  XSPR_MASK, BOOKE,    { RT } },
3905{ "mfiac1",     XSPR(31,339,1012), XSPR_MASK, PPC403,	{ RT } },
3906{ "mfiac2",     XSPR(31,339,313),  XSPR_MASK, BOOKE,    { RT } },
3907{ "mfiac2",     XSPR(31,339,1013), XSPR_MASK, PPC403,	{ RT } },
3908{ "mfiac3",     XSPR(31,339,314),  XSPR_MASK, BOOKE,    { RT } },
3909{ "mfiac3",     XSPR(31,339,948),  XSPR_MASK, PPC405,	{ RT } },
3910{ "mfiac4",     XSPR(31,339,315),  XSPR_MASK, BOOKE,    { RT } },
3911{ "mfiac4",     XSPR(31,339,949),  XSPR_MASK, PPC405,	{ RT } },
3912{ "mfdac1",     XSPR(31,339,316),  XSPR_MASK, BOOKE,    { RT } },
3913{ "mfdac1",     XSPR(31,339,1014), XSPR_MASK, PPC403,	{ RT } },
3914{ "mfdac2",     XSPR(31,339,317),  XSPR_MASK, BOOKE,    { RT } },
3915{ "mfdac2",     XSPR(31,339,1015), XSPR_MASK, PPC403,	{ RT } },
3916{ "mfdvc1",     XSPR(31,339,318),  XSPR_MASK, BOOKE,    { RT } },
3917{ "mfdvc1",     XSPR(31,339,950),  XSPR_MASK, PPC405,	{ RT } },
3918{ "mfdvc2",     XSPR(31,339,319),  XSPR_MASK, BOOKE,    { RT } },
3919{ "mfdvc2",     XSPR(31,339,951),  XSPR_MASK, PPC405,	{ RT } },
3920{ "mftsr",      XSPR(31,339,336),  XSPR_MASK, BOOKE,    { RT } },
3921{ "mftsr",      XSPR(31,339,984),  XSPR_MASK, PPC403,	{ RT } },
3922{ "mftcr",      XSPR(31,339,340),  XSPR_MASK, BOOKE,    { RT } },
3923{ "mftcr",      XSPR(31,339,986),  XSPR_MASK, PPC403,	{ RT } },
3924{ "mfivor0",    XSPR(31,339,400),  XSPR_MASK, BOOKE,    { RT } },
3925{ "mfivor1",    XSPR(31,339,401),  XSPR_MASK, BOOKE,    { RT } },
3926{ "mfivor2",    XSPR(31,339,402),  XSPR_MASK, BOOKE,    { RT } },
3927{ "mfivor3",    XSPR(31,339,403),  XSPR_MASK, BOOKE,    { RT } },
3928{ "mfivor4",    XSPR(31,339,404),  XSPR_MASK, BOOKE,    { RT } },
3929{ "mfivor5",    XSPR(31,339,405),  XSPR_MASK, BOOKE,    { RT } },
3930{ "mfivor6",    XSPR(31,339,406),  XSPR_MASK, BOOKE,    { RT } },
3931{ "mfivor7",    XSPR(31,339,407),  XSPR_MASK, BOOKE,    { RT } },
3932{ "mfivor8",    XSPR(31,339,408),  XSPR_MASK, BOOKE,    { RT } },
3933{ "mfivor9",    XSPR(31,339,409),  XSPR_MASK, BOOKE,    { RT } },
3934{ "mfivor10",   XSPR(31,339,410),  XSPR_MASK, BOOKE,    { RT } },
3935{ "mfivor11",   XSPR(31,339,411),  XSPR_MASK, BOOKE,    { RT } },
3936{ "mfivor12",   XSPR(31,339,412),  XSPR_MASK, BOOKE,    { RT } },
3937{ "mfivor13",   XSPR(31,339,413),  XSPR_MASK, BOOKE,    { RT } },
3938{ "mfivor14",   XSPR(31,339,414),  XSPR_MASK, BOOKE,    { RT } },
3939{ "mfivor15",   XSPR(31,339,415),  XSPR_MASK, BOOKE,    { RT } },
3940{ "mfspefscr",  XSPR(31,339,512),  XSPR_MASK, PPCSPE,	{ RT } },
3941{ "mfbbear",    XSPR(31,339,513),  XSPR_MASK, PPCBRLK,  { RT } },
3942{ "mfbbtar",    XSPR(31,339,514),  XSPR_MASK, PPCBRLK,  { RT } },
3943{ "mfivor32",   XSPR(31,339,528),  XSPR_MASK, PPCSPE,	{ RT } },
3944{ "mfivor33",   XSPR(31,339,529),  XSPR_MASK, PPCSPE,	{ RT } },
3945{ "mfivor34",   XSPR(31,339,530),  XSPR_MASK, PPCSPE,	{ RT } },
3946{ "mfivor35",   XSPR(31,339,531),  XSPR_MASK, PPCPMR,	{ RT } },
3947{ "mfibatu",    XSPR(31,339,528),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3948{ "mfibatl",    XSPR(31,339,529),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3949{ "mfdbatu",    XSPR(31,339,536),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3950{ "mfdbatl",    XSPR(31,339,537),  XSPRBAT_MASK, PPC,	{ RT, SPRBAT } },
3951{ "mfic_cst",   XSPR(31,339,560),  XSPR_MASK, PPC860,	{ RT } },
3952{ "mfic_adr",   XSPR(31,339,561),  XSPR_MASK, PPC860,	{ RT } },
3953{ "mfic_dat",   XSPR(31,339,562),  XSPR_MASK, PPC860,	{ RT } },
3954{ "mfdc_cst",   XSPR(31,339,568),  XSPR_MASK, PPC860,	{ RT } },
3955{ "mfdc_adr",   XSPR(31,339,569),  XSPR_MASK, PPC860,	{ RT } },
3956{ "mfmcsrr0",   XSPR(31,339,570),  XSPR_MASK, PPCRFMCI, { RT } },
3957{ "mfdc_dat",   XSPR(31,339,570),  XSPR_MASK, PPC860,	{ RT } },
3958{ "mfmcsrr1",   XSPR(31,339,571),  XSPR_MASK, PPCRFMCI, { RT } },
3959{ "mfmcsr",     XSPR(31,339,572),  XSPR_MASK, PPCRFMCI, { RT } },
3960{ "mfmcar",     XSPR(31,339,573),  XSPR_MASK, PPCRFMCI, { RT } },
3961{ "mfdpdr",     XSPR(31,339,630),  XSPR_MASK, PPC860,	{ RT } },
3962{ "mfdpir",     XSPR(31,339,631),  XSPR_MASK, PPC860,	{ RT } },
3963{ "mfimmr",     XSPR(31,339,638),  XSPR_MASK, PPC860,	{ RT } },
3964{ "mfmi_ctr",   XSPR(31,339,784),  XSPR_MASK, PPC860,	{ RT } },
3965{ "mfmi_ap",    XSPR(31,339,786),  XSPR_MASK, PPC860,	{ RT } },
3966{ "mfmi_epn",   XSPR(31,339,787),  XSPR_MASK, PPC860,	{ RT } },
3967{ "mfmi_twc",   XSPR(31,339,789),  XSPR_MASK, PPC860,	{ RT } },
3968{ "mfmi_rpn",   XSPR(31,339,790),  XSPR_MASK, PPC860,	{ RT } },
3969{ "mfmd_ctr",   XSPR(31,339,792),  XSPR_MASK, PPC860,	{ RT } },
3970{ "mfm_casid",  XSPR(31,339,793),  XSPR_MASK, PPC860,	{ RT } },
3971{ "mfmd_ap",    XSPR(31,339,794),  XSPR_MASK, PPC860,	{ RT } },
3972{ "mfmd_epn",   XSPR(31,339,795),  XSPR_MASK, PPC860,	{ RT } },
3973{ "mfmd_twb",   XSPR(31,339,796),  XSPR_MASK, PPC860,	{ RT } },
3974{ "mfmd_twc",   XSPR(31,339,797),  XSPR_MASK, PPC860,	{ RT } },
3975{ "mfmd_rpn",   XSPR(31,339,798),  XSPR_MASK, PPC860,	{ RT } },
3976{ "mfm_tw",     XSPR(31,339,799),  XSPR_MASK, PPC860,	{ RT } },
3977{ "mfmi_dbcam", XSPR(31,339,816),  XSPR_MASK, PPC860,	{ RT } },
3978{ "mfmi_dbram0",XSPR(31,339,817),  XSPR_MASK, PPC860,	{ RT } },
3979{ "mfmi_dbram1",XSPR(31,339,818),  XSPR_MASK, PPC860,	{ RT } },
3980{ "mfmd_dbcam", XSPR(31,339,824),  XSPR_MASK, PPC860,	{ RT } },
3981{ "mfmd_dbram0",XSPR(31,339,825),  XSPR_MASK, PPC860,	{ RT } },
3982{ "mfmd_dbram1",XSPR(31,339,826),  XSPR_MASK, PPC860,	{ RT } },
3983{ "mfummcr0",   XSPR(31,339,936),  XSPR_MASK, PPC750,   { RT } },
3984{ "mfupmc1",    XSPR(31,339,937),  XSPR_MASK, PPC750,   { RT } },
3985{ "mfupmc2",    XSPR(31,339,938),  XSPR_MASK, PPC750,   { RT } },
3986{ "mfusia",     XSPR(31,339,939),  XSPR_MASK, PPC750,   { RT } },
3987{ "mfummcr1",   XSPR(31,339,940),  XSPR_MASK, PPC750,   { RT } },
3988{ "mfupmc3",    XSPR(31,339,941),  XSPR_MASK, PPC750,   { RT } },
3989{ "mfupmc4",    XSPR(31,339,942),  XSPR_MASK, PPC750,   { RT } },
3990{ "mfzpr",   	XSPR(31,339,944),  XSPR_MASK, PPC403,	{ RT } },
3991{ "mfccr0",  	XSPR(31,339,947),  XSPR_MASK, PPC405,	{ RT } },
3992{ "mfmmcr0",	XSPR(31,339,952),  XSPR_MASK, PPC750,	{ RT } },
3993{ "mfpmc1",	XSPR(31,339,953),  XSPR_MASK, PPC750,	{ RT } },
3994{ "mfsgr",	XSPR(31,339,953),  XSPR_MASK, PPC403,	{ RT } },
3995{ "mfpmc2",	XSPR(31,339,954),  XSPR_MASK, PPC750,	{ RT } },
3996{ "mfdcwr", 	XSPR(31,339,954),  XSPR_MASK, PPC403,	{ RT } },
3997{ "mfsia",	XSPR(31,339,955),  XSPR_MASK, PPC750,	{ RT } },
3998{ "mfsler",	XSPR(31,339,955),  XSPR_MASK, PPC405,	{ RT } },
3999{ "mfmmcr1",	XSPR(31,339,956),  XSPR_MASK, PPC750,	{ RT } },
4000{ "mfsu0r",	XSPR(31,339,956),  XSPR_MASK, PPC405,	{ RT } },
4001{ "mfpmc3",	XSPR(31,339,957),  XSPR_MASK, PPC750,	{ RT } },
4002{ "mfpmc4",	XSPR(31,339,958),  XSPR_MASK, PPC750,	{ RT } },
4003{ "mficdbdr",   XSPR(31,339,979),  XSPR_MASK, PPC403,   { RT } },
4004{ "mfevpr",     XSPR(31,339,982),  XSPR_MASK, PPC403,	{ RT } },
4005{ "mfcdbcr",    XSPR(31,339,983),  XSPR_MASK, PPC403,	{ RT } },
4006{ "mfpit",      XSPR(31,339,987),  XSPR_MASK, PPC403,	{ RT } },
4007{ "mftbhi",     XSPR(31,339,988),  XSPR_MASK, PPC403,	{ RT } },
4008{ "mftblo",     XSPR(31,339,989),  XSPR_MASK, PPC403,	{ RT } },
4009{ "mfsrr2",     XSPR(31,339,990),  XSPR_MASK, PPC403,	{ RT } },
4010{ "mfsrr3",     XSPR(31,339,991),  XSPR_MASK, PPC403,	{ RT } },
4011{ "mfl2cr",     XSPR(31,339,1017), XSPR_MASK, PPC750,   { RT } },
4012{ "mfdccr",     XSPR(31,339,1018), XSPR_MASK, PPC403,	{ RT } },
4013{ "mficcr",     XSPR(31,339,1019), XSPR_MASK, PPC403,	{ RT } },
4014{ "mfictc",     XSPR(31,339,1019), XSPR_MASK, PPC750,   { RT } },
4015{ "mfpbl1",     XSPR(31,339,1020), XSPR_MASK, PPC403,	{ RT } },
4016{ "mfthrm1",    XSPR(31,339,1020), XSPR_MASK, PPC750,   { RT } },
4017{ "mfpbu1",     XSPR(31,339,1021), XSPR_MASK, PPC403,	{ RT } },
4018{ "mfthrm2",    XSPR(31,339,1021), XSPR_MASK, PPC750,   { RT } },
4019{ "mfpbl2",     XSPR(31,339,1022), XSPR_MASK, PPC403,	{ RT } },
4020{ "mfthrm3",    XSPR(31,339,1022), XSPR_MASK, PPC750,   { RT } },
4021{ "mfpbu2",     XSPR(31,339,1023), XSPR_MASK, PPC403,	{ RT } },
4022{ "mfspr",      X(31,339),	   X_MASK,    COM,	{ RT, SPR } },
4023
4024{ "lwax",    X(31,341),	X_MASK,		PPC64,		{ RT, RA0, RB } },
4025
4026{ "dst",     XDSS(31,342,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
4027{ "dstt",    XDSS(31,342,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
4028
4029{ "lhax",    X(31,343),	X_MASK,		COM,		{ RT, RA0, RB } },
4030
4031{ "lhaxe",   X(31,351),	X_MASK,		BOOKE64,	{ RT, RA0, RB } },
4032
4033{ "dstst",   XDSS(31,374,0), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
4034{ "dststt",  XDSS(31,374,1), XDSS_MASK,	PPCVEC,		{ RA, RB, STRM } },
4035
4036{ "dccci",   X(31,454),	XRT_MASK,	PPC403|PPC440,	{ RA, RB } },
4037
4038{ "abs",     XO(31,360,0,0), XORB_MASK, M601,		{ RT, RA } },
4039{ "abs.",    XO(31,360,0,1), XORB_MASK, M601,		{ RT, RA } },
4040{ "abso",    XO(31,360,1,0), XORB_MASK, M601,		{ RT, RA } },
4041{ "abso.",   XO(31,360,1,1), XORB_MASK, M601,		{ RT, RA } },
4042
4043{ "divs",    XO(31,363,0,0), XO_MASK,	M601,		{ RT, RA, RB } },
4044{ "divs.",   XO(31,363,0,1), XO_MASK,	M601,		{ RT, RA, RB } },
4045{ "divso",   XO(31,363,1,0), XO_MASK,	M601,		{ RT, RA, RB } },
4046{ "divso.",  XO(31,363,1,1), XO_MASK,	M601,		{ RT, RA, RB } },
4047
4048{ "tlbia",   X(31,370),	0xffffffff,	PPC,		{ 0 } },
4049
4050{ "lwaux",   X(31,373),	X_MASK,		PPC64,		{ RT, RAL, RB } },
4051
4052{ "lhaux",   X(31,375),	X_MASK,		COM,		{ RT, RAL, RB } },
4053
4054{ "lhauxe",  X(31,383),	X_MASK,		BOOKE64,	{ RT, RAL, RB } },
4055
4056{ "mtdcrx",  X(31,387),	X_MASK,		BOOKE,		{ RA, RS } },
4057
4058{ "dcblc",   X(31,390),	X_MASK,		PPCCHLK,	{ CT, RA, RB }},
4059
4060{ "subfe64", XO(31,392,0,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
4061{ "subfe64o",XO(31,392,1,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
4062
4063{ "adde64",  XO(31,394,0,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
4064{ "adde64o", XO(31,394,1,0), XO_MASK,	BOOKE64,	{ RT, RA, RB } },
4065
4066{ "dcblce",  X(31,398),	X_MASK,		PPCCHLK64,	{ CT, RA, RB }},
4067
4068{ "slbmte",  X(31,402), XRA_MASK,	PPC64,		{ RS, RB } },
4069
4070{ "sthx",    X(31,407),	X_MASK,		COM,		{ RS, RA0, RB } },
4071
4072{ "cmpb",    X(31,508),	X_MASK,		POWER6,		{ RA, RS, RB } },
4073
4074{ "lfqx",    X(31,791),	X_MASK,		POWER2,		{ FRT, RA, RB } },
4075
4076{ "lfdpx",   X(31,791),	X_MASK,		POWER6,		{ FRT, RA, RB } },
4077
4078{ "lfqux",   X(31,823),	X_MASK,		POWER2,		{ FRT, RA, RB } },
4079
4080{ "stfqx",   X(31,919),	X_MASK,		POWER2,		{ FRS, RA, RB } },
4081
4082{ "stfdpx",  X(31,919),	X_MASK,		POWER6,		{ FRS, RA, RB } },
4083
4084{ "stfqux",  X(31,951),	X_MASK,		POWER2,		{ FRS, RA, RB } },
4085
4086{ "orc",     XRC(31,412,0), X_MASK,	COM,		{ RA, RS, RB } },
4087{ "orc.",    XRC(31,412,1), X_MASK,	COM,		{ RA, RS, RB } },
4088
4089{ "sradi",   XS(31,413,0), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
4090{ "sradi.",  XS(31,413,1), XS_MASK,	PPC64,		{ RA, RS, SH6 } },
4091
4092{ "sthxe",   X(31,415),	X_MASK,		BOOKE64,	{ RS, RA0, RB } },
4093
4094{ "slbie",   X(31,434),	XRTRA_MASK,	PPC64,		{ RB } },
4095
4096{ "ecowx",   X(31,438),	X_MASK,		PPC,		{ RT, RA, RB } },
4097
4098{ "sthux",   X(31,439),	X_MASK,		COM,		{ RS, RAS, RB } },
4099
4100{ "sthuxe",  X(31,447),	X_MASK,		BOOKE64,	{ RS, RAS, RB } },
4101
4102{ "cctpl",   0x7c210b78,    0xffffffff,	CELL,		{ 0 }},
4103{ "cctpm",   0x7c421378,    0xffffffff,	CELL,		{ 0 }},
4104{ "cctph",   0x7c631b78,    0xffffffff,	CELL,		{ 0 }},
4105{ "db8cyc",  0x7f9ce378,    0xffffffff,	CELL,		{ 0 }},
4106{ "db10cyc", 0x7fbdeb78,    0xffffffff,	CELL,		{ 0 }},
4107{ "db12cyc", 0x7fdef378,    0xffffffff,	CELL,		{ 0 }},
4108{ "db16cyc", 0x7ffffb78,    0xffffffff,	CELL,		{ 0 }},
4109{ "mr",	     XRC(31,444,0), X_MASK,	COM,		{ RA, RS, RBS } },
4110{ "or",      XRC(31,444,0), X_MASK,	COM,		{ RA, RS, RB } },
4111{ "mr.",     XRC(31,444,1), X_MASK,	COM,		{ RA, RS, RBS } },
4112{ "or.",     XRC(31,444,1), X_MASK,	COM,		{ RA, RS, RB } },
4113
4114{ "mtexisr",  XSPR(31,451,64),  XSPR_MASK, PPC403,	{ RS } },
4115{ "mtexier",  XSPR(31,451,66),  XSPR_MASK, PPC403,	{ RS } },
4116{ "mtbr0",    XSPR(31,451,128), XSPR_MASK, PPC403,	{ RS } },
4117{ "mtbr1",    XSPR(31,451,129), XSPR_MASK, PPC403,	{ RS } },
4118{ "mtbr2",    XSPR(31,451,130), XSPR_MASK, PPC403,	{ RS } },
4119{ "mtbr3",    XSPR(31,451,131), XSPR_MASK, PPC403,	{ RS } },
4120{ "mtbr4",    XSPR(31,451,132), XSPR_MASK, PPC403,	{ RS } },
4121{ "mtbr5",    XSPR(31,451,133), XSPR_MASK, PPC403,	{ RS } },
4122{ "mtbr6",    XSPR(31,451,134), XSPR_MASK, PPC403,	{ RS } },
4123{ "mtbr7",    XSPR(31,451,135), XSPR_MASK, PPC403,	{ RS } },
4124{ "mtbear",   XSPR(31,451,144), XSPR_MASK, PPC403,	{ RS } },
4125{ "mtbesr",   XSPR(31,451,145), XSPR_MASK, PPC403,	{ RS } },
4126{ "mtiocr",   XSPR(31,451,160), XSPR_MASK, PPC403,	{ RS } },
4127{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403,	{ RS } },
4128{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403,	{ RS } },
4129{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403,	{ RS } },
4130{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403,	{ RS } },
4131{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403,	{ RS } },
4132{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403,	{ RS } },
4133{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403,	{ RS } },
4134{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403,	{ RS } },
4135{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403,	{ RS } },
4136{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403,	{ RS } },
4137{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403,	{ RS } },
4138{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403,	{ RS } },
4139{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403,	{ RS } },
4140{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403,	{ RS } },
4141{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403,	{ RS } },
4142{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403,	{ RS } },
4143{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403,	{ RS } },
4144{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403,	{ RS } },
4145{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403,	{ RS } },
4146{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403,	{ RS } },
4147{ "mtdmasr",  XSPR(31,451,224), XSPR_MASK, PPC403,	{ RS } },
4148{ "mtdcr",    X(31,451),	X_MASK,	PPC403 | BOOKE,	{ SPR, RS } },
4149
4150{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4151{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4152
4153{ "divdu",   XO(31,457,0,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4154{ "divdu.",  XO(31,457,0,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4155{ "divduo",  XO(31,457,1,0), XO_MASK,	PPC64,		{ RT, RA, RB } },
4156{ "divduo.", XO(31,457,1,1), XO_MASK,	PPC64,		{ RT, RA, RB } },
4157
4158{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4159{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64,	{ RT, RA } },
4160
4161{ "divwu",   XO(31,459,0,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4162{ "divwu.",  XO(31,459,0,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4163{ "divwuo",  XO(31,459,1,0), XO_MASK,	PPC,		{ RT, RA, RB } },
4164{ "divwuo.", XO(31,459,1,1), XO_MASK,	PPC,		{ RT, RA, RB } },
4165
4166{ "mtmq",      XSPR(31,467,0),    XSPR_MASK, M601,	{ RS } },
4167{ "mtxer",     XSPR(31,467,1),    XSPR_MASK, COM,	{ RS } },
4168{ "mtlr",      XSPR(31,467,8),    XSPR_MASK, COM,	{ RS } },
4169{ "mtctr",     XSPR(31,467,9),    XSPR_MASK, COM,	{ RS } },
4170{ "mttid",     XSPR(31,467,17),   XSPR_MASK, POWER,	{ RS } },
4171{ "mtdsisr",   XSPR(31,467,18),   XSPR_MASK, COM,	{ RS } },
4172{ "mtdar",     XSPR(31,467,19),   XSPR_MASK, COM,	{ RS } },
4173{ "mtrtcu",    XSPR(31,467,20),   XSPR_MASK, COM,	{ RS } },
4174{ "mtrtcl",    XSPR(31,467,21),   XSPR_MASK, COM,	{ RS } },
4175{ "mtdec",     XSPR(31,467,22),   XSPR_MASK, COM,	{ RS } },
4176{ "mtsdr0",    XSPR(31,467,24),   XSPR_MASK, POWER,	{ RS } },
4177{ "mtsdr1",    XSPR(31,467,25),   XSPR_MASK, COM,	{ RS } },
4178{ "mtsrr0",    XSPR(31,467,26),   XSPR_MASK, COM,	{ RS } },
4179{ "mtsrr1",    XSPR(31,467,27),   XSPR_MASK, COM,	{ RS } },
4180{ "mtcfar",    XSPR(31,467,28),   XSPR_MASK, POWER6,	{ RS } },
4181{ "mtpid",     XSPR(31,467,48),   XSPR_MASK, BOOKE,     { RS } },
4182{ "mtpid",     XSPR(31,467,945),  XSPR_MASK, PPC403,	{ RS } },
4183{ "mtdecar",   XSPR(31,467,54),   XSPR_MASK, BOOKE,     { RS } },
4184{ "mtcsrr0",   XSPR(31,467,58),   XSPR_MASK, BOOKE,     { RS } },
4185{ "mtcsrr1",   XSPR(31,467,59),   XSPR_MASK, BOOKE,     { RS } },
4186{ "mtdear",    XSPR(31,467,61),   XSPR_MASK, BOOKE,     { RS } },
4187{ "mtdear",    XSPR(31,467,981),  XSPR_MASK, PPC403,	{ RS } },
4188{ "mtesr",     XSPR(31,467,62),   XSPR_MASK, BOOKE,     { RS } },
4189{ "mtesr",     XSPR(31,467,980),  XSPR_MASK, PPC403,	{ RS } },
4190{ "mtivpr",    XSPR(31,467,63),   XSPR_MASK, BOOKE,     { RS } },
4191{ "mtcmpa",    XSPR(31,467,144),  XSPR_MASK, PPC860,	{ RS } },
4192{ "mtcmpb",    XSPR(31,467,145),  XSPR_MASK, PPC860,	{ RS } },
4193{ "mtcmpc",    XSPR(31,467,146),  XSPR_MASK, PPC860,	{ RS } },
4194{ "mtcmpd",    XSPR(31,467,147),  XSPR_MASK, PPC860,	{ RS } },
4195{ "mticr",     XSPR(31,467,148),  XSPR_MASK, PPC860,	{ RS } },
4196{ "mtder",     XSPR(31,467,149),  XSPR_MASK, PPC860,	{ RS } },
4197{ "mtcounta",  XSPR(31,467,150),  XSPR_MASK, PPC860,	{ RS } },
4198{ "mtcountb",  XSPR(31,467,151),  XSPR_MASK, PPC860,	{ RS } },
4199{ "mtcmpe",    XSPR(31,467,152),  XSPR_MASK, PPC860,	{ RS } },
4200{ "mtcmpf",    XSPR(31,467,153),  XSPR_MASK, PPC860,	{ RS } },
4201{ "mtcmpg",    XSPR(31,467,154),  XSPR_MASK, PPC860,	{ RS } },
4202{ "mtcmph",    XSPR(31,467,155),  XSPR_MASK, PPC860,	{ RS } },
4203{ "mtlctrl1",  XSPR(31,467,156),  XSPR_MASK, PPC860,	{ RS } },
4204{ "mtlctrl2",  XSPR(31,467,157),  XSPR_MASK, PPC860,	{ RS } },
4205{ "mtictrl",   XSPR(31,467,158),  XSPR_MASK, PPC860,	{ RS } },
4206{ "mtbar",     XSPR(31,467,159),  XSPR_MASK, PPC860,	{ RS } },
4207{ "mtvrsave",  XSPR(31,467,256),  XSPR_MASK, PPCVEC,	{ RS } },
4208{ "mtusprg0",  XSPR(31,467,256),  XSPR_MASK, BOOKE,     { RS } },
4209{ "mtsprg",    XSPR(31,467,256),  XSPRG_MASK,PPC,	{ SPRG, RS } },
4210{ "mtsprg0",   XSPR(31,467,272),  XSPR_MASK, PPC,	{ RS } },
4211{ "mtsprg1",   XSPR(31,467,273),  XSPR_MASK, PPC,	{ RS } },
4212{ "mtsprg2",   XSPR(31,467,274),  XSPR_MASK, PPC,	{ RS } },
4213{ "mtsprg3",   XSPR(31,467,275),  XSPR_MASK, PPC,	{ RS } },
4214{ "mtsprg4",   XSPR(31,467,276),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4215{ "mtsprg5",   XSPR(31,467,277),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4216{ "mtsprg6",   XSPR(31,467,278),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4217{ "mtsprg7",   XSPR(31,467,279),  XSPR_MASK, PPC405 | BOOKE, { RS } },
4218{ "mtasr",     XSPR(31,467,280),  XSPR_MASK, PPC64,	{ RS } },
4219{ "mtear",     XSPR(31,467,282),  XSPR_MASK, PPC,	{ RS } },
4220{ "mttbl",     XSPR(31,467,284),  XSPR_MASK, PPC,	{ RS } },
4221{ "mttbu",     XSPR(31,467,285),  XSPR_MASK, PPC,	{ RS } },
4222{ "mtdbsr",    XSPR(31,467,304),  XSPR_MASK, BOOKE,     { RS } },
4223{ "mtdbsr",    XSPR(31,467,1008), XSPR_MASK, PPC403,	{ RS } },
4224{ "mtdbcr0",   XSPR(31,467,308),  XSPR_MASK, BOOKE,     { RS } },
4225{ "mtdbcr0",   XSPR(31,467,1010), XSPR_MASK, PPC405,	{ RS } },
4226{ "mtdbcr1",   XSPR(31,467,309),  XSPR_MASK, BOOKE,     { RS } },
4227{ "mtdbcr1",   XSPR(31,467,957),  XSPR_MASK, PPC405,	{ RS } },
4228{ "mtdbcr2",   XSPR(31,467,310),  XSPR_MASK, BOOKE,     { RS } },
4229{ "mtiac1",    XSPR(31,467,312),  XSPR_MASK, BOOKE,     { RS } },
4230{ "mtiac1",    XSPR(31,467,1012), XSPR_MASK, PPC403,	{ RS } },
4231{ "mtiac2",    XSPR(31,467,313),  XSPR_MASK, BOOKE,     { RS } },
4232{ "mtiac2",    XSPR(31,467,1013), XSPR_MASK, PPC403,	{ RS } },
4233{ "mtiac3",    XSPR(31,467,314),  XSPR_MASK, BOOKE,     { RS } },
4234{ "mtiac3",    XSPR(31,467,948),  XSPR_MASK, PPC405,	{ RS } },
4235{ "mtiac4",    XSPR(31,467,315),  XSPR_MASK, BOOKE,     { RS } },
4236{ "mtiac4",    XSPR(31,467,949),  XSPR_MASK, PPC405,	{ RS } },
4237{ "mtdac1",    XSPR(31,467,316),  XSPR_MASK, BOOKE,     { RS } },
4238{ "mtdac1",    XSPR(31,467,1014), XSPR_MASK, PPC403,	{ RS } },
4239{ "mtdac2",    XSPR(31,467,317),  XSPR_MASK, BOOKE,     { RS } },
4240{ "mtdac2",    XSPR(31,467,1015), XSPR_MASK, PPC403,	{ RS } },
4241{ "mtdvc1",    XSPR(31,467,318),  XSPR_MASK, BOOKE,     { RS } },
4242{ "mtdvc1",    XSPR(31,467,950),  XSPR_MASK, PPC405,	{ RS } },
4243{ "mtdvc2",    XSPR(31,467,319),  XSPR_MASK, BOOKE,     { RS } },
4244{ "mtdvc2",    XSPR(31,467,951),  XSPR_MASK, PPC405,	{ RS } },
4245{ "mttsr",     XSPR(31,467,336),  XSPR_MASK, BOOKE,     { RS } },
4246{ "mttsr",     XSPR(31,467,984),  XSPR_MASK, PPC403,	{ RS } },
4247{ "mttcr",     XSPR(31,467,340),  XSPR_MASK, BOOKE,     { RS } },
4248{ "mttcr",     XSPR(31,467,986),  XSPR_MASK, PPC403,	{ RS } },
4249{ "mtivor0",   XSPR(31,467,400),  XSPR_MASK, BOOKE,     { RS } },
4250{ "mtivor1",   XSPR(31,467,401),  XSPR_MASK, BOOKE,     { RS } },
4251{ "mtivor2",   XSPR(31,467,402),  XSPR_MASK, BOOKE,     { RS } },
4252{ "mtivor3",   XSPR(31,467,403),  XSPR_MASK, BOOKE,     { RS } },
4253{ "mtivor4",   XSPR(31,467,404),  XSPR_MASK, BOOKE,     { RS } },
4254{ "mtivor5",   XSPR(31,467,405),  XSPR_MASK, BOOKE,     { RS } },
4255{ "mtivor6",   XSPR(31,467,406),  XSPR_MASK, BOOKE,     { RS } },
4256{ "mtivor7",   XSPR(31,467,407),  XSPR_MASK, BOOKE,     { RS } },
4257{ "mtivor8",   XSPR(31,467,408),  XSPR_MASK, BOOKE,     { RS } },
4258{ "mtivor9",   XSPR(31,467,409),  XSPR_MASK, BOOKE,     { RS } },
4259{ "mtivor10",  XSPR(31,467,410),  XSPR_MASK, BOOKE,     { RS } },
4260{ "mtivor11",  XSPR(31,467,411),  XSPR_MASK, BOOKE,     { RS } },
4261{ "mtivor12",  XSPR(31,467,412),  XSPR_MASK, BOOKE,     { RS } },
4262{ "mtivor13",  XSPR(31,467,413),  XSPR_MASK, BOOKE,     { RS } },
4263{ "mtivor14",  XSPR(31,467,414),  XSPR_MASK, BOOKE,     { RS } },
4264{ "mtivor15",  XSPR(31,467,415),  XSPR_MASK, BOOKE,     { RS } },
4265{ "mtspefscr",  XSPR(31,467,512),  XSPR_MASK, PPCSPE,   { RS } },
4266{ "mtbbear",   XSPR(31,467,513),  XSPR_MASK, PPCBRLK,   { RS } },
4267{ "mtbbtar",   XSPR(31,467,514),  XSPR_MASK, PPCBRLK,  { RS } },
4268{ "mtivor32",  XSPR(31,467,528),  XSPR_MASK, PPCSPE,	{ RS } },
4269{ "mtivor33",  XSPR(31,467,529),  XSPR_MASK, PPCSPE,	{ RS } },
4270{ "mtivor34",  XSPR(31,467,530),  XSPR_MASK, PPCSPE,	{ RS } },
4271{ "mtivor35",  XSPR(31,467,531),  XSPR_MASK, PPCPMR,	{ RS } },
4272{ "mtibatu",   XSPR(31,467,528),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4273{ "mtibatl",   XSPR(31,467,529),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4274{ "mtdbatu",   XSPR(31,467,536),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4275{ "mtdbatl",   XSPR(31,467,537),  XSPRBAT_MASK, PPC,	{ SPRBAT, RS } },
4276{ "mtmcsrr0",  XSPR(31,467,570),  XSPR_MASK, PPCRFMCI,  { RS } },
4277{ "mtmcsrr1",  XSPR(31,467,571),  XSPR_MASK, PPCRFMCI,  { RS } },
4278{ "mtmcsr",    XSPR(31,467,572),  XSPR_MASK, PPCRFMCI,  { RS } },
4279{ "mtummcr0",  XSPR(31,467,936),  XSPR_MASK, PPC750,    { RS } },
4280{ "mtupmc1",   XSPR(31,467,937),  XSPR_MASK, PPC750,    { RS } },