Searched defs:mir (Results 1 - 25 of 28) sorted by relevance

12

/art/compiler/dex/
H A Dpost_opt_passes.cc59 MIR* mir = bb->first_mir_insn; local
61 while (mir != nullptr) {
62 MIR* next = mir->next;
64 Instruction::Code opcode = mir->dalvikInsn.opcode;
67 bb->RemoveMIR(mir);
70 mir = next;
H A Dlocal_value_numbering_test.cc138 MIR* mir = &mirs_[i]; local
139 mir->dalvikInsn.opcode = def->opcode;
140 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
141 mir->dalvikInsn.vB_wide = def->value;
144 mir->meta.ifield_lowering_info = def->field_info;
147 mir->meta.sfield_lowering_info = def->field_info;
149 mir->ssa_rep = &ssa_reps_[i];
150 mir->ssa_rep->num_uses = def->num_uses;
151 mir->ssa_rep->uses = const_cast<int32_t*>(def->uses); // Not modified by LVN.
152 mir
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H A Dmir_dataflow.cc927 MIR* mir; local
939 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
940 uint64_t df_attributes = GetDataFlowAttributes(mir);
941 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
980 HandleExtended(use_v, def_v, live_in_v, mir->dalvikInsn);
1017 void MIRGraph::AllocateSSAUseData(MIR *mir, int num_uses) { argument
1018 mir
1027 AllocateSSADefData(MIR *mir, int num_defs) argument
1039 DataFlowSSAFormat35C(MIR* mir) argument
1052 DataFlowSSAFormat3RC(MIR* mir) argument
1064 DataFlowSSAFormatExtended(MIR* mir) argument
1074 MIR* mir; local
1268 InvokeUsesMethodStar(MIR* mir) argument
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H A Dmir_optimization_test.cc162 MIR* mir = &mirs_[i]; local
163 mir->dalvikInsn.opcode = def->opcode;
166 bb->AppendMIR(mir);
169 mir->meta.sfield_lowering_info = def->field_or_method_info;
171 mir->ssa_rep = nullptr;
172 mir->offset = 2 * i; // All insns need to be at least 2 code units long.
173 mir->optimization_flags = 0u;
H A Dvreg_analysis.cc124 bool MIRGraph::InferTypeAndSize(BasicBlock* bb, MIR* mir, bool changed) { argument
125 SSARepresentation *ssa_rep = mir->ssa_rep;
137 uint64_t attrs = GetDataFlowAttributes(mir);
218 if ((mir->dalvikInsn.opcode == Instruction::RETURN) ||
219 (mir->dalvikInsn.opcode == Instruction::RETURN_WIDE) ||
220 (mir->dalvikInsn.opcode == Instruction::RETURN_OBJECT)) {
253 Instruction::Code opcode = mir->dalvikInsn.opcode;
255 0 : Instruction::FlagsOf(mir->dalvikInsn.opcode);
259 int target_idx = mir->dalvikInsn.vB;
263 MIR* move_result_mir = FindMoveResult(bb, mir);
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H A Dglobal_value_numbering_test.cc237 MIR* mir = &mirs_[i]; local
240 bb->AppendMIR(mir);
241 mir->dalvikInsn.opcode = def->opcode;
242 mir->dalvikInsn.vB = static_cast<int32_t>(def->value);
243 mir->dalvikInsn.vB_wide = def->value;
246 mir->meta.ifield_lowering_info = def->field_info;
249 mir->meta.sfield_lowering_info = def->field_info;
251 mir->meta.phi_incoming = static_cast<BasicBlockId*>(
254 mir->meta.phi_incoming[i] = bb->predecessors->Get(i);
257 mir
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H A Dmir_optimization.cc46 MIR* mir; local
48 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
50 if (mir->ssa_rep == nullptr) {
54 uint64_t df_attributes = GetDataFlowAttributes(mir);
56 MIR::DecodedInstruction* d_insn = &mir->dalvikInsn;
68 SetConstant(mir->ssa_rep->defs[0], vB);
71 SetConstant(mir
107 AdvanceMIR(BasicBlock** p_bb, MIR* mir) argument
131 FindMoveResult(BasicBlock* bb, MIR* mir) argument
186 SelectKind(MIR* mir) argument
678 MIR* mir = bb->last_mir_insn; local
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H A Dlocal_value_numbering.cc464 const MIR* mir = fall_through_bb->first_mir_insn; local
465 DCHECK(mir != nullptr);
467 if ((Instruction::FlagsOf(mir->dalvikInsn.opcode) & Instruction::kInvoke) != 0) {
468 for (uint16_t i = 0u; i != mir->ssa_rep->num_uses; ++i) {
469 uint16_t value_name = lvn->GetOperandValue(mir->ssa_rep->uses[i]);
933 uint16_t LocalValueNumbering::MarkNonAliasingNonNull(MIR* mir) { argument
934 uint16_t res = GetOperandValue(mir->ssa_rep->defs[0]);
975 void LocalValueNumbering::HandleNullCheck(MIR* mir, uint16_t reg) { argument
980 LOG(INFO) << "Removing null check for 0x" << std::hex << mir->offset;
982 mir
989 HandleRangeCheck(MIR* mir, uint16_t array, uint16_t index) argument
1005 HandlePutObject(MIR* mir) argument
1019 HandlePhi(MIR* mir) argument
1080 HandleAGet(MIR* mir, uint16_t opcode) argument
1105 HandleAPut(MIR* mir, uint16_t opcode) argument
1143 HandleIGet(MIR* mir, uint16_t opcode) argument
1178 HandleIPut(MIR* mir, uint16_t opcode) argument
1247 HandleSGet(MIR* mir, uint16_t opcode) argument
1282 HandleSPut(MIR* mir, uint16_t opcode) argument
1331 HandleInvokeOrClInit(MIR* mir) argument
1345 GetValueNumber(MIR* mir) argument
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H A Dmir_graph.cc656 // TODO: will need to snapshot stack image and use that as the mir context identification.
866 uint64_t MIRGraph::GetDataFlowAttributes(MIR* mir) { argument
867 DCHECK(mir != nullptr);
868 Instruction::Code opcode = mir->dalvikInsn.opcode;
911 const MIR* mir; local
914 for (mir = bb->first_mir_insn; mir; mir = mir->next) {
915 int opcode = mir
1030 AppendMIR(MIR* mir) argument
1082 PrependMIR(MIR* mir) argument
1093 MIR* mir = *it; local
1105 FindPreviousMIR(MIR* mir) argument
1151 RemoveMIR(MIR* mir) argument
1215 GetDalvikDisassembly(const MIR* mir) argument
1452 NewMemCallInfo(BasicBlock* bb, MIR* mir, InvokeType type, bool is_range) argument
1480 MIR* mir = new (arena_) MIR(); local
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/art/compiler/dex/quick/mips/
H A Dfp_mips.cc210 void MipsMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, argument
H A Dcall_mips.cc27 bool MipsMir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, argument
64 void MipsMir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
141 void MipsMir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
H A Dint_mips.cc230 void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { argument
234 void MipsMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { argument
/art/compiler/dex/quick/arm/
H A Dfp_arm.cc214 void ArmMir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
220 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
221 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
226 rl_src1 = mir_graph_->GetSrc(mir, 0);
227 rl_src2 = mir_graph_->GetSrc(mir, 1);
233 ConditionCode ccode = mir->meta.ccode;
H A Dcall_arm.cc46 void ArmMir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
94 void ArmMir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
H A Dint_arm.cc230 void ArmMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { argument
232 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
233 RegLocation rl_dest = mir_graph_->GetDest(mir);
238 ConditionCode ccode = mir->meta.ccode;
239 if (mir->ssa_rep->num_uses == 1) {
241 int true_val = mir->dalvikInsn.vB;
242 int false_val = mir->dalvikInsn.vC;
282 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]];
283 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]];
305 void ArmMir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { argument
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/art/compiler/dex/quick/arm64/
H A Dfp_arm64.cc201 void Arm64Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
207 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
208 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
213 rl_src1 = mir_graph_->GetSrc(mir, 0);
214 rl_src2 = mir_graph_->GetSrc(mir, 1);
219 ConditionCode ccode = mir->meta.ccode;
H A Dcall_arm64.cc46 void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
98 void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { argument
H A Dint_arm64.cc183 void Arm64Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
184 RegLocation rl_src = mir_graph_->GetSrc(mir, 0);
189 RegLocation rl_dest = mir_graph_->GetDest(mir);
192 if (mir->ssa_rep->num_uses == 1) {
194 GenSelect(mir->dalvikInsn.vB, mir->dalvikInsn.vC, mir->meta.ccode, rl_result.reg,
198 RegLocation rl_true = mir_graph_->reg_location_[mir->ssa_rep->uses[1]];
199 RegLocation rl_false = mir_graph_->reg_location_[mir->ssa_rep->uses[2]];
209 rl_true.reg.GetReg(), rl_false.reg.GetReg(), ArmConditionEncoding(mir
214 GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) argument
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/art/compiler/dex/quick/x86/
H A Dcall_x86.cc30 void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
63 void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { argument
H A Dfp_x86.cc493 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, argument
501 rl_src1 = mir_graph_->GetSrcWide(mir, 0);
502 rl_src2 = mir_graph_->GetSrcWide(mir, 2);
507 rl_src1 = mir_graph_->GetSrc(mir, 0);
508 rl_src2 = mir_graph_->GetSrc(mir, 1);
513 ConditionCode ccode = mir->meta.ccode;
H A Dutility_x86.cc928 for (MIR *mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
929 int opcode = mir->dalvikInsn.opcode;
931 AnalyzeExtendedMIR(opcode, bb, mir);
933 AnalyzeMIR(opcode, bb, mir);
939 void X86Mir2Lir::AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir) { argument
944 AnalyzeFPInstruction(opcode, bb, mir);
955 void X86Mir2Lir::AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir) { argument
991 AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir) argument
1053 AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir) argument
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/art/compiler/dex/quick/
H A Dmir_to_lir.cc228 bool Mir2Lir::GenSpecialIGet(MIR* mir, const InlineMethod& special) { argument
241 GenPrintLabel(mir);
268 bool Mir2Lir::GenSpecialIPut(MIR* mir, const InlineMethod& special) { argument
285 GenPrintLabel(mir);
303 bool Mir2Lir::GenSpecialIdentity(MIR* mir, const InlineMethod& special) { argument
308 GenPrintLabel(mir);
319 bool Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir, const InlineMethod& special) { argument
321 current_dalvik_offset_ = mir->offset;
328 DCHECK_EQ(mir->dalvikInsn.opcode, Instruction::RETURN_VOID);
329 return_mir = mir;
389 CompileDalvikInstruction(MIR* mir, BasicBlock* bb, LIR* label_list) argument
1064 HandleExtendedMethodMIR(BasicBlock* bb, MIR* mir) argument
1106 GenPrintLabel(MIR* mir) argument
1118 MIR* mir; local
1226 MIR* mir = bb->first_mir_insn; local
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H A Dcodegen_util.cc1311 void Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { argument
H A Dgen_common.cc531 void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, argument
533 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir);
567 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) {
620 void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, argument
622 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir);
652 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) {
722 void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, argument
725 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir);
769 void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, argument
772 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir);
2044 GenSmallPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) argument
2087 GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) argument
2102 GenSmallSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) argument
2117 GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) argument
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/art/compiler/dex/portable/
H A Dmir_to_gbc.cc329 void MirConverter::ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, argument
331 if (mir_graph_->GetBasicBlock(bb->taken)->start_offset <= mir->offset) {
345 MIR* mir, ConditionCode cc, RegLocation rl_src1) {
346 if (mir_graph_->GetBasicBlock(bb->taken)->start_offset <= mir->offset) {
467 void MirConverter::ConvertInvoke(BasicBlock* bb, MIR* mir, argument
469 CallInfo* info = mir_graph_->NewMemCallInfo(bb, mir, invoke_type, is_range);
703 bool MirConverter::ConvertMIRNode(MIR* mir, BasicBlock* bb, argument
708 Instruction::Code opcode = mir->dalvikInsn.opcode;
710 uint32_t vB = mir->dalvikInsn.vB;
711 uint32_t vC = mir
344 ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc, RegLocation rl_src1) argument
1598 ConvertExtendedMIR(BasicBlock* bb, MIR* mir, ::llvm::BasicBlock* llvm_bb) argument
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