Searched refs:CPU (Results 76 - 100 of 352) sorted by relevance

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/external/clang/include/clang/Basic/
H A DTargetOptions.h30 /// If given, the name of the target CPU to generate code for.
31 std::string CPU; member in class:clang::TargetOptions
/external/chromium_org/third_party/WebKit/Source/wtf/
H A DCPU.h34 /* CPU() - the target CPU architecture */
35 #define CPU(WTF_FEATURE) (defined WTF_CPU_##WTF_FEATURE && WTF_CPU_##WTF_FEATURE) macro
37 /* ==== CPU() - the target CPU architecture ==== */
39 /* This defines CPU(BIG_ENDIAN) or nothing, as appropriate. */
40 /* This defines CPU(32BIT) or CPU(64BIT), as appropriate. */
42 /* CPU(X86) - i386 / x86 32-bit */
51 /* CPU(X86_6
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/external/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.h56 HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS,
73 HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
78 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/external/llvm/lib/Target/Sparc/
H A DSparcSubtarget.h49 SparcSubtarget(const std::string &TT, const std::string &CPU,
72 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
73 SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
/external/llvm/lib/Target/SystemZ/
H A DSystemZSubtarget.h52 SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
55 SystemZSubtarget(const std::string &TT, const std::string &CPU,
71 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DSystemZTargetMachine.cpp23 StringRef CPU, StringRef FS,
27 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
28 Subtarget(TT, CPU, FS, *this) {
22 SystemZTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/llvm/lib/Target/XCore/
H A DXCoreTargetMachine.cpp24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS, *this) {
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
/external/lzma/CPP/
H A DBuild.mak3 !IFDEF CPU
11 !IFDEF CPU
12 O=$(CPU)
18 !IF "$(CPU)" == "AMD64"
20 !ELSEIF "$(CPU)" == "ARM"
40 !IF "$(CPU)" == "ARM"
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.h77 // The CPU string.
78 std::string CPU; member in class:llvm::LLVMDisasmContext
123 StringRef getCPU() const { return CPU; }
124 void setCPU(const char *CPU) { this->CPU = CPU; } argument
/external/llvm/lib/Target/Mips/
H A DMipsSubtarget.cpp61 /// Select the Mips CPU for the given triple and cpu name.
63 static StringRef selectMipsCPU(Triple TT, StringRef CPU) { argument
64 if (CPU.empty() || CPU == "generic") {
66 CPU = "mips32";
68 CPU = "mips64";
70 return CPU;
105 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument
108 : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
118 DL(computeDataLayout(initializeSubtargetDependencies(CPU, F
191 initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine *TM) argument
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H A DMipsTargetMachine.cpp54 StringRef CPU, StringRef FS,
58 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
59 Subtarget(TT, CPU, FS, isLittle, RM, this) {
67 StringRef CPU, StringRef FS, const TargetOptions &Options,
70 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
76 StringRef CPU, StringRef FS, const TargetOptions &Options,
79 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
53 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) argument
66 MipsebTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
75 MipselTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DMipsTargetMachine.h31 MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
78 StringRef CPU, StringRef FS, const TargetOptions &Options,
89 StringRef CPU, StringRef FS, const TargetOptions &Options,
/external/chromium_org/third_party/WebKit/Source/wtf/text/
H A DASCIIFastPath.h26 #include "wtf/CPU.h"
31 #if OS(MACOSX) && (CPU(X86) || CPU(X86_64))
87 // Compare the values of CPU word size.
107 #if OS(MACOSX) && (CPU(X86) || CPU(X86_64))
137 #elif COMPILER(GCC) && CPU(ARM_NEON) && !(CPU(BIG_ENDIAN) || CPU(MIDDLE_ENDIAN)) && defined(NDEBUG)
/external/llvm/lib/Target/ARM/
H A DARMTargetMachine.h29 StringRef CPU, StringRef FS,
73 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
84 StringRef CPU, StringRef FS, const TargetOptions &Options,
94 ARMBETargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
106 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
116 ThumbLETargetMachine(const Target &T, StringRef TT, StringRef CPU,
127 ThumbBETargetMachine(const Target &T, StringRef TT, StringRef CPU,
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetMachine.cpp70 StringRef CPU, StringRef FS,
74 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
75 Subtarget(TT, CPU, FS, *this, is64bit) {
82 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
85 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
90 const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
69 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) argument
81 NVPTXTargetMachine32( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
89 NVPTXTargetMachine64( const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DNVPTXSubtarget.h57 NVPTXSubtarget(const std::string &TT, const std::string &CPU,
105 NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
106 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
H A DNVPTXTargetMachine.h34 NVPTXTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
83 NVPTXTargetMachine32(const Target &T, StringRef TT, StringRef CPU,
92 NVPTXTargetMachine64(const Target &T, StringRef TT, StringRef CPU,
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetMachine.cpp40 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU, argument
44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45 Subtarget(TT, CPU, FS, *this, is64Bit, OL) {
52 StringRef CPU, StringRef FS,
56 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
62 StringRef CPU, StringRef FS,
66 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
51 PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
61 PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
H A DPPCTargetMachine.h31 StringRef CPU, StringRef FS, const TargetOptions &Options,
75 StringRef CPU, StringRef FS, const TargetOptions &Options,
86 StringRef CPU, StringRef FS, const TargetOptions &Options,
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp76 const StringRef CPU; member in class:__anon26169::X86AsmBackend
81 : MCAsmBackend(), CPU(_CPU), MaxNopLength(_CPU == "slm" ? 7 : 15) {
82 HasNopl = CPU != "generic" && CPU != "i386" && CPU != "i486" &&
83 CPU != "i586" && CPU != "pentium" && CPU != "pentium-mmx" &&
84 CPU != "i686" && CPU !
355 ELFX86AsmBackend(const Target &T, uint8_t _OSABI, StringRef CPU) argument
361 ELFX86_32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) argument
371 ELFX86_X32AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) argument
382 ELFX86_64AsmBackend(const Target &T, uint8_t OSABI, StringRef CPU) argument
394 WindowsX86AsmBackend(const Target &T, bool is64Bit, StringRef CPU) argument
720 DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, bool Is64Bit) argument
733 DarwinX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU) argument
753 DarwinX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef CPU, MachO::CPUSubTypeX86 st) argument
804 createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
820 createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, StringRef TT, StringRef CPU) argument
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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCTargetDesc.cpp44 /// Select the Mips CPU for the given triple and cpu name.
46 static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { argument
47 if (CPU.empty() || CPU == "generic") {
51 CPU = "mips32";
53 CPU = "mips64";
55 return CPU;
70 static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, argument
72 CPU = selectMipsCPU(TT, CPU);
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/external/qemu/android/build/
H A Dcommon.sh59 ## Normalize OS and CPU
62 CPU=`uname -m`
63 case "$CPU" in
64 i?86) CPU=x86
66 amd64) CPU=x86_64
68 powerpc) CPU=ppc
72 log2 "CPU=$CPU"
74 # at this point, the supported values for CPU are:
86 OS=darwin-$CPU
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/external/chromium_org/third_party/WebKit/Source/platform/audio/
H A DVectorMath.cpp31 #include "wtf/CPU.h"
38 #if CPU(X86) || CPU(X86_64)
60 #if CPU(X86)
69 #if CPU(X86)
78 #if CPU(X86)
96 #if CPU(X86)
128 #if CPU(X86) || CPU(X86_64)
201 #if CPU(X8
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/external/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.cpp45 const std::string &CPU,
48 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
50 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), CPUString(CPU),
44 AArch64Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool LittleEndian) argument
H A DAArch64TargetMachine.h29 AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU,
68 AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU,
79 AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU,

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