/external/mesa3d/src/gallium/drivers/nv50/ |
H A D | nv50_transfer.c | 24 rect->bo = mt->base.bo; 69 nouveau_bufctx_refn(bctx, 0, src->bo, src->domain | NOUVEAU_BO_RD); 70 nouveau_bufctx_refn(bctx, 0, dst->bo, dst->domain | NOUVEAU_BO_WR); 74 if (nouveau_bo_memtype(src->bo)) { 91 if (nouveau_bo_memtype(dst->bo)) { 112 PUSH_DATAh(push, src->bo->offset + src_ofst); 113 PUSH_DATAh(push, dst->bo->offset + dst_ofst); 116 PUSH_DATA (push, src->bo->offset + src_ofst); 117 PUSH_DATA (push, dst->bo 384 nv50_cb_push(struct nouveau_context *nv, struct nouveau_bo *bo, unsigned domain, unsigned base, unsigned size, unsigned offset, unsigned words, const uint32_t *data) argument [all...] |
H A D | nv50_transfer.h | 8 struct nouveau_bo *bo; member in struct:nv50_m2mf_rect
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H A D | nv50_vbo.c | 204 struct nouveau_bo *bo; local 214 &bo); 217 NOUVEAU_BO_RD, bo); 246 struct nouveau_bo *bo; local 250 base, size, &bo); 252 BCTX_REFN_bo(nv50->bufctx_3d, VERTEX_TMP, bo_flags, bo); 598 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4); 607 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 619 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes);
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H A D | nv50_winsys.h | 21 unsigned flags, struct nouveau_bo *bo) 23 nouveau_bufctx_refn(bufctx, bin, bo, flags)->priv = NULL; 31 nouveau_bufctx_refn(bufctx, bin, res->bo, flags | res->domain); 36 #define BCTX_REFN_bo(ctx, bin, fl, bo) \ 37 nv50_add_bufctx_resident_bo(ctx, NV50_BIND_##bin, fl, bo); 43 PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) argument 45 struct nouveau_pushbuf_refn ref = { bo, flags }; 84 nouveau_bo_memtype(const struct nouveau_bo *bo) argument 86 return bo->config.nv50.memtype; 20 nv50_add_bufctx_resident_bo(struct nouveau_bufctx *bufctx, int bin, unsigned flags, struct nouveau_bo *bo) argument
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/external/mesa3d/src/gallium/drivers/nvc0/ |
H A D | nvc0_query.c | 40 struct nouveau_bo *bo; member in struct:nvc0_query 64 if (q->bo) { 65 nouveau_bo_ref(NULL, &q->bo); 75 q->mm = nouveau_mm_allocate(screen->base.mm_GART, size, &q->bo, &q->base); 76 if (!q->bo) 80 ret = nouveau_bo_map(q->bo, 0, screen->base.client); 85 q->data = (uint32_t *)((uint8_t *)q->bo->map + q->base); 163 PUSH_REFN (push, q->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR); 165 PUSH_DATAh(push, q->bo->offset + offset); 166 PUSH_DATA (push, q->bo [all...] |
H A D | nvc0_screen.h | 57 struct nouveau_bo *bo; member in struct:nvc0_screen::__anon27269 97 if (likely(res->bo)) {
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H A D | nvc0_state_validate.c | 13 struct nouveau_bo *bo = mt->base.bo; local 32 PUSH_DATAh(push, bo->offset + offset); 33 PUSH_DATA (push, bo->offset + offset); 36 PUSH_DATAh(push, bo->offset + offset); 37 PUSH_DATA (push, bo->offset + offset); 75 struct nouveau_bo *bo = res->bo; local 80 if (likely(nouveau_bo_memtype(bo))) { 256 struct nouveau_bo *bo local 366 struct nouveau_bo *bo = nvc0->screen->uniform_bo; local [all...] |
H A D | nvc0_surface.c | 80 struct nouveau_bo *bo = mt->base.bo; local 109 if (nouveau_bo_memtype(bo)) { 117 PUSH_DATAh(push, bo->offset + offset); 118 PUSH_DATA (push, bo->offset + offset); 129 PUSH_DATAh(push, bo->offset + offset); 130 PUSH_DATA (push, bo->offset + offset); 302 if (likely(nouveau_bo_memtype(res->bo))) {
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H A D | nvc0_transfer.c | 34 nouveau_bufctx_refn(bctx, 0, src->bo, src->domain | NOUVEAU_BO_RD); 35 nouveau_bufctx_refn(bctx, 0, dst->bo, dst->domain | NOUVEAU_BO_WR); 39 if (nouveau_bo_memtype(src->bo)) { 55 if (nouveau_bo_memtype(dst->bo)) { 75 PUSH_DATAh(push, src->bo->offset + src_ofst); 76 PUSH_DATA (push, src->bo->offset + src_ofst); 79 PUSH_DATAh(push, dst->bo->offset + dst_ofst); 80 PUSH_DATA (push, dst->bo->offset + dst_ofst); 126 nouveau_bufctx_refn(bctx, 0, dst->bo, dst->domain | NOUVEAU_BO_WR); 127 nouveau_bufctx_refn(bctx, 0, src->bo, sr 464 nvc0_cb_push(struct nouveau_context *nv, struct nouveau_bo *bo, unsigned domain, unsigned base, unsigned size, unsigned offset, unsigned words, const uint32_t *data) argument [all...] |
H A D | nvc0_vbo.c | 249 struct nouveau_bo *bo; local 253 base, size, &bo); 254 if (bo) 255 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo); 276 struct nouveau_bo *bo; local 286 base, size, &bo); 287 if (bo) 288 BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo);
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H A D | nvc0_vbo_translate.c | 184 struct nouveau_bo *bo; local 188 void *const dest = nouveau_scratch_get(&nvc0->base, size, &va, &bo); 198 bo); 571 struct nouveau_bo *bo; local 582 info->count * index_size, &va, &bo); 585 bo);
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H A D | nvc0_winsys.h | 20 unsigned flags, struct nouveau_bo *bo) 22 nouveau_bufctx_refn(bufctx, bin, bo, flags)->priv = NULL; 30 nouveau_bufctx_refn(bufctx, bin, res->bo, flags | res->domain); 35 #define BCTX_REFN_bo(ctx, bin, fl, bo) \ 36 nv50_add_bufctx_resident_bo(ctx, NVC0_BIND_##bin, fl, bo); 42 PUSH_REFN(struct nouveau_pushbuf *push, struct nouveau_bo *bo, uint32_t flags) argument 44 struct nouveau_pushbuf_refn ref = { bo, flags }; 94 nouveau_bo_memtype(const struct nouveau_bo *bo) argument 96 return bo->config.nvc0.memtype; 19 nv50_add_bufctx_resident_bo(struct nouveau_bufctx *bufctx, int bin, unsigned flags, struct nouveau_bo *bo) argument
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | compute_memory_pool.h | 38 int64_t start_in_dw; ///Start pointer in dwords relative in the pool bo 52 struct r600_resource *bo; ///The pool buffer object resource member in struct:compute_memory_pool
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H A D | evergreen_compute_internal.c | 116 res->bo = NULL; 213 struct r600_resource *bo, 216 assert(bo); 219 u32 rr = r600_context_bo_reloc(ctx, bo, usage); 225 struct r600_resource *bo) 227 switch (bo->b.b.format) 259 struct r600_resource* bo, 286 (struct pipe_resource *)bo, &rat_templ); 339 struct r600_resource* bo, 352 res->bo 211 evergreen_emit_ctx_reloc( struct r600_context *ctx, struct r600_resource *bo, enum radeon_bo_usage usage) argument 223 evergreen_compute_get_gpu_format( struct number_type_and_format* fmt, struct r600_resource *bo) argument 256 evergreen_set_rat( struct r600_pipe_compute *pipe, int id, struct r600_resource* bo, int start, int size) argument 337 evergreen_set_export( struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size) argument 377 evergreen_set_tmp_ring( struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size, int se) argument [all...] |
H A D | evergreen_compute_internal.h | 53 struct r600_resource *bo; member in struct:evergreen_compute_resource 87 int evergreen_compute_get_gpu_format(struct number_type_and_format* fmt, struct r600_resource *bo); ///get hw format from resource, return 0 on faliure, nonzero on success 95 void evergreen_emit_ctx_reloc(struct r600_context *ctx, struct r600_resource *bo, enum radeon_bo_usage usage); 104 void evergreen_set_rat(struct r600_pipe_compute *pipe, int id, struct r600_resource* bo, int start, int size); 106 void evergreen_set_export(struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size); 108 void evergreen_set_tmp_ring(struct r600_pipe_compute *pipe, struct r600_resource* bo, int offset, int size, int se);
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H A D | r600.h | 109 struct r600_resource *bo; member in struct:r600_pipe_reg 124 struct r600_resource *bo; member in struct:r600_block_reloc 215 struct r600_resource *bo, 225 struct r600_resource *bo, 228 #define r600_pipe_state_add_reg_bo(state, offset, value, bo, usage) _r600_pipe_state_add_reg_bo(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage)
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H A D | r600_pipe.h | 147 struct r600_resource *bo; member in struct:r600_pipe_fences 240 struct r600_resource *bo; member in struct:r600_pipe_shader 286 unsigned index; /* in the shared bo */
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H A D | r600_state_common.c | 466 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 828 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->ps_shader->current->bo); 856 r600_context_add_resource_size(ctx, (struct pipe_resource *)rctx->vs_shader->current->bo); 1377 struct r600_resource *bo, 1384 if (bo) assert(usage); 1392 state->regs[state->nregs].bo = bo; 1410 struct r600_resource *bo, 1413 if (bo) assert(usage); 1418 state->regs[state->nregs].bo 1373 _r600_pipe_state_add_reg_bo(struct r600_context *ctx, struct r600_pipe_state *state, uint32_t offset, uint32_t value, uint32_t range_id, uint32_t block_id, struct r600_resource *bo, enum radeon_bo_usage usage) argument 1408 r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, uint32_t offset, uint32_t value, struct r600_resource *bo, enum radeon_bo_usage usage) argument [all...] |
/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | radeonsi_pipe.h | 54 struct si_resource *bo; member in struct:r600_pipe_fences 98 unsigned index; /* in the shared bo */
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H A D | radeonsi_pm4.c | 89 struct si_resource *bo, 95 si_resource_reference(&state->bo[idx], bo); 169 si_resource_reference(&state->bo[i], NULL); 209 r600_context_bo_reloc(rctx, state->bo[i], 88 si_pm4_add_bo(struct si_pm4_state *state, struct si_resource *bo, enum radeon_bo_usage usage) argument
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H A D | radeonsi_pm4.h | 55 struct si_resource *bo[SI_PM4_MAX_BO]; member in struct:si_pm4_state 69 struct si_resource *bo,
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H A D | radeonsi_shader.h | 76 struct si_resource *bo; member in struct:si_pipe_shader
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/external/mesa3d/src/gallium/state_trackers/egl/drm/ |
H A D | native_drm.c | 254 struct gbm_gallium_drm_bo *bo = (void *) pix; local 256 return drm_display_create_surface_from_resource(ndpy, bo->resource);
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/external/mesa3d/src/gallium/state_trackers/gbm/ |
H A D | gbm_drm.c | 100 struct gbm_gallium_drm_bo *bo = gbm_gallium_drm_bo(_bo); local 102 pipe_resource_reference(&bo->resource, NULL); 103 free(bo); 111 struct gbm_gallium_drm_bo *bo; local 139 bo = CALLOC_STRUCT(gbm_gallium_drm_bo); 140 if (bo == NULL) 143 bo->base.base.gbm = gbm; 144 bo->base.base.width = resource->width0; 145 bo->base.base.height = resource->height0; 149 bo 177 struct gbm_gallium_drm_bo *bo; local [all...] |
H A D | gbm_gallium_drmint.h | 63 gbm_gallium_drm_bo(struct gbm_bo *bo) argument 65 return (struct gbm_gallium_drm_bo *) bo;
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