/external/chromium_org/v8/src/x64/ |
H A D | disasm-x64.cc | 379 int* rm) { 382 *rm = (data & 7) | (rex_b() ? 8 : 0); 442 int mod, regop, rm; local 443 get_modrm(*modrmp, &mod, ®op, &rm); 448 if ((rm & 7) == 5) { 452 } else if ((rm & 7) == 4) { 483 AppendToBuffer("[%s]", NameOfCPURegister(rm)); 489 if ((rm & 7) == 4) { 514 NameOfCPURegister(rm), 521 AppendToBuffer("%s", (this->*register_name)(rm)); 376 get_modrm(byte data, int* mod, int* regop, int* rm) argument 585 int mod, regop, rm; local 621 int mod, regop, rm; local 666 int mod, regop, rm; local 717 int mod, regop, rm; local 1007 int mod, regop, rm; local 1102 int mod, regop, rm; local 1113 int mod, regop, rm; local 1120 int mod, regop, rm; local 1127 int mod, regop, rm; local 1134 int mod, regop, rm; local 1140 int mod, regop, rm; local 1165 int mod, regop, rm; local 1176 int mod, regop, rm; local 1183 int mod, regop, rm; local 1191 int mod, regop, rm; local 1196 int mod, regop, rm; local 1205 int mod, regop, rm; local 1220 int mod, regop, rm; local 1227 int mod, regop, rm; local 1260 int mod, regop, rm; local 1269 int mod, regop, rm; local 1278 int mod, regop, rm; local 1299 int mod, regop, rm; local 1309 int mod, regop, rm; local 1492 int mod, regop, rm; local 1515 int mod, regop, rm; local 1526 int mod, regop, rm; local 1596 int mod, regop, rm; local 1665 int mod, regop, rm; local [all...] |
/external/icu/icu4c/source/tools/gennorm2/ |
H A D | n2builder.cpp | 709 UnicodeString &rm=*p->rawMapping; local 710 int32_t rmLength=rm.length(); 718 UChar rm0=rm.charAt(0); 721 0==rm.compare(1, 99, m, 2, 99) && 735 dataString.append(rm);
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/external/pixman/test/ |
H A D | utils.c | 1404 checker->rm = ((1 << PIXMAN_FORMAT_R (format)) - 1) << checker->rs; 1419 *r = (pixel & checker->rm) >> checker->rs; 1427 uint32_t *rm, 1433 if (rm) 1434 *rm = checker->rm; 1454 if (checker->rm == 0) 1457 color->r = r / (double)(checker->rm >> checker->rs); 1509 *ro = convert (color->r + limit, checker->rw, checker->rm, checker->rs, 0.0); 1520 int *am, int *rm, in 1425 pixel_checker_get_masks(const pixel_checker_t *checker, uint32_t *am, uint32_t *rm, uint32_t *gm, uint32_t *bm) argument 1519 pixel_checker_get_max(const pixel_checker_t *checker, color_t *color, int *am, int *rm, int *gm, int *bm) argument 1526 pixel_checker_get_min(const pixel_checker_t *checker, color_t *color, int *am, int *rm, int *gm, int *bm) argument [all...] |
/external/qemu/disas/ |
H A D | arm.c | 2074 const char *rm = arm_regnames [given & 0xf]; local 2082 func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); 2094 func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); 2289 int rm = ((given >> 0) & 0xf); local 2308 if (rm == 0xd) 2310 else if (rm != 0xf) 2311 func (stream, ", %s", arm_regnames[rm]); 2319 int rm = ((given >> 0) & 0xf); local 2383 if (rm == 0xd) 2385 else if (rm ! 2394 int rm = ((given >> 0) & 0xf); local [all...] |
/external/qemu/target-arm/ |
H A D | neon_helper.c | 1834 void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1836 uint64_t zm0 = float64_val(env->vfp.regs[rm]); 1837 uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); 1856 env->vfp.regs[rm] = make_float64(m0); 1857 env->vfp.regs[rm + 1] = make_float64(m1); 1862 void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1864 uint64_t zm0 = float64_val(env->vfp.regs[rm]); 1865 uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); 1876 env->vfp.regs[rm] = make_float64(m0); 1877 env->vfp.regs[rm 1882 neon_qunzip32(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1898 neon_unzip8(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1914 neon_unzip16(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1926 neon_qzip8(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1954 neon_qzip16(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1974 neon_qzip32(CPUARMState *env, uint32_t rd, uint32_t rm) argument 1990 neon_zip8(CPUARMState *env, uint32_t rd, uint32_t rm) argument 2006 neon_zip16(CPUARMState *env, uint32_t rd, uint32_t rm) argument [all...] |
/external/valgrind/main/VEX/priv/ |
H A D | host_s390_isel.c | 2077 s390_dfp_round_t rm; local 2098 rm = get_dfp_rounding_mode(env, irrm); 2102 f4, INVALID_HREG, r1, rm)); 2115 s390_dfp_round_t rm; local 2127 rm = get_dfp_rounding_mode(env, irrm); 2133 f4, f6, r1, rm)); 2416 s390_dfp_round_t rm; local 2424 rm = get_dfp_rounding_mode(env, irrm); 2427 addInstr(env, s390_insn_fp_convert(size, fpconv, f0, f4, r1, rm)); 2434 s390_dfp_round_t rm; local 2791 s390_dfp_round_t rm; local 2829 s390_dfp_round_t rm; local 3016 s390_dfp_round_t rm; local 3034 s390_dfp_round_t rm; local [all...] |
H A D | host_amd64_isel.c | 2157 AMD64RM* rm = iselIntExpr_RM_wrk(env, e); local 2159 switch (rm->tag) { 2161 vassert(hregClass(rm->Arm.Reg.reg) == HRcInt64); 2162 vassert(hregIsVirtual(rm->Arm.Reg.reg)); 2163 return rm; 2165 vassert(sane_AMode(rm->Arm.Mem.am)); 2166 return rm;
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H A D | host_x86_isel.c | 1736 X86RM* rm = iselIntExpr_RM_wrk(env, e); local 1738 switch (rm->tag) { 1740 vassert(hregClass(rm->Xrm.Reg.reg) == HRcInt32); 1741 vassert(hregIsVirtual(rm->Xrm.Reg.reg)); 1742 return rm; 1744 vassert(sane_AMode(rm->Xrm.Mem.am)); 1745 return rm; 1823 X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg); local 1824 addInstr(env, X86Instr_Test32(1,rm)); 1833 X86RM* rm local 1843 X86RM* rm = iselIntExpr_RM(env, e->Iex.Unop.arg); local [all...] |
/external/valgrind/main/none/tests/amd64/ |
H A D | sse4-64.c | 2445 UInt rm; local 2472 rm = get_sse_roundingmode(); 2473 assert(rm == 0); // 0 == RN == default 2478 for (rm = 0; rm <= 3; rm++) { 2479 set_sse_roundingmode(rm); 2485 printf("r (rm=%u) roundsd_1XX ", rm); 2496 printf("m (rm 2761 UInt rm; local 3092 UInt rm; local 3459 UInt rm; local [all...] |
/external/vixl/src/a64/ |
H A D | macro-assembler-a64.h | 354 void Asr(const Register& rd, const Register& rn, const Register& rm) { argument 358 VIXL_ASSERT(!rm.IsZero()); 359 asrv(rd, rn, rm); 481 const Register& rm, 486 VIXL_ASSERT(!rm.IsZero()); 488 csinc(rd, rn, rm, cond); 492 const Register& rm, 497 VIXL_ASSERT(!rm.IsZero()); 499 csinv(rd, rn, rm, cond); 503 const Register& rm, 479 Csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 490 Csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 501 Csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 520 Extr(const Register& rd, const Register& rn, const Register& rm, unsigned lsb) argument 778 Lsl(const Register& rd, const Register& rn, const Register& rm) argument 791 Lsr(const Register& rd, const Register& rn, const Register& rm) argument 798 Madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 809 Mneg(const Register& rd, const Register& rn, const Register& rm) argument 835 Msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 846 Mul(const Register& rd, const Register& rn, const Register& rm) argument 892 Ror(const Register& rd, const Register& rn, const Register& rm) argument 922 Sdiv(const Register& rd, const Register& rn, const Register& rm) argument 929 Smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 940 Smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 951 Smull(const Register& rd, const Register& rn, const Register& rm) argument 1028 Udiv(const Register& rd, const Register& rn, const Register& rm) argument 1035 Umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1046 Umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument [all...] |
H A D | simulator-a64.cc | 1151 int32_t rm = wreg(instr->Rm()); local 1152 if ((rn == kWMinInt) && (rm == -1)) { 1154 } else if (rm == 0) { 1158 result = rn / rm; 1164 int64_t rm = xreg(instr->Rm()); local 1165 if ((rn == kXMinInt) && (rm == -1)) { 1167 } else if (rm == 0) { 1171 result = rn / rm; 1177 uint32_t rm = static_cast<uint32_t>(wreg(instr->Rm())); local 1178 if (rm 1188 uint64_t rm = static_cast<uint64_t>(xreg(instr->Rm())); local [all...] |
H A D | assembler-a64.cc | 702 const Register& rm) { 704 VIXL_ASSERT(rd.size() == rm.size()); 705 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); 711 const Register& rm) { 713 VIXL_ASSERT(rd.size() == rm.size()); 714 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); 720 const Register& rm) { 722 VIXL_ASSERT(rd.size() == rm.size()); 723 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); 729 const Register& rm) { 700 lslv(const Register& rd, const Register& rn, const Register& rm) argument 709 lsrv(const Register& rd, const Register& rn, const Register& rm) argument 718 asrv(const Register& rd, const Register& rn, const Register& rm) argument 727 rorv(const Register& rd, const Register& rn, const Register& rm) argument 770 extr(const Register& rd, const Register& rn, const Register& rm, unsigned lsb) argument 781 csel(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 789 csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 797 csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 805 csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 845 ConditionalSelect(const Register& rd, const Register& rn, const Register& rm, Condition cond, ConditionalSelectOp op) argument 872 DataProcessing3Source(const Register& rd, const Register& rn, const Register& rm, const Register& ra, DataProcessing3SourceOp op) argument 881 mul(const Register& rd, const Register& rn, const Register& rm) argument 889 madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 897 mneg(const Register& rd, const Register& rn, const Register& rm) argument 905 msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 913 umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 923 smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 933 umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 943 smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 953 smull(const Register& rd, const Register& rn, const Register& rm) argument 962 sdiv(const Register& rd, const Register& rn, const Register& rm) argument 978 udiv(const Register& rd, const Register& rn, const Register& rm) argument 1168 mov(const Register& rd, const Register& rm) argument [all...] |
/external/chromium_org/third_party/skia/experimental/PdfViewer/src/ |
H A D | SkPdfRenderer.cpp | 804 SkRect rm = bBox; local 805 pdfContext->fGraphicsState.fCTM.mapRect(&rm); 807 SkTraceRect(rm, "bbox mapped");
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | RegionStore.cpp | 682 ClusterAnalysis(RegionStoreManager &rm, ProgramStateManager &StateMgr, argument 684 : RM(rm), Ctx(StateMgr.getContext()), 950 invalidateRegionsWorker(RegionStoreManager &rm, argument 959 : ClusterAnalysis<invalidateRegionsWorker>(rm, stateMgr, b, GFK), 2183 removeDeadBindingsWorker(RegionStoreManager &rm, argument 2187 : ClusterAnalysis<removeDeadBindingsWorker>(rm, stateMgr, b, GFK_None),
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/external/qemu/tcg/i386/ |
H A D | tcg-target.c | 373 static void tcg_out_opc(TCGContext *s, int opc, int r, int rm, int x) argument 393 rex |= (rm & 8) >> 3; /* REX.B */ 401 rex |= opc & (rm >= 4 ? P_REXB_RM : 0); 426 #define tcg_out_opc(s, opc, r, rm, x) (tcg_out_opc)(s, opc) 429 static void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) argument 431 tcg_out_opc(s, opc, r, rm, 0); 432 tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm)); 435 /* Output an opcode with a full "rm + (index<<shift) + offset" address mode. 440 static void tcg_out_modrm_sib_offset(TCGContext *s, int opc, int r, int rm, argument 445 if (index < 0 && rm < 523 tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, intptr_t offset) argument [all...] |
/external/skia/experimental/PdfViewer/src/ |
H A D | SkPdfRenderer.cpp | 804 SkRect rm = bBox; local 805 pdfContext->fGraphicsState.fCTM.mapRect(&rm); 807 SkTraceRect(rm, "bbox mapped");
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/external/chromium_org/third_party/icu/source/test/cintltst/ |
H A D | cbiditst.c | 1698 UBiDiReorderingMode rm; local 1761 rm = ubidi_getReorderingMode(bidi); 1763 if (rm != ubidi_getReorderingMode(bidi)) { 1767 if (rm != ubidi_getReorderingMode(bidi)) {
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/external/chromium_org/v8/src/arm/ |
H A D | assembler-arm.cc | 281 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { argument 284 rm_ = rm; 302 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) { argument 304 rm_ = rm; 319 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { argument 321 rm_ = rm; 328 MemOperand::MemOperand(Register rn, Register rm, argument 332 rm_ = rm; 347 NeonMemOperand::NeonMemOperand(Register rn, Register rm, int align) { argument 349 rm_ = rm; [all...] |
H A D | assembler-arm.h | 498 // rm 499 INLINE(explicit Operand(Register rm)); 501 // rm <shift_op> shift_imm 502 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); 503 INLINE(static Operand SmiUntag(Register rm)) { argument 504 return Operand(rm, ASR, kSmiTagSize); 515 // rm <shift_op> rs 516 explicit Operand(Register rm, ShiftOp shift_op, Register rs); 540 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED 566 // [rn +/- rm] Offse 594 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED 625 Register rm() const { return rm_; } function in class:v8::internal::BASE_EMBEDDED [all...] |
H A D | simulator-arm.cc | 2010 int rm = instr->RmValue(); local 2013 int32_t rm_val = get_register(rm); 2019 // Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 2034 // Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); 2039 // Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); 2055 // Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm"); 2090 int rm = instr->RmValue(); local 2091 int32_t rm_val = get_register(rm); 2094 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm"); 2102 // Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm"); 2218 int rm = instr->RmValue(); local 2239 int rm = instr->RmValue(); local 2718 int rm = instr->RmValue(); local [all...] |
/external/chromium_org/v8/src/arm64/ |
H A D | assembler-arm64.cc | 1242 const Register& rm) { 1244 DCHECK(rd.SizeInBits() == rm.SizeInBits()); 1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); 1251 const Register& rm) { 1253 DCHECK(rd.SizeInBits() == rm.SizeInBits()); 1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); 1260 const Register& rm) { 1262 DCHECK(rd.SizeInBits() == rm.SizeInBits()); 1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); 1269 const Register& rm) { 1240 lslv(const Register& rd, const Register& rn, const Register& rm) argument 1249 lsrv(const Register& rd, const Register& rn, const Register& rm) argument 1258 asrv(const Register& rd, const Register& rn, const Register& rm) argument 1267 rorv(const Register& rd, const Register& rn, const Register& rm) argument 1316 extr(const Register& rd, const Register& rn, const Register& rm, unsigned lsb) argument 1328 csel(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 1336 csinc(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 1344 csinv(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 1352 csneg(const Register& rd, const Register& rn, const Register& rm, Condition cond) argument 1392 ConditionalSelect(const Register& rd, const Register& rn, const Register& rm, Condition cond, ConditionalSelectOp op) argument 1419 DataProcessing3Source(const Register& rd, const Register& rn, const Register& rm, const Register& ra, DataProcessing3SourceOp op) argument 1428 mul(const Register& rd, const Register& rn, const Register& rm) argument 1437 madd(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1446 mneg(const Register& rd, const Register& rn, const Register& rm) argument 1455 msub(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1464 smaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1474 smsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1484 umaddl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1494 umsubl(const Register& rd, const Register& rn, const Register& rm, const Register& ra) argument 1504 smull(const Register& rd, const Register& rn, const Register& rm) argument 1513 smulh(const Register& rd, const Register& rn, const Register& rm) argument 1521 sdiv(const Register& rd, const Register& rn, const Register& rm) argument 1530 udiv(const Register& rd, const Register& rn, const Register& rm) argument 1726 mov(const Register& rd, const Register& rm) argument [all...] |
H A D | simulator-arm64.cc | 2012 T rm = reg<T>(instr->Rm()); local 2013 if ((rn == std::numeric_limits<T>::min()) && (rm == -1)) { 2015 } else if (rm == 0) { 2019 result = rn / rm; 2027 unsignedT rm = static_cast<unsignedT>(reg<T>(instr->Rm())); local 2028 if (rm == 0) { 2032 result = rn / rm;
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/external/chromium_org/v8/src/mips/ |
H A D | assembler-mips.cc | 258 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { argument 263 MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier, argument 264 OffsetAddend offset_addend) : Operand(rm) { 1659 DCHECK(!src.rm().is(at)); 1662 addu(at, at, src.rm()); // Add base register. 1668 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); 1678 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); 1688 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); 1698 GenInstrImmediate(LHU, rs.rm(), r [all...] |
/external/chromium_org/v8/src/mips64/ |
H A D | assembler-mips64.cc | 236 MemOperand::MemOperand(Register rm, int64_t offset) : Operand(rm) { argument 241 MemOperand::MemOperand(Register rm, int64_t unit, int64_t multiplier, argument 242 OffsetAddend offset_addend) : Operand(rm) { 1784 DCHECK(!src.rm().is(at)); 1789 daddu(at, at, src.rm()); // Add base register. 1795 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); 1805 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); 1815 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); 1825 GenInstrImmediate(LHU, rs.rm(), r [all...] |
/external/icu/icu4c/source/test/cintltst/ |
H A D | cbiditst.c | 1700 UBiDiReorderingMode rm; local 1763 rm = ubidi_getReorderingMode(bidi); 1765 if (rm != ubidi_getReorderingMode(bidi)) { 1769 if (rm != ubidi_getReorderingMode(bidi)) {
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