| /external/llvm/test/MC/X86/ |
| H A D | intel-syntax-2.s | 6 mov DWORD PTR [RSP - 4], 257
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| H A D | intel-syntax-encoding.s | 25 mov QWORD PTR [RSP - 16], RAX
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| H A D | intel-syntax.s | 9 mov DWORD PTR [RSP - 4], 257
11 mov DWORD PTR [RSP + 4], 258
13 mov QWORD PTR [RSP - 16], 123
15 mov BYTE PTR [RSP - 17], 97
17 mov EAX, DWORD PTR [RSP - 4]
19 mov RAX, QWORD PTR [RSP]
21 mov DWORD PTR [RSP - 4], -4
25 mov EAX, DWORD PTR [RSP + 4*RAX - 24]
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| /external/libunwind/src/x86_64/ |
| H A D | Gstash_frame.c | 42 rs->reg[RSP].where, rs->reg[RSP].val, DWARF_GET_LOC(d->loc[RSP]));
45 - CFA is register-relative offset off RBP or RSP;
48 - RSP is unsaved or saved at CFA+offset, offset != -1. */
52 || rs->reg[DWARF_CFA_REG_COLUMN].val == RSP)
60 && (rs->reg[RSP].where == DWARF_WHERE_UNDEF
61 || rs->reg[RSP].where == DWARF_WHERE_SAME
62 || (rs->reg[RSP].where == DWARF_WHERE_CFAREL
63 && labs(rs->reg[RSP]
[all...] |
| H A D | Gget_save_loc.c | 41 case UNW_X86_64_RSP: loc = c->dwarf.loc[RSP]; break;
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| H A D | unwind_i.h | 46 #define RSP 7 macro
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| H A D | init.h | 56 c->dwarf.loc[RSP] = REG_INIT_LOC(c, rsp, RSP);
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| H A D | Gos-freebsd.c | 118 c->dwarf.loc[RSP] = DWARF_LOC (ucontext + UC_MCONTEXT_GREGS_RSP, 0);
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| H A D | Gstep.c | 127 /* Like regular frame, CFA = RSP+8, RA = [CFA-8], no regs saved. */
195 c->dwarf.loc[RSP] = rsp_loc;
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| /external/kernel-headers/original/uapi/asm-x86/asm/ |
| H A D | ptrace-abi.h | 50 #define RSP 152 macro
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| /external/llvm/lib/Target/X86/ |
| H A D | X86CompilationCallback_Win64.asm | 20 ; Save RSP.
53 ; Restore RSP.
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| H A D | X86RegisterInfo.cpp | 71 StackPtr = X86::RSP;
330 for (MCSubRegIterator I(X86::RSP, this, /*IncludeSelf=*/true); I.isValid();
548 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
576 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
613 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
649 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
685 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
686 return X86::RSP;
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| H A D | X86FrameLowering.cpp | 1390 ScratchReg = X86::RSP;
1392 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1611 SPReg = X86::RSP;
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| /external/ltrace/sysdeps/linux-gnu/x86/ |
| H A D | regs.c | 44 # define XSP (8 * RSP)
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| /external/chromium_org/third_party/yasm/source/patched-yasm/modules/objfmts/win64/tests/ |
| H A D | sce1.asm | 15 [savereg rdi, 010h]; you can still use RSP as the base of the frame
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| H A D | sce3.asm | 15 [savereg rdi, 010h]; you can still use RSP as the base of the frame
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| /external/lzma/Asm/x86/ |
| H A D | 7zAsm.asm | 66 r4 equ RSP
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| /external/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86AsmInstrumentation.cpp | 36 return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
328 Inst.addOperand(MCOperand::CreateReg(X86::RSP));
332 X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
342 EmitInstruction(Out, MCInstBuilder(X86::AND64ri8).addReg(X86::RSP)
343 .addReg(X86::RSP).addImm(-16));
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| H A D | X86Operand.h | 348 case X86::RSP: return X86::ESP;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 287 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
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| H A D | X86MCCodeEmitter.cpp | 495 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
545 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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| /external/valgrind/main/VEX/auxprogs/ |
| H A D | genoffsets.c | 109 GENOFFSET(AMD64,amd64,RSP);
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| /external/valgrind/main/coregrind/m_sigframe/ |
| H A D | sigframe-amd64-linux.c | 360 SC2(rsp,RSP);
515 /* tst->m_rsp = rsp; also notify the tool we've updated RSP */
538 VG_(printf)("pushed signal frame; %%RSP now = %#lx, "
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| /external/libunwind/src/ptrace/ |
| H A D | _UPT_reg_offset.c | 300 UNW_R_OFF(RSP, rsp)
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| /external/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 193 ENTRY(RSP) \
|