/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86DisassemblerDecoder.cpp | 192 * @param insn - The instruction with the reader function to use. The cursor 198 static int consumeByte(struct InternalInstruction* insn, uint8_t* byte) { argument 199 int ret = insn->reader(insn->readerArg, byte, insn->readerCursor); 202 ++(insn->readerCursor); 210 * @param insn - See consumeByte(). 214 static int lookAtByte(struct InternalInstruction* insn, uint8_t* byte) { argument 215 return insn->reader(insn 218 unconsumeByte(struct InternalInstruction* insn) argument 265 dbgprintf(struct InternalInstruction* insn, const char* format, ...) argument 292 setPrefixPresent(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument 309 isPrefixAtLocation(struct InternalInstruction* insn, uint8_t prefix, uint64_t location) argument 329 readPrefixes(struct InternalInstruction* insn) argument 692 readOpcode(struct InternalInstruction* insn) argument 812 getIDWithAttrMask(uint16_t* instructionID, struct InternalInstruction* insn, uint16_t attrMask) argument 877 getID(struct InternalInstruction* insn, const void *miiArg) argument 1098 readSIB(struct InternalInstruction* insn) argument 1196 readDisplacement(struct InternalInstruction* insn) argument 1241 readModRM(struct InternalInstruction* insn) argument 1465 fixupReg(struct InternalInstruction *insn, const struct OperandSpecifier *op) argument 1517 readOpcodeRegister(struct InternalInstruction* insn, uint8_t size) argument 1564 readImmediate(struct InternalInstruction* insn, uint8_t size) argument 1618 readVVVV(struct InternalInstruction* insn) argument 1648 readMaskRegister(struct InternalInstruction* insn) argument 1666 readOperands(struct InternalInstruction* insn) argument 1806 decodeInstruction( struct InternalInstruction *insn, byteReader_t reader, const void *readerArg, dlog_t logger, void *loggerArg, const void *miiArg, uint64_t startLoc, DisassemblerMode mode) argument [all...] |
/external/valgrind/main/none/tests/s390x/ |
H A D | fpext.c | 6 #define L2F(insn, initial, target,round) \ 10 asm volatile(insn(round,0,0,2) :"=f" (_t):"d"(source)); \ 14 #define F2L(insn, initial, type, round, cc) \ 18 asm volatile(insn(round,0,2,0) \ 26 #define DO_INSN_L2F32(insn, round) \ 29 printf(#insn " %f\n", L2F(insn, 0, f32, round)); \ 30 printf(#insn " %f\n", L2F(insn, 1, f32, round)); \ 31 printf(#insn " [all...] |
H A D | comp-1.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \ 26 asm volatile( #insn " %1, %2\n\t" \ 33 #insn, op1, op2, cc); \ 38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \ 43 asm volatile( #insn " %1, %2\n\t" \ 50 #insn, op1, (int64_t)op2, cc); \ 55 #define SCOMP_REG_IMM(insn, v1, v2) \ 59 asm volatile( insn(8, v2) \ 66 #insn, op1, (int64_t)v2, cc); \ 69 /* Run a sequence of signed comparisons for a given insn */ [all...] |
H A D | fpconv.c | 12 We do not test rounding here. Just making sure the insn selector 13 picks the correct insn. 16 #define I2F(insn, initial, target_type) \ 20 asm volatile(insn " %0,%1\n\t" :"=f" (target) :"d"(source)); \ 21 printf(insn " %"PRId64" -> %f\n", source, target); \ 24 #define DO_INSN_I32_TO_F(insn, target_type) \ 27 I2F(insn, 0, target_type); \ 28 I2F(insn, 1, target_type); \ 29 I2F(insn, -1, target_type); \ 30 I2F(insn, 4 [all...] |
H A D | comp-2.c | 21 #define SCOMP_REG_REG(insn, v1, v2) \ 26 asm volatile( #insn " %1, %2\n\t" \ 33 #insn, op1, op2, cc); \ 38 #define SCOMP_REG_MEM(insn, v1, v2, op2_t) \ 43 asm volatile( #insn " %1, %2\n\t" \ 50 #insn, op1, (uint64_t)op2, cc); \ 55 #define SCOMP_REG_IMM(insn, v1, v2) \ 59 asm volatile( insn(8, v2) \ 66 #insn, op1, (uint64_t)v2, cc); \ 69 /* Run a sequence of unsigned comparisons for a given insn */ [all...] |
H A D | condloadstore.c | 5 #define LOAD_REG_MEM(insn, s, ccset, initial, mask) \ 19 insn(1,mask,5,000,00) \ 23 printf(#insn " %16.16lX into %16.16lX if mask" \ 29 #define LOAD_REG_REG(insn, s, ccset, initial, mask) \ 42 insn(mask,1,2) \ 46 printf(#insn " %16.16lX into %16.16lX if mask" \ 51 #define STORE_REG_REG(insn, s, ccset, initial, mask) \ 65 insn(1,mask,5,000,00) \ 69 printf(#insn " %16.16lX into %16.16lX if mask" \ 75 #define INSNVALCCINIT(insn, valu [all...] |
H A D | dfpext.c | 7 #define L2D(insn, initial, target,round) \ 11 asm volatile(insn(round,0,0,2) :"=f" (_t):"d"(source)); \ 15 #define I2D(insn, initial, target,round) \ 19 asm volatile(insn(round,0,0,2) :"=f" (_t):"d"(source)); \ 23 #define D2L(insn, initial, type, round, cc) \ 27 asm volatile(insn(round,0,2,0) \ 34 #define D2I(insn, initial, type, round, cc) \ 38 asm volatile(insn(round,0,2,0) \ 46 #define DO_PRINT_L2D(insn, l, d, round) \ 48 printf(#insn " roun [all...] |
/external/libpcap/ |
H A D | bpf_dump.c | 36 const struct bpf_insn *insn; local 40 insn = p->bf_insns; 43 for (i = 0; i < n; ++insn, ++i) { 44 printf("%u %u %u %u\n", insn->code, 45 insn->jt, insn->jf, insn->k); 50 for (i = 0; i < n; ++insn, ++i) 52 insn->code, insn [all...] |
/external/tcpdump/ |
H A D | bpf_dump.c | 40 struct bpf_insn *insn; local 44 insn = p->bf_insns; 47 for (i = 0; i < n; ++insn, ++i) { 48 printf("%u %u %u %u\n", insn->code, 49 insn->jt, insn->jf, insn->k); 54 for (i = 0; i < n; ++insn, ++i) 56 insn->code, insn [all...] |
/external/dexmaker/src/dx/java/com/android/dx/dex/code/form/ |
H A D | Form30t.java | 42 public String insnArgString(DalvInsn insn) { argument 43 return branchString(insn); 48 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 49 return branchComment(insn); 60 public boolean isCompatible(DalvInsn insn) { argument 61 if (!((insn instanceof TargetInsn) && 62 (insn.getRegisters().size() == 0))) { 71 public boolean branchFits(TargetInsn insn) { argument 77 public void writeTo(AnnotatedOutput out, DalvInsn insn) { argument 78 int offset = ((TargetInsn) insn) [all...] |
H A D | Form21t.java | 45 public String insnArgString(DalvInsn insn) { argument 46 RegisterSpecList regs = insn.getRegisters(); 47 return regs.get(0).regString() + ", " + branchString(insn); 52 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 53 return branchComment(insn); 64 public boolean isCompatible(DalvInsn insn) { argument 65 RegisterSpecList regs = insn.getRegisters(); 67 if (!((insn instanceof TargetInsn) && 73 TargetInsn ti = (TargetInsn) insn; 79 public BitSet compatibleRegs(DalvInsn insn) { argument 89 branchFits(TargetInsn insn) argument 98 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form22t.java | 45 public String insnArgString(DalvInsn insn) { argument 46 RegisterSpecList regs = insn.getRegisters(); 48 ", " + branchString(insn); 53 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 54 return branchComment(insn); 65 public boolean isCompatible(DalvInsn insn) { argument 66 RegisterSpecList regs = insn.getRegisters(); 68 if (!((insn instanceof TargetInsn) && 75 TargetInsn ti = (TargetInsn) insn; 81 public BitSet compatibleRegs(DalvInsn insn) { argument 92 branchFits(TargetInsn insn) argument 101 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form10t.java | 42 public String insnArgString(DalvInsn insn) { argument 43 return branchString(insn); 48 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 49 return branchComment(insn); 60 public boolean isCompatible(DalvInsn insn) { argument 61 if (!((insn instanceof TargetInsn) && 62 (insn.getRegisters().size() == 0))) { 66 TargetInsn ti = (TargetInsn) insn; 72 public boolean branchFits(TargetInsn insn) { argument 73 int offset = insn 81 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form20t.java | 42 public String insnArgString(DalvInsn insn) { argument 43 return branchString(insn); 48 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 49 return branchComment(insn); 60 public boolean isCompatible(DalvInsn insn) { argument 61 if (!((insn instanceof TargetInsn) && 62 (insn.getRegisters().size() == 0))) { 66 TargetInsn ti = (TargetInsn) insn; 72 public boolean branchFits(TargetInsn insn) { argument 73 int offset = insn 81 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form31i.java | 47 public String insnArgString(DalvInsn insn) { argument 48 RegisterSpecList regs = insn.getRegisters(); 49 CstLiteralBits value = (CstLiteralBits) ((CstInsn) insn).getConstant(); 56 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 57 CstLiteralBits value = (CstLiteralBits) ((CstInsn) insn).getConstant(); 69 public boolean isCompatible(DalvInsn insn) { argument 70 RegisterSpecList regs = insn.getRegisters(); 71 if (!((insn instanceof CstInsn) && 77 CstInsn ci = (CstInsn) insn; 89 public BitSet compatibleRegs(DalvInsn insn) { argument 99 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form31t.java | 45 public String insnArgString(DalvInsn insn) { argument 46 RegisterSpecList regs = insn.getRegisters(); 47 return regs.get(0).regString() + ", " + branchString(insn); 52 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 53 return branchComment(insn); 64 public boolean isCompatible(DalvInsn insn) { argument 65 RegisterSpecList regs = insn.getRegisters(); 67 if (!((insn instanceof TargetInsn) && 78 public BitSet compatibleRegs(DalvInsn insn) { argument 79 RegisterSpecList regs = insn 88 branchFits(TargetInsn insn) argument 94 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form51l.java | 48 public String insnArgString(DalvInsn insn) { argument 49 RegisterSpecList regs = insn.getRegisters(); 50 CstLiteralBits value = (CstLiteralBits) ((CstInsn) insn).getConstant(); 57 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 58 CstLiteralBits value = (CstLiteralBits) ((CstInsn) insn).getConstant(); 70 public boolean isCompatible(DalvInsn insn) { argument 71 RegisterSpecList regs = insn.getRegisters(); 72 if (!((insn instanceof CstInsn) && 78 CstInsn ci = (CstInsn) insn; 86 public BitSet compatibleRegs(DalvInsn insn) { argument 96 writeTo(AnnotatedOutput out, DalvInsn insn) argument [all...] |
H A D | Form11x.java | 45 public String insnArgString(DalvInsn insn) { argument 46 RegisterSpecList regs = insn.getRegisters(); 52 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 65 public boolean isCompatible(DalvInsn insn) { argument 66 RegisterSpecList regs = insn.getRegisters(); 67 return (insn instanceof SimpleInsn) && 74 public BitSet compatibleRegs(DalvInsn insn) { argument 75 RegisterSpecList regs = insn.getRegisters(); 84 public void writeTo(AnnotatedOutput out, DalvInsn insn) { argument 85 RegisterSpecList regs = insn [all...] |
H A D | Form10x.java | 42 public String insnArgString(DalvInsn insn) { argument 49 public String insnCommentString(DalvInsn insn, boolean noteIndices) { argument 62 public boolean isCompatible(DalvInsn insn) { argument 63 return (insn instanceof SimpleInsn) && 64 (insn.getRegisters().size() == 0); 69 public void writeTo(AnnotatedOutput out, DalvInsn insn) { argument 70 write(out, opcodeUnit(insn, 0));
|
/external/mockito/cglib-and-asm/src/org/mockito/asm/tree/ |
H A D | InsnList.java | 127 * @param insn an instruction.
130 public boolean contains(final AbstractInsnNode insn) {
argument 132 while (i != null && i != insn) {
145 * @param insn an instruction <i>of this list</i>.
151 * if insn does not belong to this list.
153 public int indexOf(final AbstractInsnNode insn) {
argument 154 if (check && !contains(insn)) {
160 return insn.index;
169 AbstractInsnNode insn = first;
170 while (insn ! 221 set(final AbstractInsnNode location, final AbstractInsnNode insn) argument 259 add(final AbstractInsnNode insn) argument 312 insert(final AbstractInsnNode insn) argument 368 insert(final AbstractInsnNode location, final AbstractInsnNode insn) argument 430 insertBefore(final AbstractInsnNode location, final AbstractInsnNode insn) argument 490 remove(final AbstractInsnNode insn) argument [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_eu_emit.c | 44 struct brw_instruction *insn, 48 insn->header.execution_size = BRW_EXECUTE_16; 50 insn->header.execution_size = reg.width; /* note - definitions are compatible */ 104 brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, argument 113 insn->bits1.da1.dest_reg_file = dest.file; 114 insn->bits1.da1.dest_reg_type = dest.type; 115 insn->bits1.da1.dest_address_mode = dest.address_mode; 118 insn->bits1.da1.dest_reg_nr = dest.nr; 120 if (insn->header.access_mode == BRW_ALIGN_1) { 121 insn 43 guess_execution_size(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 160 validate_reg(struct brw_instruction *insn, struct brw_reg reg) argument 236 brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 314 brw_set_src1(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 427 brw_set_math_message( struct brw_compile *p, struct brw_instruction *insn, GLuint function, GLuint integer_type, bool low_precision, GLuint dataType ) argument 484 brw_set_ff_sync_message(struct brw_compile *p, struct brw_instruction *insn, bool allocate, GLuint response_length, bool end_of_thread) argument 500 brw_set_urb_message( struct brw_compile *p, struct brw_instruction *insn, bool allocate, bool used, GLuint msg_length, GLuint response_length, bool end_of_thread, bool complete, GLuint offset, GLuint swizzle_control ) argument 542 brw_set_dp_write_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint msg_control, GLuint msg_type, GLuint msg_length, bool header_present, GLuint last_render_target, GLuint response_length, GLuint end_of_thread, GLuint send_commit_msg) argument 601 brw_set_dp_read_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint msg_control, GLuint msg_type, GLuint target_cache, GLuint msg_length, GLuint response_length) argument 658 brw_set_sampler_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint sampler, GLuint msg_type, GLuint response_length, GLuint msg_length, GLuint header_present, GLuint simd_mode, GLuint return_format) argument 702 struct brw_instruction *insn; local 734 struct brw_instruction *insn = next_insn(p, opcode); local 746 struct brw_instruction *insn = next_insn(p, opcode); local 771 struct brw_instruction *insn = next_insn(p, opcode); local 993 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP); local 1012 struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1); local 1082 struct brw_instruction *insn; local 1126 struct brw_instruction *insn; local 1285 struct brw_instruction *insn; local 1318 struct brw_instruction *insn = NULL; local 1396 struct brw_instruction *insn; local 1418 struct brw_instruction *insn; local 1434 struct brw_instruction *insn; local 1471 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); local 1524 struct brw_instruction *insn, *do_insn; local 1615 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP); local 1640 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT); local 1669 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH); local 1701 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 1729 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH); local 1785 struct brw_instruction *insn; local 1895 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2002 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2059 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2104 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2136 struct brw_instruction *insn; local 2206 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2247 struct brw_instruction *insn; local 2384 struct brw_instruction *insn; local 2439 struct brw_instruction *insn; local 2483 struct brw_instruction *insn = &p->store[ip]; local 2508 struct brw_instruction *insn = &p->store[ip]; local 2535 struct brw_instruction *insn = &p->store[ip]; local 2564 struct brw_instruction *insn; local 2602 struct brw_instruction *insn; local [all...] |
/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_eu_emit.c | 44 struct brw_instruction *insn, 48 insn->header.execution_size = BRW_EXECUTE_16; 50 insn->header.execution_size = reg.width; /* note - definitions are compatible */ 104 brw_set_dest(struct brw_compile *p, struct brw_instruction *insn, argument 113 insn->bits1.da1.dest_reg_file = dest.file; 114 insn->bits1.da1.dest_reg_type = dest.type; 115 insn->bits1.da1.dest_address_mode = dest.address_mode; 118 insn->bits1.da1.dest_reg_nr = dest.nr; 120 if (insn->header.access_mode == BRW_ALIGN_1) { 121 insn 43 guess_execution_size(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 160 validate_reg(struct brw_instruction *insn, struct brw_reg reg) argument 236 brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 314 brw_set_src1(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) argument 427 brw_set_math_message( struct brw_compile *p, struct brw_instruction *insn, GLuint function, GLuint integer_type, bool low_precision, GLuint dataType ) argument 484 brw_set_ff_sync_message(struct brw_compile *p, struct brw_instruction *insn, bool allocate, GLuint response_length, bool end_of_thread) argument 500 brw_set_urb_message( struct brw_compile *p, struct brw_instruction *insn, bool allocate, bool used, GLuint msg_length, GLuint response_length, bool end_of_thread, bool complete, GLuint offset, GLuint swizzle_control ) argument 542 brw_set_dp_write_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint msg_control, GLuint msg_type, GLuint msg_length, bool header_present, GLuint last_render_target, GLuint response_length, GLuint end_of_thread, GLuint send_commit_msg) argument 601 brw_set_dp_read_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint msg_control, GLuint msg_type, GLuint target_cache, GLuint msg_length, GLuint response_length) argument 658 brw_set_sampler_message(struct brw_compile *p, struct brw_instruction *insn, GLuint binding_table_index, GLuint sampler, GLuint msg_type, GLuint response_length, GLuint msg_length, GLuint header_present, GLuint simd_mode, GLuint return_format) argument 702 struct brw_instruction *insn; local 734 struct brw_instruction *insn = next_insn(p, opcode); local 746 struct brw_instruction *insn = next_insn(p, opcode); local 771 struct brw_instruction *insn = next_insn(p, opcode); local 993 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP); local 1012 struct brw_instruction *insn = brw_alu2(p, BRW_OPCODE_JMPI, dest, src0, src1); local 1082 struct brw_instruction *insn; local 1126 struct brw_instruction *insn; local 1285 struct brw_instruction *insn; local 1318 struct brw_instruction *insn = NULL; local 1396 struct brw_instruction *insn; local 1418 struct brw_instruction *insn; local 1434 struct brw_instruction *insn; local 1471 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_DO); local 1524 struct brw_instruction *insn, *do_insn; local 1615 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_CMP); local 1640 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT); local 1669 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH); local 1701 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 1729 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_MATH); local 1785 struct brw_instruction *insn; local 1895 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2002 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2059 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2104 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2136 struct brw_instruction *insn; local 2206 struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND); local 2247 struct brw_instruction *insn; local 2384 struct brw_instruction *insn; local 2439 struct brw_instruction *insn; local 2483 struct brw_instruction *insn = &p->store[ip]; local 2508 struct brw_instruction *insn = &p->store[ip]; local 2535 struct brw_instruction *insn = &p->store[ip]; local 2564 struct brw_instruction *insn; local 2602 struct brw_instruction *insn; local [all...] |
/external/valgrind/main/memcheck/tests/amd64/ |
H A D | insn-pcmpistri.stderr.exp | 2 at 0x........: aligned_strlen (insn-pcmpistri.c:21) 3 by 0x........: test_strlen (insn-pcmpistri.c:62) 4 by 0x........: doit (insn-pcmpistri.c:74) 5 by 0x........: main (insn-pcmpistri.c:79) 8 at 0x........: doit (insn-pcmpistri.c:73) 9 by 0x........: main (insn-pcmpistri.c:79) 13 at 0x........: aligned_strlen (insn-pcmpistri.c:21) 14 by 0x........: test_strlen (insn-pcmpistri.c:62) 15 by 0x........: doit (insn-pcmpistri.c:74) 16 by 0x........: main (insn [all...] |
/external/dexmaker/src/dx/java/com/android/dx/ssa/ |
H A D | NormalSsaInsn.java | 22 * A "normal" (non-phi) instruction in SSA form. Always wraps a rop insn. 25 /** {@code non-null;} rop insn that we're wrapping */ 26 private Insn insn; field in class:NormalSsaInsn 31 * @param insn Rop insn to wrap 32 * @param block block that contains this insn 34 NormalSsaInsn(final Insn insn, final SsaBasicBlock block) { argument 35 super(insn.getResult(), block); 36 this.insn = insn; [all...] |
/external/chromium_org/sandbox/linux/seccomp-bpf/ |
H A D | verifier.cc | 171 void Ld(State* state, const struct sock_filter& insn, const char** err) { argument 172 if (BPF_SIZE(insn.code) != BPF_W || BPF_MODE(insn.code) != BPF_ABS) { 176 if (insn.k < sizeof(struct arch_seccomp_data) && (insn.k & 3) == 0) { 179 reinterpret_cast<const char*>(&state->data) + insn.k, 189 void Jmp(State* state, const struct sock_filter& insn, const char** err) { argument 190 if (BPF_OP(insn.code) == BPF_JA) { 191 if (state->ip + insn.k + 1 >= state->program.size() || 192 state->ip + insn 239 Ret(State*, const struct sock_filter& insn, const char** err) argument 247 Alu(State* state, const struct sock_filter& insn, const char** err) argument 362 const struct sock_filter& insn = program[state.ip]; local [all...] |