Searched refs:LWR (Results 1 - 11 of 11) sorted by relevance
| /external/chromium_org/v8/src/mips/ |
| H A D | constants-mips.cc | 317 case LWR:
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| H A D | constants-mips.h | 350 LWR = ((4 << 3) + 6) << kOpcodeShift,
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| H A D | simulator-mips.cc | 2876 case LWR: {
2969 case LWR:
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| H A D | assembler-mips.cc | 1722 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
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| /external/chromium_org/v8/src/mips64/ |
| H A D | constants-mips64.cc | 337 case LWR:
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| H A D | constants-mips64.h | 319 LWR = ((4 << 3) + 6) << kOpcodeShift,
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| H A D | simulator-mips64.cc | 2842 // Alignment for 32-bit integers used in LWL, LWR, etc.
3023 case LWR: {
3122 case LWR:
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| H A D | assembler-mips64.cc | 1859 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 222 case Mips::LWR:
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 198 LWR, enumerator in enum:llvm::MipsISD::NodeType
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| H A D | MipsISelLowering.cpp | 156 case MipsISD::LWR: return "MipsISD::LWR";
2057 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, local
2069 return LWR;
2082 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2084 SDValue Ops[] = { SRL, LWR.getValue(1) };
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