Searched refs:RegIndex (Results 1 - 10 of 10) sorted by relevance
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUInstrInfo.cpp | 136 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); local 138 unsigned Address = calculateIndirectAddress(RegIndex, Channel); 151 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm(); local 153 unsigned Address = calculateIndirectAddress(RegIndex, Channel); 160 calculateIndirectAddress(RegIndex, Channel), 299 unsigned RegIndex; local 301 for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; 302 ++RegIndex) { 303 if (IndirectRC->getRegister(RegIndex) [all...] |
H A D | AMDGPUInstrInfo.h | 150 /// \brief Calculate the "Indirect Address" for the given \p RegIndex and 155 /// address in this virtual address space that maps to the given \p RegIndex 157 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
|
H A D | SIInstrInfo.h | 155 unsigned calculateIndirectAddress(unsigned RegIndex,
|
H A D | R600InstrInfo.h | 216 unsigned calculateIndirectAddress(unsigned RegIndex,
|
H A D | R600InstrInfo.cpp | 1105 unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, 1109 return RegIndex;
|
H A D | R600ISelLowering.cpp | 597 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local 598 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); 630 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local 631 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
|
H A D | SIInstrInfo.cpp | 1356 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex, argument 1359 return RegIndex;
|
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 99 int64_t RegIndex = MI->getOperand(1).getImm(); local 100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex); 261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); 282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local 283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ISelLowering.cpp | 99 int64_t RegIndex = MI->getOperand(1).getImm(); local 100 unsigned ConstantReg = AMDGPU::R600_CReg32RegClass.getRegister(RegIndex); 261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); local 262 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); 282 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); local 283 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
|
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1426 void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) { argument 1427 if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) { 1428 if (RegIndex == 1) 1431 Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" + 1432 Twine(RegIndex) + "\"");
|
Completed in 133 milliseconds