Searched refs:c_code (Results 1 - 10 of 10) sorted by path

/art/compiler/dex/quick/arm/
H A Dcodegen_arm.h142 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
H A Dint_arm.cc1102 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument
1106 return OpCondBranch(c_code, target);
/art/compiler/dex/quick/arm64/
H A Dcodegen_arm64.h208 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
H A Dint_arm64.cc942 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument
949 return OpCondBranch(c_code, target);
/art/compiler/dex/quick/
H A Dgen_common.cc56 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { argument
57 LIR* branch = OpCondBranch(c_code, nullptr);
H A Dmir_to_lir.h827 // c_code holds condition code that's generated from testing divisor against 0.
828 void GenDivZeroCheck(ConditionCode c_code);
1391 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0;
/art/compiler/dex/quick/mips/
H A Dcodegen_mips.h140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
H A Dint_mips.cc369 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument
371 return OpCmpImmBranch(c_code, reg, 0, target);
/art/compiler/dex/quick/x86/
H A Dcodegen_x86.h267 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
H A Dint_x86.cc1236 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument
1238 return OpCondBranch(c_code, target);

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