Searched refs:c_code (Results 1 - 10 of 10) sorted by path
/art/compiler/dex/quick/arm/ |
H A D | codegen_arm.h | 142 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
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H A D | int_arm.cc | 1102 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument 1106 return OpCondBranch(c_code, target);
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/art/compiler/dex/quick/arm64/ |
H A D | codegen_arm64.h | 208 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
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H A D | int_arm64.cc | 942 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument 949 return OpCondBranch(c_code, target);
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/art/compiler/dex/quick/ |
H A D | gen_common.cc | 56 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { argument 57 LIR* branch = OpCondBranch(c_code, nullptr);
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H A D | mir_to_lir.h | 827 // c_code holds condition code that's generated from testing divisor against 0. 828 void GenDivZeroCheck(ConditionCode c_code); 1391 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0;
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/art/compiler/dex/quick/mips/ |
H A D | codegen_mips.h | 140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
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H A D | int_mips.cc | 369 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument 371 return OpCmpImmBranch(c_code, reg, 0, target);
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/art/compiler/dex/quick/x86/ |
H A D | codegen_x86.h | 267 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
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H A D | int_x86.cc | 1236 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { argument 1238 return OpCondBranch(c_code, target);
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