Searched refs:getSchedModel (Results 1 - 12 of 12) sorted by relevance

/external/llvm/include/llvm/MC/
H A DMCSubtargetInfo.h87 /// getSchedModel - Get the machine model for this subtarget's CPU.
89 const MCSchedModel *getSchedModel() const { return CPUSchedModel; } function in class:llvm::MCSubtargetInfo
/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp126 SchedModel.init(*ST.getSchedModel(), &ST, TII);
H A DAArch64ConditionalCompares.cpp897 MF.getTarget().getSubtarget<TargetSubtargetInfo>().getSchedModel();
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h171 const TargetSchedModel *getSchedModel() const { return &SchedModel; } function in class:llvm::ScheduleDAGInstrs
/external/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp200 SchedModel = DAG->getSchedModel();
207 const InstrItineraryData *Itin = DAG->getSchedModel()->getInstrItineraries();
216 Top.ResourceModel = new VLIWResourceModel(TM, DAG->getSchedModel());
217 Bot.ResourceModel = new VLIWResourceModel(TM, DAG->getSchedModel());
/external/llvm/lib/CodeGen/
H A DBasicTargetTransformInfo.cpp229 else if (ST->getSchedModel()->LoopMicroOpBufferSize > 0)
230 MaxOps = ST->getSchedModel()->LoopMicroOpBufferSize;
H A DEarlyIfConversion.cpp788 MF.getTarget().getSubtarget<TargetSubtargetInfo>().getSchedModel();
H A DMachineTraceMetrics.cpp61 SchedModel.init(*ST.getSchedModel(), &ST, TII);
H A DIfConversion.cpp280 SchedModel.init(*ST.getSchedModel(), &ST, TII);
H A DScheduleDAGInstrs.cpp67 SchedModel.init(*ST.getSchedModel(), &ST, TII);
H A DMachineScheduler.cpp2346 SchedModel = DAG->getSchedModel();
2878 SchedModel = DAG->getSchedModel();
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp205 const MCSchedModel *SCModel = STI->getSchedModel();

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