Searched refs:isT2 (Results 1 - 1 of 1) sorted by relevance

/external/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp1366 const TargetInstrInfo *TII, bool isT2) {
1402 bool isT2 = Opcode == ARM::t2LDRDi8 || Opcode == ARM::t2STRDi8; local
1412 bool OffKill = isT2 ? false : MI->getOperand(3).isKill();
1413 bool OffUndef = isT2 ? false : MI->getOperand(3).isUndef();
1422 ? (isT2 ? ARM::t2LDMIA : ARM::LDMIA)
1423 : (isT2 ? ARM::t2STMIA : ARM::STMIA);
1445 ? (isT2 ? (OffImm < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
1446 : (isT2 ? (OffImm < 0 ? ARM::t2STRi8 : ARM::t2STRi12) : ARM::STRi12);
1450 ? (isT2 ? (OffImm+4 < 0 ? ARM::t2LDRi8 : ARM::t2LDRi12) : ARM::LDRi12)
1451 : (isT2
1358 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument
1875 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument
2039 bool isT2 = false; local
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