Searched refs:operands (Results 1 - 25 of 195) sorted by relevance

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/external/srec/srec/Semproc/src/
H A DExpressionEvaluator.c39 ESR_ReturnCode EE_concat(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen) argument
44 if (operands == NULL || resultBuf == NULL || resultLen == NULL)
52 opLen = LSTRLEN(operands[i]);
54 LSTRCAT(resultBuf, operands[i]);
62 ESR_ReturnCode EE_conditional(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen) argument
64 if (operands == NULL || resultBuf == NULL || resultLen == NULL)
70 if (!LSTRCMP(operands[0], UNDEFINED_SYMBOL) || !operands[0] ||
71 !LSTRCMP(operands[0], FALSE_SYMBOL))
73 if (strlen(operands[
96 EE_add(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen) argument
112 EE_subtract(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen) argument
[all...]
/external/chromium_org/third_party/mesa/src/src/glsl/
H A Dlower_instructions.cpp128 ir->operands[1] = new(ir) ir_expression(ir_unop_neg, ir->operands[1]->type,
129 ir->operands[1], NULL);
136 assert(ir->operands[1]->type->is_float());
141 ir->operands[1]->type,
142 ir->operands[1]);
146 ir->operands[1] = expr;
154 assert(ir->operands[1]->type->is_integer());
164 ir->operands[1]->type->vector_elements,
165 ir->operands[
[all...]
H A Dopt_algebraic.cpp96 if (ir->operands[0]->type->is_vector())
97 ir->type = ir->operands[0]->type;
99 ir->type = ir->operands[1]->type;
108 ir_rvalue *temp = ir2->operands[op2];
109 ir2->operands[op2] = ir1->operands[op1];
110 ir1->operands[op1] = temp;
113 * base types matched, and at least one of the operands of the 2
135 if (ir1->operands[0]->type->is_matrix() ||
136 ir1->operands[
[all...]
H A Dir_validate.cpp231 assert(ir->operands[0]->type == ir->type);
235 assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL);
244 assert(ir->type == ir->operands[0]->type);
251 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
252 assert(ir->type == ir->operands[0]->type);
256 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
260 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
264 assert(ir->operands[0]->type->base_type == GLSL_TYPE_INT);
268 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
272 assert(ir->operands[
[all...]
H A Dlower_vector.cpp67 ir_rvalue *op = ir->operands[i];
98 op = ex->operands[0];
162 const ir_constant *const c = expr->operands[i]->as_constant();
198 if (expr->operands[i]->ir_type == ir_type_constant)
203 new(mem_ctx) ir_assignment(lhs, expr->operands[i], NULL, (1U << i));
/external/mesa3d/src/glsl/
H A Dlower_instructions.cpp128 ir->operands[1] = new(ir) ir_expression(ir_unop_neg, ir->operands[1]->type,
129 ir->operands[1], NULL);
136 assert(ir->operands[1]->type->is_float());
141 ir->operands[1]->type,
142 ir->operands[1]);
146 ir->operands[1] = expr;
154 assert(ir->operands[1]->type->is_integer());
164 ir->operands[1]->type->vector_elements,
165 ir->operands[
[all...]
H A Dopt_algebraic.cpp96 if (ir->operands[0]->type->is_vector())
97 ir->type = ir->operands[0]->type;
99 ir->type = ir->operands[1]->type;
108 ir_rvalue *temp = ir2->operands[op2];
109 ir2->operands[op2] = ir1->operands[op1];
110 ir1->operands[op1] = temp;
113 * base types matched, and at least one of the operands of the 2
135 if (ir1->operands[0]->type->is_matrix() ||
136 ir1->operands[
[all...]
H A Dir_validate.cpp231 assert(ir->operands[0]->type == ir->type);
235 assert(ir->operands[0]->type->base_type == GLSL_TYPE_BOOL);
244 assert(ir->type == ir->operands[0]->type);
251 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
252 assert(ir->type == ir->operands[0]->type);
256 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
260 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
264 assert(ir->operands[0]->type->base_type == GLSL_TYPE_INT);
268 assert(ir->operands[0]->type->base_type == GLSL_TYPE_FLOAT);
272 assert(ir->operands[
[all...]
H A Dlower_vector.cpp67 ir_rvalue *op = ir->operands[i];
98 op = ex->operands[0];
162 const ir_constant *const c = expr->operands[i]->as_constant();
198 if (expr->operands[i]->ir_type == ir_type_constant)
203 new(mem_ctx) ir_assignment(lhs, expr->operands[i], NULL, (1U << i));
/external/llvm/test/MC/ARM/
H A Dthumb2-ldrd.s11 @ CHECK: error: destination operands can't be identical
12 @ CHECK: error: destination operands can't be identical
13 @ CHECK: error: destination operands can't be identical
14 @ CHECK: error: destination operands can't be identical
15 @ CHECK-NOT: error: destination operands can't be identical
/external/llvm/utils/TableGen/
H A DX86DisassemblerShared.h20 operands[llvm::X86Disassembler::X86_MAX_OPERANDS]; member in struct:InstructionSpecifier
27 memset(operands, 0, sizeof(operands));
/external/llvm/test/MC/Mips/
H A Dmips_directives_bad.s4 .abicalls should have no operands
6 # CHECK-NEXT: .abicalls should have no operands
H A Dsym-expr.s3 # RUN: llvm-mc -triple=mipsel -show-inst-operands %s 2> %t0
/external/srec/srec/Semproc/include/
H A DSR_ExpressionEvaluator.h60 * @param operands array of strings holding operands to concatenate
61 * @param opCount number of operands
66 SREC_SEMPROC_API ESR_ReturnCode EE_concat(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen);
69 * Built-in function to support conditional expressions (with 3 operands only!!!)
71 * @param operands first op is the condition, second is the true val, third is the false val
72 * @param opCount number of operands
76 SREC_SEMPROC_API ESR_ReturnCode EE_conditional(LCHAR* name, LCHAR** operands, size_t opCount, void* data, LCHAR* resultBuf, size_t* resultLen);
81 * @param operands strings to interpret as integers and then add together
82 * @param opCount number of operands
[all...]
/external/chromium_org/third_party/ots/src/
H A Dcff.cc184 std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) {
198 operands->push_back(std::make_pair(static_cast<uint32_t>(0),
205 operands->push_back(std::make_pair(static_cast<uint32_t>(0),
244 std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) {
253 operands->push_back(std::make_pair((12U << 8) + op, DICT_OPERATOR));
263 std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) {
275 operands->push_back(std::make_pair(
286 operands->push_back(std::make_pair(
292 return ParseDictDataBcd(table, operands);
315 operands
182 ParseDictDataBcd( ots::Buffer *table, std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) argument
242 ParseDictDataEscapedOperator( ots::Buffer *table, std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) argument
261 ParseDictDataNumber( ots::Buffer *table, uint8_t b0, std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) argument
319 ParseDictDataReadNext( ots::Buffer *table, std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > *operands) argument
346 std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > operands; local
471 std::vector<std::pair<uint32_t, DICT_OPERAND_TYPE> > operands; local
[all...]
/external/llvm/test/MC/Mips/mips32r2/
H A Dinvalid.s2 # invalid set of operands or operand's restrictions not met).
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid.s2 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
/external/llvm/test/MC/Mips/mips64r2/
H A Dinvalid.s2 # invalid set of operands or operand's restrictions not met).
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid.s2 # the assembler (e.g. invalid set of operands or operand's restrictions not met).
/external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/
H A Dgen_x86_insn.py27 # NOTE: operands are arranged in NASM / Intel order (e.g. dest, src)
264 # opt="foo" must be set for one of the operands.
271 # Build operands string (C array initializer)
272 self.operands = kwargs.pop("operands")
273 for op in self.operands:
370 "%d" % len(self.operands),
611 # Sort by number of operands to shorten output
618 key=lambda x:len(x.operands), reverse=True):
619 num_operands = len(form.operands)
667 operands=[]) variable
676 operands=[]) variable
686 operands=[]) variable
694 operands=[]) variable
705 operands=[Operand(type="Mem", dest="EA")]) variable
716 operands=[Operand(type="Mem", relaxed=True, dest="EA")]) variable
729 operands=[Operand(type="Areg", size=sz, dest=None), variable
738 operands=[Operand(type="MemOffs", size=sz, relaxed=True, dest="EA"), variable
747 operands=[Operand(type="Areg", size=sz, dest=None), variable
755 operands=[Operand(type="MemOffs", size=sz, relaxed=True, dest="EA64"), variable
765 operands=[ variable
775 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
785 operands=[Operand(type="Areg", size=sz, dest="Spare"), variable
795 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
802 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA"), variable
809 operands=[ variable
815 operands=[Operand(type="SegReg", size=16, relaxed=True, dest="Spare"), variable
821 operands=[ variable
829 operands=[Operand(type="Reg", size=8, dest="Op0Add"), variable
836 operands=[Operand(type="Reg", size=sz, dest="Op0Add"), variable
843 operands=[Operand(type="Reg", size=64, dest="Op0Add"), variable
850 operands=[Operand(type="Reg", size=64, dest="Op0Add"), variable
859 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
866 operands=[Operand(type="RM", size=sz, dest="EA"), variable
875 operands=[Operand(type="CR4", size=32, dest="Spare"), variable
882 operands=[Operand(type="CRReg", size=32, dest="Spare"), variable
888 operands=[Operand(type="CRReg", size=32, dest="Spare"), variable
895 operands=[Operand(type="Reg", size=32, dest="EA"), variable
902 operands=[Operand(type="Reg", size=32, dest="EA"), variable
908 operands=[Operand(type="Reg", size=64, dest="EA"), variable
917 operands=[Operand(type="DRReg", size=32, dest="Spare"), variable
923 operands=[Operand(type="DRReg", size=32, dest="Spare"), variable
930 operands=[Operand(type="Reg", size=32, dest="EA"), variable
936 operands=[Operand(type="Reg", size=64, dest="EA"), variable
945 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
953 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
960 operands=[Operand(type="SIMDRM", size=64, relaxed=True, dest="EA"), variable
968 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
978 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
986 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
995 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
1003 operands=[Operand(type="SIMDRM", size=64, relaxed=True, dest="EA"), variable
1012 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
1025 operands=[Operand(type="Areg", size=8, dest=None), variable
1033 operands=[Operand(type="Areg", size=sz, dest=None), variable
1041 operands=[Operand(type="MemOffs", size=8, relaxed=True, dest="EA64"), variable
1049 operands=[Operand(type="MemOffs", size=sz, relaxed=True, variable
1058 operands=[Operand(type="Reg", size=64, dest="Op0Add"), variable
1072 operands=[Operand(type="Reg", size=16, dest="Spare"), variable
1080 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
1087 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
1095 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
1102 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
1125 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
1137 operands=[Operand(type="Reg", size="BITS", dest="Op0Add")]) variable
1143 operands=[Operand(type="Reg", size=16, dest="Op0Add")]) variable
1149 operands=[Operand(type="Reg", size=32, dest="Op0Add")]) variable
1155 operands=[Operand(type="Reg", size=64, dest="Op0Add")]) variable
1161 operands=[Operand(type="RM", size="BITS", dest="EA")]) variable
1168 operands=[Operand(type="RM", size=16, dest="EA")]) variable
1175 operands=[Operand(type="RM", size=32, dest="EA")]) variable
1182 operands=[Operand(type="RM", size=64, dest="EA")]) variable
1189 operands=[Operand(type="Imm", size=8, dest="SImm")]) variable
1195 operands=[Operand(type="Imm", size=8, relaxed=True, dest="SImm")]) variable
1203 operands=[Operand(type="Imm", size=32, relaxed=True, dest="SImm", variable
1211 operands=[Operand(type="Imm", size="BITS", relaxed=True, dest="Imm", variable
1220 operands=[Operand(type="Imm", size=16, relaxed=True, dest="Imm", variable
1228 operands=[Operand(type="Imm", size=32, relaxed=True, dest="Imm", variable
1238 operands=[Operand(type="Imm", size=16, dest="Imm")]) variable
1244 operands=[Operand(type="Imm", size=32, dest="Imm")]) variable
1251 operands=[Operand(type="Imm", size=32, dest="SImm")]) variable
1255 operands=[Operand(type="CS", dest=None)]) variable
1261 operands=[Operand(type="CS", size=16, dest=None)]) variable
1267 operands=[Operand(type="CS", size=32, dest=None)]) variable
1271 operands=[Operand(type="SS", dest=None)]) variable
1277 operands=[Operand(type="SS", size=16, dest=None)]) variable
1283 operands=[Operand(type="SS", size=32, dest=None)]) variable
1287 operands=[Operand(type="DS", dest=None)]) variable
1293 operands=[Operand(type="DS", size=16, dest=None)]) variable
1299 operands=[Operand(type="DS", size=32, dest=None)]) variable
1303 operands=[Operand(type="ES", dest=None)]) variable
1309 operands=[Operand(type="ES", size=16, dest=None)]) variable
1315 operands=[Operand(type="ES", size=32, dest=None)]) variable
1318 operands=[Operand(type="FS", dest=None)]) variable
1323 operands=[Operand(type="FS", size=16, dest=None)]) variable
1328 operands=[Operand(type="FS", size=32, dest=None)]) variable
1331 operands=[Operand(type="GS", dest=None)]) variable
1336 operands=[Operand(type="GS", size=16, dest=None)]) variable
1341 operands=[Operand(type="GS", size=32, dest=None)]) variable
1357 operands=[Operand(type="Reg", size="BITS", dest="Op0Add")]) variable
1363 operands=[Operand(type="Reg", size=16, dest="Op0Add")]) variable
1369 operands=[Operand(type="Reg", size=32, dest="Op0Add")]) variable
1375 operands=[Operand(type="Reg", size=64, dest="Op0Add")]) variable
1380 operands=[Operand(type="RM", size="BITS", dest="EA")]) variable
1386 operands=[Operand(type="RM", size=16, dest="EA")]) variable
1392 operands=[Operand(type="RM", size=32, dest="EA")]) variable
1398 operands=[Operand(type="RM", size=64, dest="EA")]) variable
1410 operands=[Operand(type="SS", dest=None)]) variable
1415 operands=[Operand(type="SS", size=16, dest=None)]) variable
1420 operands=[Operand(type="SS", size=32, dest=None)]) variable
1424 operands=[Operand(type="DS", dest=None)]) variable
1429 operands=[Operand(type="DS", size=16, dest=None)]) variable
1434 operands=[Operand(type="DS", size=32, dest=None)]) variable
1438 operands=[Operand(type="ES", dest=None)]) variable
1443 operands=[Operand(type="ES", size=16, dest=None)]) variable
1448 operands=[Operand(type="ES", size=32, dest=None)]) variable
1451 operands=[Operand(type="FS", dest=None)]) variable
1455 operands=[Operand(type="FS", size=16, dest=None)]) variable
1459 operands=[Operand(type="FS", size=32, dest=None)]) variable
1462 operands=[Operand(type="GS", dest=None)]) variable
1466 operands=[Operand(type="GS", size=16, dest=None)]) variable
1470 operands=[Operand(type="GS", size=32, dest=None)]) variable
1486 operands=[Operand(type="RM", size=8, relaxed=True, dest="EA"), variable
1491 operands=[Operand(type="Reg", size=8, dest="Spare"), variable
1508 operands=[Operand(type="Areg", size=16, dest=None), variable
1514 operands=[Operand(type="Reg", size=16, dest="Op0Add"), variable
1520 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA"), variable
1526 operands=[Operand(type="Reg", size=16, dest="Spare"), variable
1541 operands=[Operand(type="Areg", size=32, dest="EA"), variable
1547 operands=[Operand(type="Areg", size=32, dest=None), variable
1553 operands=[Operand(type="Reg", size=32, dest="Op0Add"), variable
1559 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
1565 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
1573 operands=[Operand(type="Areg", size=64, dest=None), variable
1579 operands=[Operand(type="Areg", size=64, dest=None), variable
1585 operands=[Operand(type="Reg", size=64, dest="Op0Add"), variable
1591 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
1597 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
1608 operands=[Operand(type="Areg", size=8, dest=None), variable
1615 operands=[Operand(type="Areg", size=sz, dest=None), variable
1620 operands=[Operand(type="Areg", size=8, dest=None), variable
1627 operands=[Operand(type="Areg", size=sz, dest=None), variable
1634 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
1641 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
1646 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1652 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1659 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1666 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm"), variable
1673 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm"), variable
1678 operands=[Operand(type="Dreg", size=16, dest=None), variable
1685 operands=[Operand(type="Dreg", size=16, dest=None), variable
1692 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
1698 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
1705 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
1710 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1716 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1723 operands=[Operand(type="Dreg", size=16, dest=None)]) variable
1735 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
1750 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
1763 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
1805 operands=[Operand(type="Areg", size=8, dest=None), variable
1814 operands=[Operand(type="Areg", size=sz, dest=None), variable
1823 operands=[Operand(type="RM", size=8, dest="EA"), variable
1830 operands=[Operand(type="RM", size=8, relaxed=True, dest="EA"), variable
1839 operands=[Operand(type="RM", size=16, dest="EA"), variable
1848 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA"), variable
1857 operands=[ variable
1867 operands=[Operand(type="RM", size=32, dest="EA"), variable
1879 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
1888 operands=[ variable
1899 operands=[Operand(type="RM", size=64, dest="EA"), variable
1908 operands=[ variable
1918 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
1926 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
1946 operands=[Operand(type="RM", size=8, dest="EA")]) variable
1954 operands=[Operand(type="Reg", size=sz, dest="Op0Add")]) variable
1961 operands=[Operand(type="RM", size=sz, dest="EA")]) variable
1968 operands=[Operand(type="RM", size=64, dest="EA")]) variable
1983 operands=[Operand(type="RM", size=sz, dest="EA")]) variable
2000 operands=[Operand(type="RM", size=sz, dest="EA")]) variable
2009 operands=[Operand(type="Areg", size=sz, dest=None), variable
2023 operands=[Operand(type="Areg", size=sz, dest=None), variable
2031 operands=[Operand(type="RM", size=sz, dest="EA"), variable
2037 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
2045 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
2052 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
2063 operands=[]) variable
2067 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
2105 operands=[Operand(type="RM", size=sz, dest="EA")]) variable
2112 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
2120 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
2129 operands=[Operand(type="Reg", size=sz, dest="SpareEA"), variable
2138 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
2149 operands=[Operand(type="Reg", size=sz, dest="SpareEA"), variable
2165 operands=[Operand(type="RM", size=sz, dest="EA"), variable
2173 operands=[Operand(type="RM", size=sz, dest="EA"), variable
2182 operands=[Operand(type="RM", size=sz, dest="EA"), variable
2193 operands=[Operand(type="RM", size=sz, dest="EA")]) variable
2214 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
2223 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
2235 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
2249 operands=[Operand(type="ImmNotSegOff", dest="JmpRel")]) variable
2254 operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")]) variable
2260 operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")]) variable
2266 operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")]) variable
2272 operands=[Operand(type="Imm", size=16, tmod="Near", dest="JmpRel")]) variable
2277 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2283 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2287 operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")]) variable
2295 operands=[Operand(type="RM", size=16, dest="EA")]) variable
2303 operands=[Operand(type="RM", size=32, dest="EA")]) variable
2311 operands=[Operand(type="RM", size=64, dest="EA")]) variable
2317 operands=[Operand(type="Reg", size="BITS", dest="EA")]) variable
2322 operands=[Operand(type="Mem", dest="EA")]) variable
2329 operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")]) variable
2336 operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")]) variable
2343 operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")]) variable
2349 operands=[Operand(type="Mem", tmod="Near", dest="EA")]) variable
2358 operands=[Operand(type="Mem", size=sz, tmod="Far", dest="EA")]) variable
2363 operands=[Operand(type="Mem", tmod="Far", dest="EA")]) variable
2372 operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")]) variable
2377 operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")]) variable
2386 operands=[Operand(type="Imm", size=sz, dest="JmpFar")]) variable
2391 operands=[Operand(type="Imm", dest="JmpFar")]) variable
2403 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2410 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2420 operands=[Operand(type="ImmNotSegOff", dest="JmpRel")]) variable
2425 operands=[Operand(type="ImmNotSegOff", size=16, dest="JmpRel")]) variable
2431 operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")]) variable
2437 operands=[Operand(type="ImmNotSegOff", size=32, dest="JmpRel")]) variable
2442 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")]) variable
2447 operands=[Operand(type="Imm", size=16, tmod="Near", dest="JmpRel")]) variable
2453 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2459 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2463 operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")]) variable
2472 operands=[Operand(type="RM", size=16, dest="EA")]) variable
2480 operands=[Operand(type="RM", size=32, dest="EA")]) variable
2488 operands=[Operand(type="RM", size=64, dest="EA")]) variable
2494 operands=[Operand(type="Reg", size="BITS", dest="EA")]) variable
2499 operands=[Operand(type="Mem", dest="EA")]) variable
2506 operands=[Operand(type="RM", size=16, tmod="Near", dest="EA")]) variable
2514 operands=[Operand(type="RM", size=32, tmod="Near", dest="EA")]) variable
2521 operands=[Operand(type="RM", size=64, tmod="Near", dest="EA")]) variable
2527 operands=[Operand(type="Mem", tmod="Near", dest="EA")]) variable
2535 operands=[Operand(type="Mem", size=sz, tmod="Far", dest="EA")]) variable
2539 operands=[Operand(type="Mem", tmod="Far", dest="EA")]) variable
2547 operands=[Operand(type="Imm", size=sz, tmod="Far", dest="JmpFar")]) variable
2551 operands=[Operand(type="Imm", tmod="Far", dest="JmpFar")]) variable
2560 operands=[Operand(type="Imm", size=sz, dest="JmpFar")]) variable
2565 operands=[Operand(type="Imm", dest="JmpFar")]) variable
2577 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2584 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2602 operands=[Operand(type="Mem", size=sz, relaxed=True, dest="EA")]) variable
2607 operands=[Operand(type="Mem", size="BITS", relaxed=True, dest="EA")]) variable
2619 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2626 operands=[Operand(type="Imm", size=16, relaxed=True, dest="JmpFar"), variable
2639 operands=[]) variable
2644 operands=[Operand(type="Imm", size=16, relaxed=True, dest="Imm")]) variable
2649 operands=[]) variable
2654 operands=[Operand(type="Imm", size=16, relaxed=True, dest="Imm")]) variable
2660 operands=[]) variable
2667 operands=[Operand(type="Imm", size=16, relaxed=True, dest="Imm")]) variable
2690 operands=[ variable
2701 operands=[ variable
2712 operands=[ variable
2734 operands=[Operand(type="Imm", dest="JmpRel")]) variable
2738 operands=[Operand(type="Imm", size=16, dest="JmpRel")]) variable
2743 operands=[Operand(type="Imm", size=32, dest="JmpRel")]) variable
2748 operands=[Operand(type="Imm", size=32, dest="JmpRel")]) variable
2754 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")]) variable
2761 operands=[Operand(type="Imm", size=16, tmod="Near", dest="JmpRel")]) variable
2768 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2775 operands=[Operand(type="Imm", size=32, tmod="Near", dest="JmpRel")]) variable
2781 operands=[Operand(type="Imm", tmod="Near", dest="JmpRel")]) variable
2820 operands=[Operand(type="Imm", dest="JmpRel")]) variable
2825 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")]) variable
2836 operands=[Operand(type="Imm", dest="JmpRel")]) variable
2840 operands=[Operand(type="Imm", dest="JmpRel"), variable
2845 operands=[Operand(type="Imm", dest="JmpRel"), variable
2850 operands=[Operand(type="Imm", dest="JmpRel"), variable
2857 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")]) variable
2863 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel"), variable
2880 operands=[Operand(type="Imm", dest="JmpRel")]) variable
2887 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel")]) variable
2894 operands=[Operand(type="Imm", dest="JmpRel"), variable
2902 operands=[Operand(type="Imm", tmod="Short", dest="JmpRel"), variable
2920 operands=[Operand(type="RM", size=8, relaxed=True, dest="EA")]) variable
2965 operands=[]) variable
2995 operands=[]) variable
3039 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
3049 operands=[Operand(type="RM", size=sz, dest="EA"), variable
3066 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
3077 operands=[Operand(type="Imm", size=8, relaxed=True, dest="Imm")]) variable
3098 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
3114 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
3121 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
3132 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA"), variable
3154 operands=[Operand(type="Reg", size=sz, dest="EA")]) variable
3160 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA")]) variable
3170 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA")]) variable
3186 operands=[Operand(type="Mem", size=sz, relaxed=True, dest="EA")]) variable
3195 operands=[Operand(type="Reg", size=sz, dest="EA")]) variable
3261 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3266 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3271 operands=[Operand(type="Mem", size=80, dest="EA")]) variable
3275 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3284 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3290 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3295 operands=[Operand(type="Mem", size=80, dest="EA")]) variable
3299 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3311 operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA")]) variable
3322 operands=[Operand(type="Mem", size=16, dest="EA")]) variable
3329 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3336 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3344 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA")]) variable
3354 operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA")]) variable
3369 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3375 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3379 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3389 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3393 operands=[Operand(type="ST0", size=80, dest=None), variable
3398 operands=[Operand(type="Reg", size=80, dest="Op1Add"), variable
3403 operands=[]) variable
3416 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3423 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3428 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3436 operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA")]) variable
3443 operands=[]) variable
3449 operands=[Operand(type="ST0", size=80, dest=None), variable
3462 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3467 operands=[Operand(type="ST0", size=80, dest=None), variable
3482 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3489 operands=[Operand(type="Mem", size=64, dest="EA")]) variable
3494 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3499 operands=[Operand(type="ST0", size=80, dest=None), variable
3505 operands=[Operand(type="Reg", size=80, tmod="To", dest="Op1Add")]) variable
3511 operands=[Operand(type="Reg", size=80, dest="Op1Add"), variable
3518 operands=[Operand(type="Reg", size=80, dest="Op1Add"), variable
3532 operands=[]) variable
3537 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3542 operands=[Operand(type="Reg", size=80, dest="Op1Add"), variable
3565 operands=[Operand(type="Mem", size=16, dest="EA")]) variable
3572 operands=[Operand(type="Mem", size=32, dest="EA")]) variable
3593 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA")]) variable
3603 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA")]) variable
3612 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA")]) variable
3617 operands=[Operand(type="Areg", size=16, dest=None)]) variable
3626 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA")]) variable
3631 operands=[Operand(type="Areg", size=16, dest=None)]) variable
3639 operands=[Operand(type="Reg", size=80, dest="Op1Add")]) variable
3652 operands=[Operand(type="Reg", size=32, dest="Op1Add")]) variable
3657 operands=[Operand(type="Reg", size=64, dest="Op1Add")]) variable
3668 operands=[Operand(type="RM", size=sz, relaxed=True, dest="EA"), variable
3698 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA")]) variable
3725 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
3763 operands=[Operand(type="ST0", size=80, dest=None), variable
3787 operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA"), variable
3794 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
3803 operands=[Operand(type="Mem", size=8, relaxed=True, dest="EA")]) variable
3823 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
3829 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
3834 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
3840 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
3846 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
3853 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
3859 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
3866 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
3880 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
3887 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
3893 operands=[Operand(type="SIMDRM", size=64, relaxed=True, dest="EA"), variable
3900 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
3909 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
3916 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
3924 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
3931 operands=[Operand(type="SIMDRM", size=64, relaxed=True, dest="EA"), variable
3939 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
3948 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
3955 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4041 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4048 operands=[Operand(type="SIMDReg", size=64, dest="EA"), variable
4055 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4063 operands=[Operand(type="SIMDReg", size=128, dest="EA"), variable
4083 operands=[Operand(type="SIMDReg", size=sz, dest="SpareVEX"), variable
4092 operands=[Operand(type="SIMDReg", size=sz, dest="EAVEX"), variable
4100 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
4110 operands=[Operand(type="SIMDReg", size=sz, dest="VEX"), variable
4157 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4165 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4174 operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"), variable
4182 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4192 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4200 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4209 operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"), variable
4217 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4227 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4235 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4275 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4283 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4293 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4302 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4314 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4320 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4330 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4343 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4352 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4362 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4372 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4382 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4393 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4405 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4412 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4420 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4429 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4460 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4467 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4475 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4484 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4491 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4499 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4508 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4564 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4576 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4584 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4593 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4601 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4610 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4623 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4631 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4640 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4650 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4663 operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA")]) variable
4673 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4686 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4694 operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), variable
4701 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4708 operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), variable
4715 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
4722 operands=[Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"), variable
4734 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4741 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4755 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4762 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
4770 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4785 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4794 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4803 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4813 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4824 operands=[Operand(type="Mem", size=128, relaxed=True, dest="EA"), variable
4832 operands=[Operand(type="Mem", size=256, relaxed=True, dest="EA"), variable
4841 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
4851 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4858 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4865 operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA"), variable
4872 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
4884 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4893 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
4902 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4912 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
4921 operands=[Operand(type="Mem", size=16, relaxed=True, dest="EA"), variable
4930 operands=[Operand(type="Reg", size=32, dest="EA"), variable
4939 operands=[Operand(type="Reg", size=64, dest="EA"), variable
4951 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4961 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4969 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
4978 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4989 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
4998 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5007 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5019 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5029 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5042 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5050 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5058 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5067 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5077 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5087 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5096 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
5110 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5117 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5125 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5134 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5201 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5208 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5216 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5225 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5251 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5259 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5269 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5278 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5289 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
5299 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5310 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5318 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5326 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5335 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5367 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5374 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5381 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
5388 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5406 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5415 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5431 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
5439 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
5449 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
5457 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
5466 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA")]) variable
5476 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA")]) variable
5514 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5529 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
5538 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5549 operands=[Operand(type="SIMDReg", size=128, dest="EAVEX"), variable
5557 operands=[Operand(type="SIMDReg", size=128, dest="VEX"), variable
5567 operands=[Operand(type="SIMDReg", size=256, dest="EAVEX"), variable
5576 operands=[Operand(type="SIMDReg", size=256, dest="VEX"), variable
5615 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5622 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5637 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
5644 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5652 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5661 operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"), variable
5669 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5707 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
5715 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5731 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5739 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5781 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5790 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5800 operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"), variable
5809 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5820 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5829 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5839 operands=[Operand(type="SIMDReg", size=256, dest="SpareVEX"), variable
5848 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5859 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5868 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5879 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5887 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
5896 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5906 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5939 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5946 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5961 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5971 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
5986 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
5996 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6010 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
6019 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
6029 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
6038 operands=[Operand(type="Reg", size=64, dest="EA"), variable
6050 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6058 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6066 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6075 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6088 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6095 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6106 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6125 operands=[Operand(type="Mem", size=8, relaxed=True, dest="EA"), variable
6133 operands=[Operand(type="Reg", size=32, dest="EA"), variable
6142 operands=[Operand(type="Reg", size=64, dest="EA"), variable
6154 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
6167 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
6179 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6187 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6195 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6204 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6217 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6225 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6239 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6248 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
6262 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6269 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6277 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6285 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6325 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
6342 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6349 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
6359 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6366 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6373 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
6381 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6389 operands=[Operand(type="RM", size=64, relaxed=True, dest="EA"), variable
6401 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6409 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6428 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6437 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6446 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6459 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6467 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6475 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6488 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6496 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6510 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6518 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6531 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6539 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6547 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6561 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6573 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6587 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6595 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6604 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6612 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6636 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6643 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6650 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6657 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6667 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6674 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6684 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6695 operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), variable
6707 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6719 operands=[]) variable
6729 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6737 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6745 operands=[Operand(type="SIMDRM", size=128, relaxed=True, dest="EA"), variable
6753 operands=[Operand(type="SIMDRM", size=256, relaxed=True, dest="EA"), variable
6766 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6775 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6784 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
6793 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6805 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6827 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6842 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6854 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
6869 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6879 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6892 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6902 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6915 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6925 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6938 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6948 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6961 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6973 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
6995 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
7007 operands=[Operand(type="SIMDRM", size=sz, relaxed=True, dest="EA"), variable
7021 operands=[Operand(type="SIMDReg", size=sz, dest="Spare"), variable
7036 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7046 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7059 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7069 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7082 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7092 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7105 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7115 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7133 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7143 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7155 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7165 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7176 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7187 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7198 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7209 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7236 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
7244 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7264 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7276 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7293 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
7302 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7315 operands=[Operand(type="SIMDReg", size=128, dest="SpareVEX"), variable
7323 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7342 operands=[Operand(type="Reg", size=16, dest="EA")]) variable
7349 operands=[Operand(type="Reg", size=32, dest="EA")]) variable
7355 operands=[Operand(type="Reg", size=64, dest="EA")]) variable
7366 operands=[Operand(type="Reg", size=32, dest="EA")]) variable
7374 operands=[Operand(type="Reg", size=64, dest="EA")]) variable
7419 operands=operands1) variable
7427 operands=operands2) variable
7435 operands=operands3) variable
7443 operands=operands4) variable
7456 operands=[Operand(type="SIMDReg", size=128, dest="EA"), variable
7463 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7472 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7480 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7489 operands=[Operand(type="Mem", size=64, relaxed=True, dest="EA"), variable
7498 operands=[Operand(type="Mem", size=32, relaxed=True, dest="EA"), variable
7512 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7519 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7528 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7534 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7542 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7548 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7557 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7566 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7575 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7584 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7596 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7604 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7629 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7655 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7678 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7687 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7699 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7708 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7716 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7728 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7737 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7755 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7766 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7777 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7788 operands=[Operand(type="SIMDReg", size=256, dest="Spare"), variable
7814 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7825 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7836 operands=[Operand(type="SIMDReg", size=128, dest="Spare"), variable
7870 operands=[Operand(type="Mem", relaxed=True, dest="EA")]) variable
7882 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
7888 operands=[Operand(type="Mem", size=sz, relaxed=True, dest="EA"), variable
7907 operands=[Operand(type="Reg", size=sz, dest="VEX"), variable
7926 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
7941 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
7961 operands=[Operand(type="Reg", size=sz, dest="Spare"), variable
7989 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
7997 operands=[Operand(type="Reg", size=64, dest="Spare"), variable
8013 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
8064 operands=[Operand(type="Mem", size=128, relaxed=True, dest="EA")]) variable
8079 operands=[]) variable
8083 operands=[Operand(type="MemrAX", dest="AdSizeEA"), variable
8091 operands=[]) variable
8095 operands=[Operand(type="MemEAX", dest=None)]) variable
8103 operands=[]) variable
8108 operands=[Operand(type="MemrAX", dest="AdSizeEA")]) variable
8123 operands=[]) variable
8144 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
8162 operands=[Operand(type="SIMDReg", size=64, dest="Spare"), variable
8178 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA")]) variable
8186 operands=[Operand(type="SegReg", size=16, relaxed=True, dest="Spare"), variable
8195 operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA")]) variable
8205 operands=[Operand(type="Mem", size=80, relaxed=True, dest="EA"), variable
8224 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA"), variable
8230 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
8238 operands=[Operand(type="RM", size=8, relaxed=True, dest="EA"), variable
8244 operands=[Operand(type="RM", size=16, relaxed=True, dest="EA"), variable
8250 operands=[Operand(type="RM", size=32, relaxed=True, dest="EA"), variable
8255 operands=[Operand(type="Reg", size=8, dest="Spare"), variable
8261 operands=[Operand(type="Reg", size=16, dest="Spare"), variable
8267 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
8276 operands=[Operand(type="Reg", size=16, dest="Spare"), variable
8282 operands=[Operand(type="Reg", size=32, dest="Spare"), variable
[all...]
/external/dexmaker/src/dx/java/com/android/dx/ssa/
H A DPhiInsn.java41 * {@code non-null;} operands of the instruction; built up by
44 private final ArrayList<Operand> operands = new ArrayList<Operand>(); field in class:PhiInsn
50 * Constructs a new phi insn with no operands.
82 * Updates the TypeBearers of all the sources (phi operands) to be
86 * Note that local association of operands are preserved in this step.
91 for (Operand o : operands) {
130 operands.add(new Operand(registerSpec, predBlock.getIndex(),
144 for (Operand o : operands) {
150 operands.removeAll(operandsToRemove);
164 return operands
[all...]
/external/llvm/include/llvm/IR/
H A DOperandTraits.h12 // the operands in the most efficient manner.
38 static unsigned operands(const User*) { function in struct:llvm::FixedNumOperandTraits
47 /// OptionalOperandTraits - when the number of operands may change at runtime.
52 static unsigned operands(const User *U) { function in struct:llvm::OptionalOperandTraits
73 static unsigned operands(const User *U) { function in struct:llvm::VariadicOperandTraits
100 static unsigned operands(const User *U) { function in struct:llvm::HungoffOperandTraits
137 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
143 assert(i_nocapture < OperandTraits<CLASS>::operands(this) \
148 return OperandTraits<CLASS>::operands(this); \
/external/antlr/antlr-3.4/tool/src/main/java/org/antlr/analysis/
H A DSemanticContext.java55 * July 7, 2006: TJP altered OR to be set of operands. the Binary tree
304 protected final Set<SemanticContext> operands = new HashSet<SemanticContext>(); field in class:SemanticContext.CommutativePredicate
310 operands.addAll(predicate.operands);
312 operands.add(a);
317 operands.addAll(predicate.operands);
319 operands.add(b);
329 operands.addAll(predicate.operands);
[all...]
/external/lldb/examples/python/
H A Dgdb_disassemble.py18 print "<%s + %-4u> 0x%x %8s %s ; %s" % (name, inst_offset, inst_addr, inst.mnemonic, inst.operands, comment)
20 print "<%s + %-4u> 0x%x %8s %s" % (name, inst_offset, inst_addr, inst.mnemonic, inst.operands)
/external/llvm/test/MC/PowerPC/
H A Dppc64-errors.s7 # Register operands
17 # TLS register operands
27 # Signed 16-bit immediate operands
37 # Unsigned 16-bit immediate operands
47 # Signed 16-bit immediate operands (extended range for addis)
55 # D-Form memory operands

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