Searched refs:subnr (Results 1 - 12 of 12) sorted by relevance
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i965/ |
H A D | brw_eu_debug.c | 63 hwreg.subnr == 0 && 77 printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4); 86 hwreg.subnr / type_sz(hwreg.type),
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H A D | brw_eu.h | 78 GLuint subnr:5; /* :1 in align16 */ member in struct:brw_reg 178 * \param subnr register sub number 188 GLuint subnr, 207 reg.subnr = subnr * type_sz(type); 217 * set swizzle and writemask to W, as the lower bits of subnr will 232 GLuint subnr ) 236 subnr, 248 GLuint subnr ) 252 subnr, 186 brw_reg( GLuint file, GLuint nr, GLuint subnr, GLuint type, GLuint vstride, GLuint width, GLuint hstride, GLuint swizzle, GLuint writemask ) argument [all...] |
H A D | brw_wm_debug.c | 75 if ((hw_reg.nr&1) || hw_reg.subnr) { 76 printf("->%d.%d", (hw_reg.nr&1), hw_reg.subnr);
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H A D | brw_eu_emit.c | 121 insn->bits1.da1.dest_subreg_nr = dest.subnr; 127 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; 134 insn->bits1.ia1.dest_subreg_nr = dest.subnr; 264 insn->bits2.da1.src0_subreg_nr = reg.subnr; 268 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16; 273 insn->bits2.ia1.src0_subreg_nr = reg.subnr; 346 insn->bits3.da1.src1_subreg_nr = reg.subnr; 350 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16; 758 return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0); 760 return reg.subnr / [all...] |
H A D | brw_gs_emit.c | 448 vertex_slot.subnr = (slot % 2) * 16;
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H A D | brw_vs_emit.c | 1079 const_reg.subnr = 0; 1174 GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * reg_size; 1212 GLuint byte_offset = base.nr * 32 + base.subnr; 1759 prev_insn->bits1.da16.dest_subreg_nr == val.subnr / 16 &&
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_eu_debug.c | 63 hwreg.subnr == 0 && 77 printf("scl%d.%d", hwreg.nr, hwreg.subnr / 4); 86 hwreg.subnr / type_sz(hwreg.type),
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H A D | brw_eu.h | 78 GLuint subnr:5; /* :1 in align16 */ member in struct:brw_reg 178 * \param subnr register sub number 188 GLuint subnr, 207 reg.subnr = subnr * type_sz(type); 217 * set swizzle and writemask to W, as the lower bits of subnr will 232 GLuint subnr ) 236 subnr, 248 GLuint subnr ) 252 subnr, 186 brw_reg( GLuint file, GLuint nr, GLuint subnr, GLuint type, GLuint vstride, GLuint width, GLuint hstride, GLuint swizzle, GLuint writemask ) argument [all...] |
H A D | brw_wm_debug.c | 75 if ((hw_reg.nr&1) || hw_reg.subnr) { 76 printf("->%d.%d", (hw_reg.nr&1), hw_reg.subnr);
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H A D | brw_eu_emit.c | 121 insn->bits1.da1.dest_subreg_nr = dest.subnr; 127 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16; 134 insn->bits1.ia1.dest_subreg_nr = dest.subnr; 264 insn->bits2.da1.src0_subreg_nr = reg.subnr; 268 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16; 273 insn->bits2.ia1.src0_subreg_nr = reg.subnr; 346 insn->bits3.da1.src1_subreg_nr = reg.subnr; 350 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16; 758 return reg.subnr / 4 + BRW_GET_SWZ(reg.dw1.bits.swizzle, 0); 760 return reg.subnr / [all...] |
H A D | brw_gs_emit.c | 448 vertex_slot.subnr = (slot % 2) * 16;
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H A D | brw_vs_emit.c | 1079 const_reg.subnr = 0; 1174 GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * reg_size; 1212 GLuint byte_offset = base.nr * 32 + base.subnr; 1759 prev_insn->bits1.da16.dest_subreg_nr == val.subnr / 16 &&
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