Searched refs:xreg (Results 1 - 18 of 18) sorted by relevance

/external/vixl/examples/
H A Dswap4.cc74 simulator.xreg(0), simulator.xreg(1),
75 simulator.xreg(2), simulator.xreg(3));
84 simulator.xreg(0), simulator.xreg(1),
85 simulator.xreg(2), simulator.xreg(3));
H A Dabs.cc63 printf("abs(%ld) = %ld\n", input_value, simulator.xreg(0));
H A Dgetting-started.cc57 printf("x0 = %" PRIx64 "\n", simulator.xreg(0));
H A Dfactorial.cc73 printf("factorial(%ld) = %ld\n", input_val, simulator.xreg(0));
H A Dcheck-bounds.cc69 simulator->xreg(0) ? "is" : "is not",
H A Dfactorial-rec.cc75 printf("factorial(%ld) = %ld\n", input_val, simulator.xreg(0));
/external/vixl/test/examples/
H A Dtest-examples.cc87 saved_xregs[0] = simulator.xreg(19); \
88 saved_xregs[1] = simulator.xreg(20); \
89 saved_xregs[2] = simulator.xreg(21); \
90 saved_xregs[3] = simulator.xreg(22); \
91 saved_xregs[4] = simulator.xreg(23); \
92 saved_xregs[5] = simulator.xreg(24); \
93 saved_xregs[6] = simulator.xreg(25); \
94 saved_xregs[7] = simulator.xreg(26); \
95 saved_xregs[8] = simulator.xreg(27); \
96 saved_xregs[9] = simulator.xreg(2
[all...]
/external/chromium_org/v8/src/arm64/
H A Dsimulator-arm64.cc169 return xreg(0);
238 saved_registers[i] = xreg(register_list.PopLowestIndex().code());
254 CHECK_EQ(saved_registers[i], xreg(register_list.PopLowestIndex().code()));
585 xreg(0), xreg(1), xreg(2), xreg(3),
586 xreg(4), xreg(5), xreg(
[all...]
H A Dsimulator-arm64.h346 int64_t xreg(unsigned code, Reg31Mode r31mode = Reg31IsZeroRegister) const {
403 int64_t sp() { return xreg(31, Reg31IsStackPointer); }
404 int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); }
406 return xreg(kFramePointerRegCode, Reg31IsStackPointer);
/external/vixl/src/a64/
H A Dsimulator-a64.cc433 (last_regs[i] != xreg(i, Reg31IsStackPointer))) {
439 xreg(i, Reg31IsStackPointer),
443 last_regs[i] = xreg(i, Reg31IsStackPointer);
543 Instruction* target = Instruction::Cast(xreg(instr->Rn()));
559 bool bit_zero = ((xreg(instr->Rt()) >> bit_pos) & 1) == 0;
577 case CBZ_x: take_branch = (xreg(rt) == 0); break;
579 case CBNZ_x: take_branch = (xreg(rt) != 0); break;
767 int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext,
789 case STR_x: MemoryWrite(address, xreg(srcdst), num_bytes); break;
890 MemoryWrite64(address, xreg(r
[all...]
H A Dsimulator-a64.h238 inline int64_t xreg(unsigned code,
H A Ddebugger-a64.cc928 uint64_t reg_value = debugger->xreg(value().code(), Reg31IsStackPointer);
/external/chromium_org/v8/test/cctest/
H A Dtest-utils-arm64.cc101 int64_t result_x = core->xreg(reg.code());
116 uint64_t result = core->xreg(reg.code());
150 int64_t expected = core->xreg(reg0.code());
151 int64_t result = core->xreg(reg1.code());
192 if (a->xreg(i) != b->xreg(i)) {
194 i, a->xreg(i), b->xreg(i));
H A Dtest-utils-arm64.h66 inline int64_t xreg(unsigned code) const { function in class:RegisterDump
H A Dtest-assembler-arm64.cc92 // CHECK_EQUAL_64(0x1234, core.xreg(0) & 0xffff);
1899 CHECK_EQUAL_64(core.xreg(3) + kInstructionSize, x0);
/external/vixl/test/
H A Dtest-utils-a64.cc101 int64_t result_x = core->xreg(reg.code());
116 uint64_t result = core->xreg(reg.code());
150 int64_t expected = core->xreg(reg0.code());
151 int64_t result = core->xreg(reg1.code());
192 if (a->xreg(i) != b->xreg(i)) {
194 i, a->xreg(i), b->xreg(i));
H A Dtest-utils-a64.h69 inline int64_t xreg(unsigned code) const { function in class:vixl::RegisterDump
H A Dtest-assembler-a64.cc1728 ASSERT_EQUAL_64(core.xreg(3) + kInstructionSize, x0);

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