/external/smack/src/org/xbill/DNS/ |
H A D | Opcode.java | 11 public final class Opcode { class 30 private static Mnemonic opcodes = new Mnemonic("DNS Opcode", 46 Opcode() {} method in class:Opcode 48 /** Converts a numeric Opcode into a String */ 54 /** Converts a String representation of an Opcode into its numeric value */
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/external/smali/dexlib2/src/main/java/org/jf/dexlib2/ |
H A D | Opcode.java | 34 public enum Opcode enum 36 NOP((short)0x00, "nop", ReferenceType.NONE, Format.Format10x, Opcode.CAN_CONTINUE), 37 MOVE((short)0x01, "move", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER), 38 MOVE_FROM16((short)0x02, "move/from16", ReferenceType.NONE, Format.Format22x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER), 39 MOVE_16((short)0x03, "move/16", ReferenceType.NONE, Format.Format32x, Opcode.CAN_CONTINUE | Opcode.SETS_REGISTER), 40 MOVE_WIDE((short)0x04, "move-wide", ReferenceType.NONE, Format.Format12x, Opcode.CAN_CONTINUE | Opcode 331 Opcode(short opcodeValue, String opcodeName, int referenceType, Format format) { method in class:Opcode 335 Opcode(short opcodeValue, String opcodeName, int referenceType, Format format, int flags) { method in class:Opcode 339 Opcode(short opcodeValue, String opcodeName, int referenceType, Format format, int flags, short jumboOpcodeValue) { method in class:Opcode 343 Opcode(short opcodeValue, String opcodeName, int apiConstraints, int referenceType, Format format) { method in class:Opcode 347 Opcode(short opcodeValue, String opcodeName, int apiConstraints, int referenceType, Format format, int flags) { method in class:Opcode 351 Opcode(short opcodeValue, String opcodeName, int apiConstraints, int referenceType, Format format, int flags, method in class:Opcode [all...] |
/external/robolectric/lib/main/ |
H A D | javassist-3.14.0-GA.jar | META-INF/ META-INF/MANIFEST.MF javassist/ javassist/bytecode/ javassist/bytecode/analysis/ javassist/bytecode/annotation/ javassist/ ... |
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | asm-xml-3.3.jar | META-INF/MANIFEST.MF org/objectweb/asm/xml/ASMContentHandler$AnnotationDefaultRule.class " package org.objectweb ... |
H A D | findbugs.jar | META-INF/ META-INF/MANIFEST.MF default.xsl edu/ edu/umd/ edu/umd/cs/ edu/ ... |
/external/mesa3d/src/mesa/program/ |
H A D | prog_instruction.c | 144 gl_inst_opcode Opcode; member in struct:instruction_info 152 * \note Opcode should equal array index! 260 ASSERT(opcode == InstInfo[opcode].Opcode); 261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode); 273 ASSERT(opcode == InstInfo[opcode].Opcode); 274 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
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H A D | prog_instruction.h | 340 gl_inst_opcode Opcode; member in struct:prog_instruction
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
H A D | radeon_opcodes.h | 243 rc_opcode Opcode; member in struct:rc_opcode_info 272 assert(rc_opcodes[opcode].Opcode == opcode);
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H A D | radeon_program.h | 65 rc_presubtract_op Opcode; member in struct:rc_presub_instruction 82 * Opcode of this instruction, according to \ref rc_opcode enums. 84 unsigned int Opcode:8; member in struct:rc_sub_instruction
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H A D | radeon_program_alu.c | 44 rc_opcode Opcode, struct rc_sub_instruction * base, 53 fpi->U.I.Opcode = Opcode; 61 rc_opcode Opcode, struct rc_sub_instruction * base, 71 fpi->U.I.Opcode = Opcode; 80 rc_opcode Opcode, struct rc_sub_instruction * base, 91 fpi->U.I.Opcode = Opcode; 199 const struct rc_opcode_info *info = rc_get_opcode_info(inst->U.I.Opcode); 42 emit1( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg) argument 59 emit2( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1) argument 78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument [all...] |
H A D | radeon_program_pair.h | 72 unsigned int Opcode:8; member in struct:rc_pair_sub_instruction
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
H A D | rc_test_helpers.c | 297 struct match_info Opcode; member in struct:inst_tokens 334 tokens.Opcode.String = inst_str + matches[1].rm_so; 335 tokens.Opcode.Length = match_length(matches, 1); 347 if (strncmp(tokens.Opcode.String, info->Name, tokens.Opcode.Length)) { 350 inst->U.I.Opcode = info->Opcode;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600ExpandSpecialInstrs.cpp | 133 unsigned Opcode; local 137 Opcode = AMDGPU::CUBE_r600_real; 140 Opcode = AMDGPU::CUBE_eg_real; 144 Opcode = 0; 148 Opcode = MI.getOpcode(); 151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
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H A D | R600InstrInfo.cpp | 95 bool R600InstrInfo::isMov(unsigned Opcode) const 99 switch(Opcode) { 111 bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const 113 switch (Opcode) { 122 bool R600InstrInfo::isReductionOp(unsigned Opcode) const 124 switch(Opcode) { 132 bool R600InstrInfo::isCubeOp(unsigned Opcode) const 134 switch(Opcode) { 152 isPredicateSetter(unsigned Opcode) argument 154 switch (Opcode) { [all...] |
/external/mesa3d/src/gallium/include/pipe/ |
H A D | p_shader_tokens.h | 441 * Opcode is the operation code to execute. A given operation defines the 458 unsigned Opcode : 8; /* TGSI_OPCODE_ */ member in struct:tgsi_instruction
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/external/mesa3d/src/mesa/main/ |
H A D | atifragshader.h | 53 GLenum Opcode[2]; member in struct:atifs_instruction 62 GLenum Opcode; member in struct:atifs_setupinst
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H A D | dlist.c | 105 struct gl_list_instruction Opcode[MAX_DLIST_EXT_OPCODES]; member in struct:gl_list_extensions 607 ctx->ListExt->Opcode[i].Destroy(ctx, &node[1]); 608 step = ctx->ListExt->Opcode[i].Size; 619 ctx->ListExt->Opcode[i].Execute(ctx, &node[1]); 620 step = ctx->ListExt->Opcode[i].Size; 631 ctx->ListExt->Opcode[i].Print(ctx, &node[1]); 632 step = ctx->ListExt->Opcode[i].Size; 1057 ctx->ListExt->Opcode[i].Size = 1059 ctx->ListExt->Opcode[i].Execute = execute; 1060 ctx->ListExt->Opcode[ [all...] |
/external/llvm/utils/TableGen/ |
H A D | DAGISelMatcher.h | 480 const SDNodeInfo &Opcode; member in class:llvm::CheckOpcodeMatcher 483 : Matcher(CheckOpcode), Opcode(opcode) {} 485 const SDNodeInfo &getOpcode() const { return Opcode; }
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H A D | X86RecognizableInstr.h | 46 uint8_t Opcode; member in class:llvm::X86Disassembler::RecognizableInstr
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/external/llvm/tools/llvm-readobj/ |
H A D | ARMEHABIPrinter.h | 96 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 97 SW.startLine() << format("0x%02X ; vsp = vsp + %u\n", Opcode, 98 ((Opcode & 0x3f) << 2) + 4); 101 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 102 SW.startLine() << format("0x%02X ; vsp = vsp - %u\n", Opcode, 103 ((Opcode & 0x3f) << 2) + 4); 119 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 120 SW.startLine() << format("0x%02X ; reserved (ARM MOVrr)\n", Opcode); 123 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 124 SW.startLine() << format("0x%02X ; reserved (WiMMX MOVrr)\n", Opcode); 127 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 131 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 137 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 143 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 160 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 186 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 190 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 237 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 241 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 247 uint8_t Opcode = Opcodes[OI++ ^ 3]; local 253 uint8_t Opcode = Opcodes[OI++ ^ 3]; local [all...] |
/external/llvm/lib/Transforms/Vectorize/ |
H A D | SLPVectorizer.cpp | 152 ///\returns Opcode that can be clubbed with \p Op to create an alternate 169 ///\returns bool representing if Opcode \p Op can be part 184 unsigned Opcode = I0->getOpcode(); local 185 unsigned AltOpcode = getAltOpcode(Opcode); 188 if (!I || I->getOpcode() != ((i & 1) ? AltOpcode : Opcode)) 200 unsigned Opcode = I0->getOpcode(); local 203 if (!I || Opcode != I->getOpcode()) { 204 if (canCombineAsAltInst(Opcode) && i == 1) 209 return Opcode; 665 unsigned Opcode local 1157 unsigned Opcode = getSameOpcode(VL); local 1623 unsigned Opcode = getSameOpcode(E->Scalars); local 2800 createBinOp(IRBuilder< &Builder, unsigned Opcode, Value *L, Value *R, const Twine &Name = �) argument [all...] |
/external/llvm/bindings/ocaml/llvm/ |
H A D | llvm.ml | 141 module Opcode = struct module 276 | Instruction of Opcode.t 442 external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode" 953 external instr_opcode : llvalue -> Opcode.t = "llvm_instr_get_opcode"
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H A D | llvm.mli | 197 module Opcode : sig module 343 | Instruction of Opcode.t 763 (** [constexpr_opcode v] returns an [Opcode.t] corresponding to constexpr 764 value [v], or [Opcode.Invalid] if [v] is not a constexpr. *) 765 val constexpr_opcode : llvalue -> Opcode.t 1682 (** [inst_opcode i] returns the [Opcode.t] corresponding to instruction [i], 1683 or [Opcode.Invalid] if [i] is not an instruction. *) 1684 val instr_opcode : llvalue -> Opcode.t
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/external/llvm/examples/Kaleidoscope/Chapter6/ |
H A D | toy.cpp | 130 char Opcode; member in class:__anon25454::UnaryExprAST 134 : Opcode(opcode), Operand(operand) {} 564 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
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/external/llvm/examples/Kaleidoscope/Chapter7/ |
H A D | toy.cpp | 135 char Opcode; member in class:__anon25455::UnaryExprAST 139 : Opcode(opcode), Operand(operand) {} 642 Function *F = TheModule->getFunction(std::string("unary")+Opcode);
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