/external/valgrind/main/cachegrind/tests/ |
H A D | chdir.stderr.exp | 6 I1 miss rate: 7 LLi miss rate: 12 D1 miss rate: 13 LLd miss rate: 17 LL miss rate:
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H A D | dlclose.stderr.exp | 6 I1 miss rate: 7 LLi miss rate: 12 D1 miss rate: 13 LLd miss rate: 17 LL miss rate:
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H A D | notpower2.stderr.exp | 6 I1 miss rate: 7 LLi miss rate: 12 D1 miss rate: 13 LLd miss rate: 17 LL miss rate:
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H A D | wrap5.stderr.exp | 6 I1 miss rate: 7 LLi miss rate: 12 D1 miss rate: 13 LLd miss rate: 17 LL miss rate:
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/external/valgrind/main/cachegrind/tests/x86/ |
H A D | fpu-28-108.stderr.exp | 6 I1 miss rate: 7 LLi miss rate: 12 D1 miss rate: 13 LLd miss rate: 17 LL miss rate:
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/external/valgrind/main/callgrind/ |
H A D | main.c | 138 Bool miss; local 145 miss = 1 & do_cond_branch_predict(CLG_(bb_base) + ii->instr_offset, taken); 159 if (miss) { 168 Bool miss; local 175 miss = 1 & do_ind_branch_predict(CLG_(bb_base) + ii->instr_offset, actual_dst); 189 if (miss) {
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/external/valgrind/main/callgrind/tests/ |
H A D | notpower2-hwpref.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | notpower2-use.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | notpower2-wb.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | notpower2.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | simwork-both.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | simwork-cache.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | simwork1.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | simwork2.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | simwork3.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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H A D | threads-use.stderr.exp | 9 I1 miss rate: 10 LLi miss rate: 15 D1 miss rate: 16 LLd miss rate: 20 LL miss rate:
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/external/skia/experimental/Intersection/ |
H A D | EdgeWalkerPolygons_Mismatches.cpp | 1591 const misMatch& miss = misMatches[index]; local 1592 int ax = miss.a & 0x03; 1593 int ay = miss.a >> 2; 1594 int bx = miss.b & 0x03; 1595 int by = miss.b >> 2; 1596 int cx = miss.c & 0x03; 1597 int cy = miss.c >> 2; 1598 int dx = miss.d & 0x03; 1599 int dy = miss.d >> 2; 1600 int ex = miss [all...] |
/external/oprofile/events/i386/atom/ |
H A D | unit_masks | 44 0x02 misses Icache miss 98 0x02 l2_miss Retired loads that miss the L2 cache (precise event) 99 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)
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/external/oprofile/events/i386/nehalem/ |
H A D | events | 27 event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB
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H A D | unit_masks | 25 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB 29 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB 82 0x02 ld_miss Counts the number of loads that miss the L2 cache 85 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache 88 0x20 ifetch_miss Counts number of instruction fetches that miss the L2 cache 93 0xAA miss Counts all L2 misses for both code and data 128 0x41 miss This event counts each cache miss condition for references to the last level cache 166 0x02 miss Counts number of hardware prefetch requests that miss th [all...] |
/external/oprofile/events/i386/westmere/ |
H A D | events | 17 event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event) 33 event:0x2e counters:0,1,2,3 um:longest_lat_cache minimum:100000 name:LONGEST_LAT_CACHE : Longest latency cache miss 46 event:0x85 counters:0,1,2,3 um:itlb_misses minimum:200000 name:ITLB_MISSES : ITLB miss 70 event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
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H A D | unit_masks | 65 0x02 walk_completed DTLB load miss page walks complete 66 0x04 walk_cycles DTLB load miss page walk cycles 68 0x20 pde_miss DTLB load miss caused by low part of address 69 0x80 large_walk_completed DTLB load miss large page walks 72 0x02 walk_completed DTLB miss page walks 73 0x04 walk_cycles DTLB miss page walk cycles 76 0x80 large_walk_completed DTLB miss large page walks 105 0x01 any ITLB miss 106 0x02 walk_completed ITLB miss page walks 107 0x04 walk_cycles ITLB miss pag [all...] |
/external/oprofile/events/mips/1004K/ |
H A D | events | 31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache 60 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss 62 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline 95 event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention 96 event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned 111 event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache 134 event:0x424 counters:1 um:zero minimum:500 name:INTERVENTION_MISS_STALLS : 36-1 Cache coherence intervention processing stall cycles due to an earlier miss 139 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss 141 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline 172 event:0x43d counters:1 um:zero minimum:500 name:SELF_INTERVENTION_COUNT : 61-1 Self intervention requests on miss detectio [all...] |
/external/oprofile/events/mips/24K/ |
H A D | events | 31 event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache 55 event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss 57 event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline 95 event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache 119 event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss 121 event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
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/external/oprofile/events/mips/25K/ |
H A D | events | 52 event:0x1a counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss 57 event:0x1b counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss 64 event:0x1e counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss
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