Searched refs:Ctx (Results 1 - 25 of 421) sorted by path

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/external/chromium_org/third_party/cython/src/Cython/Compiler/
H A DParsing.py30 class Ctx(object): class in inherits:object
47 ctx = Ctx()
1710 body_ctx = Ctx()
1933 def p_suite(s, ctx=Ctx()):
2331 def p_c_declarator(s, ctx = Ctx(), empty = 0, is_type = 0, cmethod_flag = 0,
2515 def p_c_arg_list(s, ctx = Ctx(), in_pyfunc = 0, cmethod_flag = 0,
2730 body_ctx = Ctx()
2819 doc, suite = p_suite_with_docstring(s, Ctx(level='function'))
2917 doc, body = p_suite_with_docstring(s, Ctx(level='function'))
2969 doc, body = p_suite_with_docstring(s, Ctx(leve
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H A DTreeFragment.py68 ctx = Parsing.Ctx(allow_struct_enum_decorator=allow_struct_enum_decorator)
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCTargetDesc.cpp75 MCContext &Ctx) {
77 return createSIMCCodeEmitter(MCII, STI, Ctx);
79 return createR600MCCodeEmitter(MCII, STI, Ctx);
84 MCContext &Ctx, MCAsmBackend &MAB,
89 return createPureStreamer(Ctx, MAB, _OS, _Emitter);
73 createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
83 createMCStreamer(const Target &T, StringRef TT, MCContext &Ctx, MCAsmBackend &MAB, raw_ostream &_OS, MCCodeEmitter *_Emitter, bool RelaxAll, bool NoExecStack) argument
H A DAMDGPUMCTargetDesc.h33 MCContext &Ctx);
37 MCContext &Ctx);
H A DR600MCCodeEmitter.cpp44 MCContext &Ctx; member in class:__anon13910::R600MCCodeEmitter
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
146 MCContext &Ctx) {
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
144 createR600MCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
H A DSIMCCodeEmitter.cpp64 MCContext &Ctx; member in class:__anon13912::SIMCCodeEmitter
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
127 MCContext &Ctx) {
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
125 createSIMCCodeEmitter(const MCInstrInfo &MCII, const MCSubtargetInfo &STI, MCContext &Ctx) argument
/external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/i915/
H A Di830_context.h119 GLuint Ctx[I830_CTX_SETUP_SIZE]; member in struct:i830_hw_state
H A Di830_state.c64 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_TEST_MASK;
65 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_TEST_MASK |
67 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_REF_VALUE_MASK |
69 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_REF_VALUE |
85 i830->state.Ctx[I830_CTXREG_STATE4] &= ~MODE4_ENABLE_STENCIL_WRITE_MASK;
86 i830->state.Ctx[I830_CTXREG_STATE4] |= (ENABLE_STENCIL_WRITE_MASK |
193 i830->state.Ctx[I830_CTXREG_STENCILTST] &= ~(STENCIL_OPS_MASK);
194 i830->state.Ctx[I830_CTXREG_STENCILTST] |= (ENABLE_STENCIL_PARMS |
214 i830->state.Ctx[I830_CTXREG_STATE2] &= ~ALPHA_TEST_REF_MASK;
215 i830->state.Ctx[I830_CTXREG_STATE
[all...]
H A Di830_vtbl.c178 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
179 v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
180 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
197 i830->state.Ctx[I830_CTXREG_VF] = v0;
198 i830->state.Ctx[I830_CTXREG_VF2] = v2;
199 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
243 int vft0 = i830->state.Ctx[I830_CTXREG_VF];
244 int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
394 sz += sizeof(state->Ctx);
489 emit(intel, state->Ctx, sizeo
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H A Di915_context.h219 GLuint Ctx[I915_CTX_SETUP_SIZE]; member in struct:i915_hw_state
H A Di915_fragprog.c1348 GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
1419 if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
1420 s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
1439 i915->state.Ctx[I915_CTXREG_LIS2] = s2;
1440 i915->state.Ctx[I915_CTXREG_LIS4] = s4;
H A Di915_state.c97 GLuint dw = i915->state.Ctx[reg]; \
100 dirty |= dw != i915->state.Ctx[reg]; \
101 i915->state.Ctx[reg] = dw; \
187 dw = i915->state.Ctx[I915_CTXREG_LIS6];
191 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
192 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
209 dw0 = i915->state.Ctx[I915_CTXREG_LIS5];
210 dw1 = i915->state.Ctx[I915_CTXREG_LIS6];
226 if (dw0 != i915->state.Ctx[I915_CTXREG_LIS5] ||
227 dw1 != i915->state.Ctx[I915_CTXREG_LIS
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H A Di915_vtbl.c106 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
107 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
258 sz += sizeof(state->Ctx);
377 emit(intel, state->Ctx, sizeof(state->Ctx));
692 uint32_t dw = i915->state.Ctx[I915_CTXREG_LIS6];
697 if (dw != i915->state.Ctx[I915_CTXREG_LIS6]) {
699 i915->state.Ctx[I915_CTXREG_LIS6] = dw;
H A Dintel_tris.c300 OUT_BATCH((i830->state.Ctx[I830_CTXREG_VF] & VFT0_TEX_COUNT_MASK) >>
302 (i830->state.Ctx[I830_CTXREG_VF2] << 16) |
/external/clang/include/clang/ARCMigrate/
H A DARCMT.h109 virtual void start(ASTContext &Ctx) { } argument
/external/clang/include/clang/AST/
H A DAPValue.h197 void printPretty(raw_ostream &OS, ASTContext &Ctx, QualType Ty) const;
198 std::string getAsString(ASTContext &Ctx, QualType Ty) const;
H A DASTConsumer.h69 virtual void HandleTranslationUnit(ASTContext &Ctx) {} argument
H A DASTContext.h2314 static inline Selector GetNullarySelector(StringRef name, ASTContext& Ctx) { argument
2315 IdentifierInfo* II = &Ctx.Idents.get(name);
2316 return Ctx.Selectors.getSelector(0, &II);
2320 static inline Selector GetUnarySelector(StringRef name, ASTContext& Ctx) { argument
2321 IdentifierInfo* II = &Ctx.Idents.get(name);
2322 return Ctx.Selectors.getSelector(1, &II);
2414 const clang::ASTContext &Ctx, T Value) {
2418 if (auto *Source = Ctx.getExternalSource())
2419 return new (Ctx) LazyData(Source, Value);
2413 makeValue( const clang::ASTContext &Ctx, T Value) argument
H A DDecl.h75 ASTContext &Ctx; member in class:clang::TranslationUnitDecl
84 Ctx(ctx), AnonymousNamespace(nullptr) {}
86 ASTContext &getASTContext() const { return Ctx; }
2213 unsigned getBitWidthValue(const ASTContext &Ctx) const;
3395 void setBlockMangling(unsigned Number, Decl *Ctx) {
3397 ManglingContextDecl = Ctx;
H A DDeclBase.h299 /// \param Ctx The context in which we will allocate memory.
302 void *operator new(std::size_t Size, const ASTContext &Ctx, unsigned ID,
306 void *operator new(std::size_t Size, const ASTContext &Ctx,
969 void setAttrsImpl(const AttrVec& Attrs, ASTContext &Ctx);
971 ASTContext &Ctx);
H A DDeclObjC.h49 void set(void *const* InList, unsigned Elts, ASTContext &Ctx);
60 void set(T* const* InList, unsigned Elts, ASTContext &Ctx) { argument
61 ObjCListBase::set(reinterpret_cast<void*const*>(InList), Elts, Ctx); local
89 const SourceLocation *Locs, ASTContext &Ctx);
2341 IdentifierInfo *getDefaultSynthIvarName(ASTContext &Ctx) const;
H A DDeclarationName.h341 const ASTContext &Ctx; member in class:clang::DeclarationNameTable
H A DExpr.h235 ASTContext &Ctx) const;
268 LValueClassification ClassifyLValue(ASTContext &Ctx) const;
297 isModifiableLvalue(ASTContext &Ctx, SourceLocation *Loc = nullptr) const;
374 Classification Classify(ASTContext &Ctx) const {
375 return ClassifyImpl(Ctx, nullptr);
386 Classification ClassifyModifiable(ASTContext &Ctx, SourceLocation &Loc) const{ argument
387 return ClassifyImpl(Ctx, &Loc);
425 Classification ClassifyImpl(ASTContext &Ctx, SourceLocation *Loc) const;
485 bool isIntegerConstantExpr(llvm::APSInt &Result, const ASTContext &Ctx,
488 bool isIntegerConstantExpr(const ASTContext &Ctx,
3484 getShuffleMaskIdx(const ASTContext &Ctx, unsigned N) const argument
[all...]
H A DExprCXX.h1663 bool shouldNullCheckAllocation(const ASTContext &Ctx) const;
H A DExternalASTSource.h394 static ValueType makeValue(const ASTContext &Ctx, T Value);
397 explicit LazyGenerationalUpdatePtr(const ASTContext &Ctx, T Value = T()) argument
398 : Value(makeValue(Ctx, Value)) {}

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