gen_common.cc revision b48819db07f9a0992a72173380c24249d7fc648a
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "verifier/method_verifier.h" 23 24namespace art { 25 26/* 27 * This source files contains "gen" codegen routines that should 28 * be applicable to most targets. Only mid-level support utilities 29 * and "op" calls may be used here. 30 */ 31 32/* 33 * Generate a kPseudoBarrier marker to indicate the boundary of special 34 * blocks. 35 */ 36void Mir2Lir::GenBarrier() { 37 LIR* barrier = NewLIR0(kPseudoBarrier); 38 /* Mark all resources as being clobbered */ 39 DCHECK(!barrier->flags.use_def_invalid); 40 barrier->u.m.def_mask = ENCODE_ALL; 41} 42 43// FIXME: need to do some work to split out targets with 44// condition codes and those without 45LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) { 46 DCHECK_NE(cu_->instruction_set, kMips); 47 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_); 48 LIR* branch = OpCondBranch(c_code, tgt); 49 // Remember branch target - will process later 50 throw_launchpads_.Insert(tgt); 51 return branch; 52} 53 54LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) { 55 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg, imm_val); 56 LIR* branch; 57 if (c_code == kCondAl) { 58 branch = OpUnconditionalBranch(tgt); 59 } else { 60 branch = OpCmpImmBranch(c_code, reg, imm_val, tgt); 61 } 62 // Remember branch target - will process later 63 throw_launchpads_.Insert(tgt); 64 return branch; 65} 66 67/* Perform null-check on a register. */ 68LIR* Mir2Lir::GenNullCheck(int s_reg, int m_reg, int opt_flags) { 69 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && 70 opt_flags & MIR_IGNORE_NULL_CHECK) { 71 return NULL; 72 } 73 return GenImmedCheck(kCondEq, m_reg, 0, kThrowNullPointer); 74} 75 76/* Perform check on two registers */ 77LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 78 ThrowKind kind) { 79 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2); 80 LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt); 81 // Remember branch target - will process later 82 throw_launchpads_.Insert(tgt); 83 return branch; 84} 85 86void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 87 RegLocation rl_src2, LIR* taken, 88 LIR* fall_through) { 89 ConditionCode cond; 90 switch (opcode) { 91 case Instruction::IF_EQ: 92 cond = kCondEq; 93 break; 94 case Instruction::IF_NE: 95 cond = kCondNe; 96 break; 97 case Instruction::IF_LT: 98 cond = kCondLt; 99 break; 100 case Instruction::IF_GE: 101 cond = kCondGe; 102 break; 103 case Instruction::IF_GT: 104 cond = kCondGt; 105 break; 106 case Instruction::IF_LE: 107 cond = kCondLe; 108 break; 109 default: 110 cond = static_cast<ConditionCode>(0); 111 LOG(FATAL) << "Unexpected opcode " << opcode; 112 } 113 114 // Normalize such that if either operand is constant, src2 will be constant 115 if (rl_src1.is_const) { 116 RegLocation rl_temp = rl_src1; 117 rl_src1 = rl_src2; 118 rl_src2 = rl_temp; 119 cond = FlipComparisonOrder(cond); 120 } 121 122 rl_src1 = LoadValue(rl_src1, kCoreReg); 123 // Is this really an immediate comparison? 124 if (rl_src2.is_const) { 125 // If it's already live in a register or not easily materialized, just keep going 126 RegLocation rl_temp = UpdateLoc(rl_src2); 127 if ((rl_temp.location == kLocDalvikFrame) && 128 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 129 // OK - convert this to a compare immediate and branch 130 OpCmpImmBranch(cond, rl_src1.low_reg, mir_graph_->ConstantValue(rl_src2), taken); 131 return; 132 } 133 } 134 rl_src2 = LoadValue(rl_src2, kCoreReg); 135 OpCmpBranch(cond, rl_src1.low_reg, rl_src2.low_reg, taken); 136} 137 138void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 139 LIR* fall_through) { 140 ConditionCode cond; 141 rl_src = LoadValue(rl_src, kCoreReg); 142 switch (opcode) { 143 case Instruction::IF_EQZ: 144 cond = kCondEq; 145 break; 146 case Instruction::IF_NEZ: 147 cond = kCondNe; 148 break; 149 case Instruction::IF_LTZ: 150 cond = kCondLt; 151 break; 152 case Instruction::IF_GEZ: 153 cond = kCondGe; 154 break; 155 case Instruction::IF_GTZ: 156 cond = kCondGt; 157 break; 158 case Instruction::IF_LEZ: 159 cond = kCondLe; 160 break; 161 default: 162 cond = static_cast<ConditionCode>(0); 163 LOG(FATAL) << "Unexpected opcode " << opcode; 164 } 165 OpCmpImmBranch(cond, rl_src.low_reg, 0, taken); 166} 167 168void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 169 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 170 if (rl_src.location == kLocPhysReg) { 171 OpRegCopy(rl_result.low_reg, rl_src.low_reg); 172 } else { 173 LoadValueDirect(rl_src, rl_result.low_reg); 174 } 175 OpRegRegImm(kOpAsr, rl_result.high_reg, rl_result.low_reg, 31); 176 StoreValueWide(rl_dest, rl_result); 177} 178 179void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 180 RegLocation rl_src) { 181 rl_src = LoadValue(rl_src, kCoreReg); 182 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 183 OpKind op = kOpInvalid; 184 switch (opcode) { 185 case Instruction::INT_TO_BYTE: 186 op = kOp2Byte; 187 break; 188 case Instruction::INT_TO_SHORT: 189 op = kOp2Short; 190 break; 191 case Instruction::INT_TO_CHAR: 192 op = kOp2Char; 193 break; 194 default: 195 LOG(ERROR) << "Bad int conversion type"; 196 } 197 OpRegReg(op, rl_result.low_reg, rl_src.low_reg); 198 StoreValue(rl_dest, rl_result); 199} 200 201/* 202 * Let helper function take care of everything. Will call 203 * Array::AllocFromCode(type_idx, method, count); 204 * Note: AllocFromCode will handle checks for errNegativeArraySize. 205 */ 206void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 207 RegLocation rl_src) { 208 FlushAllRegs(); /* Everything to home location */ 209 ThreadOffset func_offset(-1); 210 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file, 211 type_idx)) { 212 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArray); 213 } else { 214 func_offset= QUICK_ENTRYPOINT_OFFSET(pAllocArrayWithAccessCheck); 215 } 216 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 217 RegLocation rl_result = GetReturn(false); 218 StoreValue(rl_dest, rl_result); 219} 220 221/* 222 * Similar to GenNewArray, but with post-allocation initialization. 223 * Verifier guarantees we're dealing with an array class. Current 224 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 225 * Current code also throws internal unimp if not 'L', '[' or 'I'. 226 */ 227void Mir2Lir::GenFilledNewArray(CallInfo* info) { 228 int elems = info->num_arg_words; 229 int type_idx = info->index; 230 FlushAllRegs(); /* Everything to home location */ 231 ThreadOffset func_offset(-1); 232 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file, 233 type_idx)) { 234 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArray); 235 } else { 236 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArrayWithAccessCheck); 237 } 238 CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 239 FreeTemp(TargetReg(kArg2)); 240 FreeTemp(TargetReg(kArg1)); 241 /* 242 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 243 * return region. Because AllocFromCode placed the new array 244 * in kRet0, we'll just lock it into place. When debugger support is 245 * added, it may be necessary to additionally copy all return 246 * values to a home location in thread-local storage 247 */ 248 LockTemp(TargetReg(kRet0)); 249 250 // TODO: use the correct component size, currently all supported types 251 // share array alignment with ints (see comment at head of function) 252 size_t component_size = sizeof(int32_t); 253 254 // Having a range of 0 is legal 255 if (info->is_range && (elems > 0)) { 256 /* 257 * Bit of ugliness here. We're going generate a mem copy loop 258 * on the register range, but it is possible that some regs 259 * in the range have been promoted. This is unlikely, but 260 * before generating the copy, we'll just force a flush 261 * of any regs in the source range that have been promoted to 262 * home location. 263 */ 264 for (int i = 0; i < elems; i++) { 265 RegLocation loc = UpdateLoc(info->args[i]); 266 if (loc.location == kLocPhysReg) { 267 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), 268 loc.low_reg, kWord); 269 } 270 } 271 /* 272 * TUNING note: generated code here could be much improved, but 273 * this is an uncommon operation and isn't especially performance 274 * critical. 275 */ 276 int r_src = AllocTemp(); 277 int r_dst = AllocTemp(); 278 int r_idx = AllocTemp(); 279 int r_val = INVALID_REG; 280 switch (cu_->instruction_set) { 281 case kThumb2: 282 r_val = TargetReg(kLr); 283 break; 284 case kX86: 285 FreeTemp(TargetReg(kRet0)); 286 r_val = AllocTemp(); 287 break; 288 case kMips: 289 r_val = AllocTemp(); 290 break; 291 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 292 } 293 // Set up source pointer 294 RegLocation rl_first = info->args[0]; 295 OpRegRegImm(kOpAdd, r_src, TargetReg(kSp), SRegOffset(rl_first.s_reg_low)); 296 // Set up the target pointer 297 OpRegRegImm(kOpAdd, r_dst, TargetReg(kRet0), 298 mirror::Array::DataOffset(component_size).Int32Value()); 299 // Set up the loop counter (known to be > 0) 300 LoadConstant(r_idx, elems - 1); 301 // Generate the copy loop. Going backwards for convenience 302 LIR* target = NewLIR0(kPseudoTargetLabel); 303 // Copy next element 304 LoadBaseIndexed(r_src, r_idx, r_val, 2, kWord); 305 StoreBaseIndexed(r_dst, r_idx, r_val, 2, kWord); 306 FreeTemp(r_val); 307 OpDecAndBranch(kCondGe, r_idx, target); 308 if (cu_->instruction_set == kX86) { 309 // Restore the target pointer 310 OpRegRegImm(kOpAdd, TargetReg(kRet0), r_dst, 311 -mirror::Array::DataOffset(component_size).Int32Value()); 312 } 313 } else if (!info->is_range) { 314 // TUNING: interleave 315 for (int i = 0; i < elems; i++) { 316 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 317 StoreBaseDisp(TargetReg(kRet0), 318 mirror::Array::DataOffset(component_size).Int32Value() + 319 i * 4, rl_arg.low_reg, kWord); 320 // If the LoadValue caused a temp to be allocated, free it 321 if (IsTemp(rl_arg.low_reg)) { 322 FreeTemp(rl_arg.low_reg); 323 } 324 } 325 } 326 if (info->result.location != kLocInvalid) { 327 StoreValue(info->result, GetReturn(false /* not fp */)); 328 } 329} 330 331void Mir2Lir::GenSput(uint32_t field_idx, RegLocation rl_src, bool is_long_or_double, 332 bool is_object) { 333 int field_offset; 334 int ssb_index; 335 bool is_volatile; 336 bool is_referrers_class; 337 bool fast_path = cu_->compiler_driver->ComputeStaticFieldInfo( 338 field_idx, mir_graph_->GetCurrentDexCompilationUnit(), true, 339 &field_offset, &ssb_index, &is_referrers_class, &is_volatile); 340 if (fast_path && !SLOW_FIELD_PATH) { 341 DCHECK_GE(field_offset, 0); 342 int rBase; 343 if (is_referrers_class) { 344 // Fast path, static storage base is this method's class 345 RegLocation rl_method = LoadCurrMethod(); 346 rBase = AllocTemp(); 347 LoadWordDisp(rl_method.low_reg, 348 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), rBase); 349 if (IsTemp(rl_method.low_reg)) { 350 FreeTemp(rl_method.low_reg); 351 } 352 } else { 353 // Medium path, static storage base in a different class which requires checks that the other 354 // class is initialized. 355 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 356 DCHECK_GE(ssb_index, 0); 357 // May do runtime call so everything to home locations. 358 FlushAllRegs(); 359 // Using fixed register to sync with possible call to runtime support. 360 int r_method = TargetReg(kArg1); 361 LockTemp(r_method); 362 LoadCurrMethodDirect(r_method); 363 rBase = TargetReg(kArg0); 364 LockTemp(rBase); 365 LoadWordDisp(r_method, 366 mirror::ArtMethod::DexCacheInitializedStaticStorageOffset().Int32Value(), 367 rBase); 368 LoadWordDisp(rBase, 369 mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 370 sizeof(int32_t*) * ssb_index, rBase); 371 // rBase now points at appropriate static storage base (Class*) 372 // or NULL if not initialized. Check for NULL and call helper if NULL. 373 // TUNING: fast path should fall through 374 LIR* branch_over = OpCmpImmBranch(kCondNe, rBase, 0, NULL); 375 LoadConstant(TargetReg(kArg0), ssb_index); 376 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage), ssb_index, true); 377 if (cu_->instruction_set == kMips) { 378 // For Arm, kRet0 = kArg0 = rBase, for Mips, we need to copy 379 OpRegCopy(rBase, TargetReg(kRet0)); 380 } 381 LIR* skip_target = NewLIR0(kPseudoTargetLabel); 382 branch_over->target = skip_target; 383 FreeTemp(r_method); 384 } 385 // rBase now holds static storage base 386 if (is_long_or_double) { 387 rl_src = LoadValueWide(rl_src, kAnyReg); 388 } else { 389 rl_src = LoadValue(rl_src, kAnyReg); 390 } 391 if (is_volatile) { 392 GenMemBarrier(kStoreStore); 393 } 394 if (is_long_or_double) { 395 StoreBaseDispWide(rBase, field_offset, rl_src.low_reg, 396 rl_src.high_reg); 397 } else { 398 StoreWordDisp(rBase, field_offset, rl_src.low_reg); 399 } 400 if (is_volatile) { 401 GenMemBarrier(kStoreLoad); 402 } 403 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 404 MarkGCCard(rl_src.low_reg, rBase); 405 } 406 FreeTemp(rBase); 407 } else { 408 FlushAllRegs(); // Everything to home locations 409 ThreadOffset setter_offset = 410 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Static) 411 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjStatic) 412 : QUICK_ENTRYPOINT_OFFSET(pSet32Static)); 413 CallRuntimeHelperImmRegLocation(setter_offset, field_idx, rl_src, true); 414 } 415} 416 417void Mir2Lir::GenSget(uint32_t field_idx, RegLocation rl_dest, 418 bool is_long_or_double, bool is_object) { 419 int field_offset; 420 int ssb_index; 421 bool is_volatile; 422 bool is_referrers_class; 423 bool fast_path = cu_->compiler_driver->ComputeStaticFieldInfo( 424 field_idx, mir_graph_->GetCurrentDexCompilationUnit(), false, 425 &field_offset, &ssb_index, &is_referrers_class, &is_volatile); 426 if (fast_path && !SLOW_FIELD_PATH) { 427 DCHECK_GE(field_offset, 0); 428 int rBase; 429 if (is_referrers_class) { 430 // Fast path, static storage base is this method's class 431 RegLocation rl_method = LoadCurrMethod(); 432 rBase = AllocTemp(); 433 LoadWordDisp(rl_method.low_reg, 434 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), rBase); 435 } else { 436 // Medium path, static storage base in a different class which requires checks that the other 437 // class is initialized 438 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 439 DCHECK_GE(ssb_index, 0); 440 // May do runtime call so everything to home locations. 441 FlushAllRegs(); 442 // Using fixed register to sync with possible call to runtime support. 443 int r_method = TargetReg(kArg1); 444 LockTemp(r_method); 445 LoadCurrMethodDirect(r_method); 446 rBase = TargetReg(kArg0); 447 LockTemp(rBase); 448 LoadWordDisp(r_method, 449 mirror::ArtMethod::DexCacheInitializedStaticStorageOffset().Int32Value(), 450 rBase); 451 LoadWordDisp(rBase, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 452 sizeof(int32_t*) * ssb_index, rBase); 453 // rBase now points at appropriate static storage base (Class*) 454 // or NULL if not initialized. Check for NULL and call helper if NULL. 455 // TUNING: fast path should fall through 456 LIR* branch_over = OpCmpImmBranch(kCondNe, rBase, 0, NULL); 457 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage), ssb_index, true); 458 if (cu_->instruction_set == kMips) { 459 // For Arm, kRet0 = kArg0 = rBase, for Mips, we need to copy 460 OpRegCopy(rBase, TargetReg(kRet0)); 461 } 462 LIR* skip_target = NewLIR0(kPseudoTargetLabel); 463 branch_over->target = skip_target; 464 FreeTemp(r_method); 465 } 466 // rBase now holds static storage base 467 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 468 if (is_volatile) { 469 GenMemBarrier(kLoadLoad); 470 } 471 if (is_long_or_double) { 472 LoadBaseDispWide(rBase, field_offset, rl_result.low_reg, 473 rl_result.high_reg, INVALID_SREG); 474 } else { 475 LoadWordDisp(rBase, field_offset, rl_result.low_reg); 476 } 477 FreeTemp(rBase); 478 if (is_long_or_double) { 479 StoreValueWide(rl_dest, rl_result); 480 } else { 481 StoreValue(rl_dest, rl_result); 482 } 483 } else { 484 FlushAllRegs(); // Everything to home locations 485 ThreadOffset getterOffset = 486 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Static) 487 :(is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjStatic) 488 : QUICK_ENTRYPOINT_OFFSET(pGet32Static)); 489 CallRuntimeHelperImm(getterOffset, field_idx, true); 490 if (is_long_or_double) { 491 RegLocation rl_result = GetReturnWide(rl_dest.fp); 492 StoreValueWide(rl_dest, rl_result); 493 } else { 494 RegLocation rl_result = GetReturn(rl_dest.fp); 495 StoreValue(rl_dest, rl_result); 496 } 497 } 498} 499 500void Mir2Lir::HandleSuspendLaunchPads() { 501 int num_elems = suspend_launchpads_.Size(); 502 ThreadOffset helper_offset = QUICK_ENTRYPOINT_OFFSET(pTestSuspend); 503 for (int i = 0; i < num_elems; i++) { 504 ResetRegPool(); 505 ResetDefTracking(); 506 LIR* lab = suspend_launchpads_.Get(i); 507 LIR* resume_lab = reinterpret_cast<LIR*>(lab->operands[0]); 508 current_dalvik_offset_ = lab->operands[1]; 509 AppendLIR(lab); 510 int r_tgt = CallHelperSetup(helper_offset); 511 CallHelper(r_tgt, helper_offset, true /* MarkSafepointPC */); 512 OpUnconditionalBranch(resume_lab); 513 } 514} 515 516void Mir2Lir::HandleIntrinsicLaunchPads() { 517 int num_elems = intrinsic_launchpads_.Size(); 518 for (int i = 0; i < num_elems; i++) { 519 ResetRegPool(); 520 ResetDefTracking(); 521 LIR* lab = intrinsic_launchpads_.Get(i); 522 CallInfo* info = reinterpret_cast<CallInfo*>(lab->operands[0]); 523 current_dalvik_offset_ = info->offset; 524 AppendLIR(lab); 525 // NOTE: GenInvoke handles MarkSafepointPC 526 GenInvoke(info); 527 LIR* resume_lab = reinterpret_cast<LIR*>(lab->operands[2]); 528 if (resume_lab != NULL) { 529 OpUnconditionalBranch(resume_lab); 530 } 531 } 532} 533 534void Mir2Lir::HandleThrowLaunchPads() { 535 int num_elems = throw_launchpads_.Size(); 536 for (int i = 0; i < num_elems; i++) { 537 ResetRegPool(); 538 ResetDefTracking(); 539 LIR* lab = throw_launchpads_.Get(i); 540 current_dalvik_offset_ = lab->operands[1]; 541 AppendLIR(lab); 542 ThreadOffset func_offset(-1); 543 int v1 = lab->operands[2]; 544 int v2 = lab->operands[3]; 545 bool target_x86 = (cu_->instruction_set == kX86); 546 switch (lab->operands[0]) { 547 case kThrowNullPointer: 548 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowNullPointer); 549 break; 550 case kThrowConstantArrayBounds: // v1 is length reg (for Arm/Mips), v2 constant index 551 // v1 holds the constant array index. Mips/Arm uses v2 for length, x86 reloads. 552 if (target_x86) { 553 OpRegMem(kOpMov, TargetReg(kArg1), v1, mirror::Array::LengthOffset().Int32Value()); 554 } else { 555 OpRegCopy(TargetReg(kArg1), v1); 556 } 557 // Make sure the following LoadConstant doesn't mess with kArg1. 558 LockTemp(TargetReg(kArg1)); 559 LoadConstant(TargetReg(kArg0), v2); 560 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 561 break; 562 case kThrowArrayBounds: 563 // Move v1 (array index) to kArg0 and v2 (array length) to kArg1 564 if (v2 != TargetReg(kArg0)) { 565 OpRegCopy(TargetReg(kArg0), v1); 566 if (target_x86) { 567 // x86 leaves the array pointer in v2, so load the array length that the handler expects 568 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 569 } else { 570 OpRegCopy(TargetReg(kArg1), v2); 571 } 572 } else { 573 if (v1 == TargetReg(kArg1)) { 574 // Swap v1 and v2, using kArg2 as a temp 575 OpRegCopy(TargetReg(kArg2), v1); 576 if (target_x86) { 577 // x86 leaves the array pointer in v2; load the array length that the handler expects 578 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 579 } else { 580 OpRegCopy(TargetReg(kArg1), v2); 581 } 582 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 583 } else { 584 if (target_x86) { 585 // x86 leaves the array pointer in v2; load the array length that the handler expects 586 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 587 } else { 588 OpRegCopy(TargetReg(kArg1), v2); 589 } 590 OpRegCopy(TargetReg(kArg0), v1); 591 } 592 } 593 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 594 break; 595 case kThrowDivZero: 596 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowDivZero); 597 break; 598 case kThrowNoSuchMethod: 599 OpRegCopy(TargetReg(kArg0), v1); 600 func_offset = 601 QUICK_ENTRYPOINT_OFFSET(pThrowNoSuchMethod); 602 break; 603 case kThrowStackOverflow: 604 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow); 605 // Restore stack alignment 606 if (target_x86) { 607 OpRegImm(kOpAdd, TargetReg(kSp), frame_size_); 608 } else { 609 OpRegImm(kOpAdd, TargetReg(kSp), (num_core_spills_ + num_fp_spills_) * 4); 610 } 611 break; 612 default: 613 LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0]; 614 } 615 ClobberCalleeSave(); 616 int r_tgt = CallHelperSetup(func_offset); 617 CallHelper(r_tgt, func_offset, true /* MarkSafepointPC */); 618 } 619} 620 621void Mir2Lir::GenIGet(uint32_t field_idx, int opt_flags, OpSize size, 622 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 623 bool is_object) { 624 int field_offset; 625 bool is_volatile; 626 627 bool fast_path = FastInstance(field_idx, false, &field_offset, &is_volatile); 628 629 if (fast_path && !SLOW_FIELD_PATH) { 630 RegLocation rl_result; 631 RegisterClass reg_class = oat_reg_class_by_size(size); 632 DCHECK_GE(field_offset, 0); 633 rl_obj = LoadValue(rl_obj, kCoreReg); 634 if (is_long_or_double) { 635 DCHECK(rl_dest.wide); 636 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, opt_flags); 637 if (cu_->instruction_set == kX86) { 638 rl_result = EvalLoc(rl_dest, reg_class, true); 639 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, opt_flags); 640 LoadBaseDispWide(rl_obj.low_reg, field_offset, rl_result.low_reg, 641 rl_result.high_reg, rl_obj.s_reg_low); 642 if (is_volatile) { 643 GenMemBarrier(kLoadLoad); 644 } 645 } else { 646 int reg_ptr = AllocTemp(); 647 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.low_reg, field_offset); 648 rl_result = EvalLoc(rl_dest, reg_class, true); 649 LoadBaseDispWide(reg_ptr, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); 650 if (is_volatile) { 651 GenMemBarrier(kLoadLoad); 652 } 653 FreeTemp(reg_ptr); 654 } 655 StoreValueWide(rl_dest, rl_result); 656 } else { 657 rl_result = EvalLoc(rl_dest, reg_class, true); 658 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, opt_flags); 659 LoadBaseDisp(rl_obj.low_reg, field_offset, rl_result.low_reg, 660 kWord, rl_obj.s_reg_low); 661 if (is_volatile) { 662 GenMemBarrier(kLoadLoad); 663 } 664 StoreValue(rl_dest, rl_result); 665 } 666 } else { 667 ThreadOffset getterOffset = 668 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Instance) 669 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjInstance) 670 : QUICK_ENTRYPOINT_OFFSET(pGet32Instance)); 671 CallRuntimeHelperImmRegLocation(getterOffset, field_idx, rl_obj, true); 672 if (is_long_or_double) { 673 RegLocation rl_result = GetReturnWide(rl_dest.fp); 674 StoreValueWide(rl_dest, rl_result); 675 } else { 676 RegLocation rl_result = GetReturn(rl_dest.fp); 677 StoreValue(rl_dest, rl_result); 678 } 679 } 680} 681 682void Mir2Lir::GenIPut(uint32_t field_idx, int opt_flags, OpSize size, 683 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 684 bool is_object) { 685 int field_offset; 686 bool is_volatile; 687 688 bool fast_path = FastInstance(field_idx, true, &field_offset, &is_volatile); 689 if (fast_path && !SLOW_FIELD_PATH) { 690 RegisterClass reg_class = oat_reg_class_by_size(size); 691 DCHECK_GE(field_offset, 0); 692 rl_obj = LoadValue(rl_obj, kCoreReg); 693 if (is_long_or_double) { 694 int reg_ptr; 695 rl_src = LoadValueWide(rl_src, kAnyReg); 696 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, opt_flags); 697 reg_ptr = AllocTemp(); 698 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.low_reg, field_offset); 699 if (is_volatile) { 700 GenMemBarrier(kStoreStore); 701 } 702 StoreBaseDispWide(reg_ptr, 0, rl_src.low_reg, rl_src.high_reg); 703 if (is_volatile) { 704 GenMemBarrier(kLoadLoad); 705 } 706 FreeTemp(reg_ptr); 707 } else { 708 rl_src = LoadValue(rl_src, reg_class); 709 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, opt_flags); 710 if (is_volatile) { 711 GenMemBarrier(kStoreStore); 712 } 713 StoreBaseDisp(rl_obj.low_reg, field_offset, rl_src.low_reg, kWord); 714 if (is_volatile) { 715 GenMemBarrier(kLoadLoad); 716 } 717 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 718 MarkGCCard(rl_src.low_reg, rl_obj.low_reg); 719 } 720 } 721 } else { 722 ThreadOffset setter_offset = 723 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Instance) 724 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjInstance) 725 : QUICK_ENTRYPOINT_OFFSET(pSet32Instance)); 726 CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_idx, rl_obj, rl_src, true); 727 } 728} 729 730void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 731 RegLocation rl_method = LoadCurrMethod(); 732 int res_reg = AllocTemp(); 733 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 734 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 735 *cu_->dex_file, 736 type_idx)) { 737 // Call out to helper which resolves type and verifies access. 738 // Resolved type returned in kRet0. 739 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 740 type_idx, rl_method.low_reg, true); 741 RegLocation rl_result = GetReturn(false); 742 StoreValue(rl_dest, rl_result); 743 } else { 744 // We're don't need access checks, load type from dex cache 745 int32_t dex_cache_offset = 746 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 747 LoadWordDisp(rl_method.low_reg, dex_cache_offset, res_reg); 748 int32_t offset_of_type = 749 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 750 * type_idx); 751 LoadWordDisp(res_reg, offset_of_type, rl_result.low_reg); 752 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 753 type_idx) || SLOW_TYPE_PATH) { 754 // Slow path, at runtime test if type is null and if so initialize 755 FlushAllRegs(); 756 LIR* branch1 = OpCmpImmBranch(kCondEq, rl_result.low_reg, 0, NULL); 757 // Resolved, store and hop over following code 758 StoreValue(rl_dest, rl_result); 759 /* 760 * Because we have stores of the target value on two paths, 761 * clobber temp tracking for the destination using the ssa name 762 */ 763 ClobberSReg(rl_dest.s_reg_low); 764 LIR* branch2 = OpUnconditionalBranch(0); 765 // TUNING: move slow path to end & remove unconditional branch 766 LIR* target1 = NewLIR0(kPseudoTargetLabel); 767 // Call out to helper, which will return resolved type in kArg0 768 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, 769 rl_method.low_reg, true); 770 RegLocation rl_result = GetReturn(false); 771 StoreValue(rl_dest, rl_result); 772 /* 773 * Because we have stores of the target value on two paths, 774 * clobber temp tracking for the destination using the ssa name 775 */ 776 ClobberSReg(rl_dest.s_reg_low); 777 // Rejoin code paths 778 LIR* target2 = NewLIR0(kPseudoTargetLabel); 779 branch1->target = target1; 780 branch2->target = target2; 781 } else { 782 // Fast path, we're done - just store result 783 StoreValue(rl_dest, rl_result); 784 } 785 } 786} 787 788void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 789 /* NOTE: Most strings should be available at compile time */ 790 int32_t offset_of_string = mirror::Array::DataOffset(sizeof(mirror::String*)).Int32Value() + 791 (sizeof(mirror::String*) * string_idx); 792 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 793 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 794 // slow path, resolve string if not in dex cache 795 FlushAllRegs(); 796 LockCallTemps(); // Using explicit registers 797 LoadCurrMethodDirect(TargetReg(kArg2)); 798 LoadWordDisp(TargetReg(kArg2), 799 mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), TargetReg(kArg0)); 800 // Might call out to helper, which will return resolved string in kRet0 801 int r_tgt = CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(pResolveString)); 802 LoadWordDisp(TargetReg(kArg0), offset_of_string, TargetReg(kRet0)); 803 LoadConstant(TargetReg(kArg1), string_idx); 804 if (cu_->instruction_set == kThumb2) { 805 OpRegImm(kOpCmp, TargetReg(kRet0), 0); // Is resolved? 806 GenBarrier(); 807 // For testing, always force through helper 808 if (!EXERCISE_SLOWEST_STRING_PATH) { 809 OpIT(kCondEq, "T"); 810 } 811 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .eq 812 LIR* call_inst = OpReg(kOpBlx, r_tgt); // .eq, helper(Method*, string_idx) 813 MarkSafepointPC(call_inst); 814 FreeTemp(r_tgt); 815 } else if (cu_->instruction_set == kMips) { 816 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kRet0), 0, NULL); 817 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .eq 818 LIR* call_inst = OpReg(kOpBlx, r_tgt); 819 MarkSafepointPC(call_inst); 820 FreeTemp(r_tgt); 821 LIR* target = NewLIR0(kPseudoTargetLabel); 822 branch->target = target; 823 } else { 824 DCHECK_EQ(cu_->instruction_set, kX86); 825 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pResolveString), TargetReg(kArg2), 826 TargetReg(kArg1), true); 827 } 828 GenBarrier(); 829 StoreValue(rl_dest, GetReturn(false)); 830 } else { 831 RegLocation rl_method = LoadCurrMethod(); 832 int res_reg = AllocTemp(); 833 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 834 LoadWordDisp(rl_method.low_reg, 835 mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg); 836 LoadWordDisp(res_reg, offset_of_string, rl_result.low_reg); 837 StoreValue(rl_dest, rl_result); 838 } 839} 840 841/* 842 * Let helper function take care of everything. Will 843 * call Class::NewInstanceFromCode(type_idx, method); 844 */ 845void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 846 FlushAllRegs(); /* Everything to home location */ 847 // alloc will always check for resolution, do we also need to verify 848 // access because the verifier was unable to? 849 ThreadOffset func_offset(-1); 850 if (cu_->compiler_driver->CanAccessInstantiableTypeWithoutChecks( 851 cu_->method_idx, *cu_->dex_file, type_idx)) { 852 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObject); 853 } else { 854 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectWithAccessCheck); 855 } 856 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 857 RegLocation rl_result = GetReturn(false); 858 StoreValue(rl_dest, rl_result); 859} 860 861void Mir2Lir::GenThrow(RegLocation rl_src) { 862 FlushAllRegs(); 863 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pDeliverException), rl_src, true); 864} 865 866// For final classes there are no sub-classes to check and so we can answer the instance-of 867// question with simple comparisons. 868void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 869 RegLocation rl_src) { 870 RegLocation object = LoadValue(rl_src, kCoreReg); 871 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 872 int result_reg = rl_result.low_reg; 873 if (result_reg == object.low_reg) { 874 result_reg = AllocTypedTemp(false, kCoreReg); 875 } 876 LoadConstant(result_reg, 0); // assume false 877 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.low_reg, 0, NULL); 878 879 int check_class = AllocTypedTemp(false, kCoreReg); 880 int object_class = AllocTypedTemp(false, kCoreReg); 881 882 LoadCurrMethodDirect(check_class); 883 if (use_declaring_class) { 884 LoadWordDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 885 check_class); 886 LoadWordDisp(object.low_reg, mirror::Object::ClassOffset().Int32Value(), object_class); 887 } else { 888 LoadWordDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 889 check_class); 890 LoadWordDisp(object.low_reg, mirror::Object::ClassOffset().Int32Value(), object_class); 891 int32_t offset_of_type = 892 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 893 (sizeof(mirror::Class*) * type_idx); 894 LoadWordDisp(check_class, offset_of_type, check_class); 895 } 896 897 LIR* ne_branchover = NULL; 898 if (cu_->instruction_set == kThumb2) { 899 OpRegReg(kOpCmp, check_class, object_class); // Same? 900 OpIT(kCondEq, ""); // if-convert the test 901 LoadConstant(result_reg, 1); // .eq case - load true 902 } else { 903 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 904 LoadConstant(result_reg, 1); // eq case - load true 905 } 906 LIR* target = NewLIR0(kPseudoTargetLabel); 907 null_branchover->target = target; 908 if (ne_branchover != NULL) { 909 ne_branchover->target = target; 910 } 911 FreeTemp(object_class); 912 FreeTemp(check_class); 913 if (IsTemp(result_reg)) { 914 OpRegCopy(rl_result.low_reg, result_reg); 915 FreeTemp(result_reg); 916 } 917 StoreValue(rl_dest, rl_result); 918} 919 920void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 921 bool type_known_abstract, bool use_declaring_class, 922 bool can_assume_type_is_in_dex_cache, 923 uint32_t type_idx, RegLocation rl_dest, 924 RegLocation rl_src) { 925 FlushAllRegs(); 926 // May generate a call - use explicit registers 927 LockCallTemps(); 928 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 929 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 930 if (needs_access_check) { 931 // Check we have access to type_idx and if not throw IllegalAccessError, 932 // returns Class* in kArg0 933 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 934 type_idx, true); 935 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 936 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 937 } else if (use_declaring_class) { 938 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 939 LoadWordDisp(TargetReg(kArg1), 940 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 941 } else { 942 // Load dex cache entry into class_reg (kArg2) 943 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 944 LoadWordDisp(TargetReg(kArg1), 945 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 946 int32_t offset_of_type = 947 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 948 * type_idx); 949 LoadWordDisp(class_reg, offset_of_type, class_reg); 950 if (!can_assume_type_is_in_dex_cache) { 951 // Need to test presence of type in dex cache at runtime 952 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 953 // Not resolved 954 // Call out to helper, which will return resolved type in kRet0 955 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true); 956 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path 957 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* reload Ref */ 958 // Rejoin code paths 959 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 960 hop_branch->target = hop_target; 961 } 962 } 963 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 964 RegLocation rl_result = GetReturn(false); 965 if (cu_->instruction_set == kMips) { 966 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 967 LoadConstant(rl_result.low_reg, 0); 968 } 969 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 970 971 /* load object->klass_ */ 972 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 973 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 974 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 975 LIR* branchover = NULL; 976 if (type_known_final) { 977 // rl_result == ref == null == 0. 978 if (cu_->instruction_set == kThumb2) { 979 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 980 OpIT(kCondEq, "E"); // if-convert the test 981 LoadConstant(rl_result.low_reg, 1); // .eq case - load true 982 LoadConstant(rl_result.low_reg, 0); // .ne case - load false 983 } else { 984 LoadConstant(rl_result.low_reg, 0); // ne case - load false 985 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1), TargetReg(kArg2), NULL); 986 LoadConstant(rl_result.low_reg, 1); // eq case - load true 987 } 988 } else { 989 if (cu_->instruction_set == kThumb2) { 990 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 991 if (!type_known_abstract) { 992 /* Uses conditional nullification */ 993 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 994 OpIT(kCondEq, "EE"); // if-convert the test 995 LoadConstant(TargetReg(kArg0), 1); // .eq case - load true 996 } 997 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 998 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 999 FreeTemp(r_tgt); 1000 } else { 1001 if (!type_known_abstract) { 1002 /* Uses branchovers */ 1003 LoadConstant(rl_result.low_reg, 1); // assume true 1004 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 1005 } 1006 if (cu_->instruction_set != kX86) { 1007 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1008 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1009 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1010 FreeTemp(r_tgt); 1011 } else { 1012 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 1013 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1014 } 1015 } 1016 } 1017 // TODO: only clobber when type isn't final? 1018 ClobberCalleeSave(); 1019 /* branch targets here */ 1020 LIR* target = NewLIR0(kPseudoTargetLabel); 1021 StoreValue(rl_dest, rl_result); 1022 branch1->target = target; 1023 if (branchover != NULL) { 1024 branchover->target = target; 1025 } 1026} 1027 1028void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1029 bool type_known_final, type_known_abstract, use_declaring_class; 1030 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1031 *cu_->dex_file, 1032 type_idx, 1033 &type_known_final, 1034 &type_known_abstract, 1035 &use_declaring_class); 1036 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1037 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1038 1039 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1040 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1041 } else { 1042 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1043 use_declaring_class, can_assume_type_is_in_dex_cache, 1044 type_idx, rl_dest, rl_src); 1045 } 1046} 1047 1048void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1049 bool type_known_final, type_known_abstract, use_declaring_class; 1050 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1051 *cu_->dex_file, 1052 type_idx, 1053 &type_known_final, 1054 &type_known_abstract, 1055 &use_declaring_class); 1056 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1057 // of the exception throw path. 1058 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1059 const MethodReference mr(cu->GetDexFile(), cu->GetDexMethodIndex()); 1060 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(mr, insn_idx)) { 1061 // Verifier type analysis proved this check cast would never cause an exception. 1062 return; 1063 } 1064 FlushAllRegs(); 1065 // May generate a call - use explicit registers 1066 LockCallTemps(); 1067 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1068 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1069 if (needs_access_check) { 1070 // Check we have access to type_idx and if not throw IllegalAccessError, 1071 // returns Class* in kRet0 1072 // InitializeTypeAndVerifyAccess(idx, method) 1073 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1074 type_idx, TargetReg(kArg1), true); 1075 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1076 } else if (use_declaring_class) { 1077 LoadWordDisp(TargetReg(kArg1), 1078 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1079 } else { 1080 // Load dex cache entry into class_reg (kArg2) 1081 LoadWordDisp(TargetReg(kArg1), 1082 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1083 int32_t offset_of_type = 1084 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1085 (sizeof(mirror::Class*) * type_idx); 1086 LoadWordDisp(class_reg, offset_of_type, class_reg); 1087 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1088 // Need to test presence of type in dex cache at runtime 1089 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1090 // Not resolved 1091 // Call out to helper, which will return resolved type in kArg0 1092 // InitializeTypeFromCode(idx, method) 1093 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, 1094 TargetReg(kArg1), true); 1095 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1096 // Rejoin code paths 1097 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1098 hop_branch->target = hop_target; 1099 } 1100 } 1101 // At this point, class_reg (kArg2) has class 1102 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1103 /* Null is OK - continue */ 1104 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1105 /* load object->klass_ */ 1106 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1107 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 1108 /* kArg1 now contains object->klass_ */ 1109 LIR* branch2 = NULL; 1110 if (!type_known_abstract) { 1111 branch2 = OpCmpBranch(kCondEq, TargetReg(kArg1), class_reg, NULL); 1112 } 1113 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pCheckCast), TargetReg(kArg1), 1114 TargetReg(kArg2), true); 1115 /* branch target here */ 1116 LIR* target = NewLIR0(kPseudoTargetLabel); 1117 branch1->target = target; 1118 if (branch2 != NULL) { 1119 branch2->target = target; 1120 } 1121} 1122 1123void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1124 RegLocation rl_src1, RegLocation rl_src2) { 1125 RegLocation rl_result; 1126 if (cu_->instruction_set == kThumb2) { 1127 /* 1128 * NOTE: This is the one place in the code in which we might have 1129 * as many as six live temporary registers. There are 5 in the normal 1130 * set for Arm. Until we have spill capabilities, temporarily add 1131 * lr to the temp set. It is safe to do this locally, but note that 1132 * lr is used explicitly elsewhere in the code generator and cannot 1133 * normally be used as a general temp register. 1134 */ 1135 MarkTemp(TargetReg(kLr)); // Add lr to the temp pool 1136 FreeTemp(TargetReg(kLr)); // and make it available 1137 } 1138 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1139 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1140 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1141 // The longs may overlap - use intermediate temp if so 1142 if ((rl_result.low_reg == rl_src1.high_reg) || (rl_result.low_reg == rl_src2.high_reg)) { 1143 int t_reg = AllocTemp(); 1144 OpRegRegReg(first_op, t_reg, rl_src1.low_reg, rl_src2.low_reg); 1145 OpRegRegReg(second_op, rl_result.high_reg, rl_src1.high_reg, rl_src2.high_reg); 1146 OpRegCopy(rl_result.low_reg, t_reg); 1147 FreeTemp(t_reg); 1148 } else { 1149 OpRegRegReg(first_op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg); 1150 OpRegRegReg(second_op, rl_result.high_reg, rl_src1.high_reg, 1151 rl_src2.high_reg); 1152 } 1153 /* 1154 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1155 * following StoreValueWide might need to allocate a temp register. 1156 * To further work around the lack of a spill capability, explicitly 1157 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1158 * Remove when spill is functional. 1159 */ 1160 FreeRegLocTemps(rl_result, rl_src1); 1161 FreeRegLocTemps(rl_result, rl_src2); 1162 StoreValueWide(rl_dest, rl_result); 1163 if (cu_->instruction_set == kThumb2) { 1164 Clobber(TargetReg(kLr)); 1165 UnmarkTemp(TargetReg(kLr)); // Remove lr from the temp pool 1166 } 1167} 1168 1169 1170void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1171 RegLocation rl_src1, RegLocation rl_shift) { 1172 ThreadOffset func_offset(-1); 1173 1174 switch (opcode) { 1175 case Instruction::SHL_LONG: 1176 case Instruction::SHL_LONG_2ADDR: 1177 func_offset = QUICK_ENTRYPOINT_OFFSET(pShlLong); 1178 break; 1179 case Instruction::SHR_LONG: 1180 case Instruction::SHR_LONG_2ADDR: 1181 func_offset = QUICK_ENTRYPOINT_OFFSET(pShrLong); 1182 break; 1183 case Instruction::USHR_LONG: 1184 case Instruction::USHR_LONG_2ADDR: 1185 func_offset = QUICK_ENTRYPOINT_OFFSET(pUshrLong); 1186 break; 1187 default: 1188 LOG(FATAL) << "Unexpected case"; 1189 } 1190 FlushAllRegs(); /* Send everything to home location */ 1191 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1192 RegLocation rl_result = GetReturnWide(false); 1193 StoreValueWide(rl_dest, rl_result); 1194} 1195 1196 1197void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1198 RegLocation rl_src1, RegLocation rl_src2) { 1199 OpKind op = kOpBkpt; 1200 bool is_div_rem = false; 1201 bool check_zero = false; 1202 bool unary = false; 1203 RegLocation rl_result; 1204 bool shift_op = false; 1205 switch (opcode) { 1206 case Instruction::NEG_INT: 1207 op = kOpNeg; 1208 unary = true; 1209 break; 1210 case Instruction::NOT_INT: 1211 op = kOpMvn; 1212 unary = true; 1213 break; 1214 case Instruction::ADD_INT: 1215 case Instruction::ADD_INT_2ADDR: 1216 op = kOpAdd; 1217 break; 1218 case Instruction::SUB_INT: 1219 case Instruction::SUB_INT_2ADDR: 1220 op = kOpSub; 1221 break; 1222 case Instruction::MUL_INT: 1223 case Instruction::MUL_INT_2ADDR: 1224 op = kOpMul; 1225 break; 1226 case Instruction::DIV_INT: 1227 case Instruction::DIV_INT_2ADDR: 1228 check_zero = true; 1229 op = kOpDiv; 1230 is_div_rem = true; 1231 break; 1232 /* NOTE: returns in kArg1 */ 1233 case Instruction::REM_INT: 1234 case Instruction::REM_INT_2ADDR: 1235 check_zero = true; 1236 op = kOpRem; 1237 is_div_rem = true; 1238 break; 1239 case Instruction::AND_INT: 1240 case Instruction::AND_INT_2ADDR: 1241 op = kOpAnd; 1242 break; 1243 case Instruction::OR_INT: 1244 case Instruction::OR_INT_2ADDR: 1245 op = kOpOr; 1246 break; 1247 case Instruction::XOR_INT: 1248 case Instruction::XOR_INT_2ADDR: 1249 op = kOpXor; 1250 break; 1251 case Instruction::SHL_INT: 1252 case Instruction::SHL_INT_2ADDR: 1253 shift_op = true; 1254 op = kOpLsl; 1255 break; 1256 case Instruction::SHR_INT: 1257 case Instruction::SHR_INT_2ADDR: 1258 shift_op = true; 1259 op = kOpAsr; 1260 break; 1261 case Instruction::USHR_INT: 1262 case Instruction::USHR_INT_2ADDR: 1263 shift_op = true; 1264 op = kOpLsr; 1265 break; 1266 default: 1267 LOG(FATAL) << "Invalid word arith op: " << opcode; 1268 } 1269 if (!is_div_rem) { 1270 if (unary) { 1271 rl_src1 = LoadValue(rl_src1, kCoreReg); 1272 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1273 OpRegReg(op, rl_result.low_reg, rl_src1.low_reg); 1274 } else { 1275 if (shift_op) { 1276 int t_reg = INVALID_REG; 1277 if (cu_->instruction_set == kX86) { 1278 // X86 doesn't require masking and must use ECX 1279 t_reg = TargetReg(kCount); // rCX 1280 LoadValueDirectFixed(rl_src2, t_reg); 1281 } else { 1282 rl_src2 = LoadValue(rl_src2, kCoreReg); 1283 t_reg = AllocTemp(); 1284 OpRegRegImm(kOpAnd, t_reg, rl_src2.low_reg, 31); 1285 } 1286 rl_src1 = LoadValue(rl_src1, kCoreReg); 1287 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1288 OpRegRegReg(op, rl_result.low_reg, rl_src1.low_reg, t_reg); 1289 FreeTemp(t_reg); 1290 } else { 1291 rl_src1 = LoadValue(rl_src1, kCoreReg); 1292 rl_src2 = LoadValue(rl_src2, kCoreReg); 1293 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1294 OpRegRegReg(op, rl_result.low_reg, rl_src1.low_reg, rl_src2.low_reg); 1295 } 1296 } 1297 StoreValue(rl_dest, rl_result); 1298 } else { 1299 if (cu_->instruction_set == kMips) { 1300 rl_src1 = LoadValue(rl_src1, kCoreReg); 1301 rl_src2 = LoadValue(rl_src2, kCoreReg); 1302 if (check_zero) { 1303 GenImmedCheck(kCondEq, rl_src2.low_reg, 0, kThrowDivZero); 1304 } 1305 rl_result = GenDivRem(rl_dest, rl_src1.low_reg, rl_src2.low_reg, op == kOpDiv); 1306 } else { 1307 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1308 FlushAllRegs(); /* Send everything to home location */ 1309 LoadValueDirectFixed(rl_src2, TargetReg(kArg1)); 1310 int r_tgt = CallHelperSetup(func_offset); 1311 LoadValueDirectFixed(rl_src1, TargetReg(kArg0)); 1312 if (check_zero) { 1313 GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero); 1314 } 1315 // NOTE: callout here is not a safepoint 1316 CallHelper(r_tgt, func_offset, false /* not a safepoint */); 1317 if (op == kOpDiv) 1318 rl_result = GetReturn(false); 1319 else 1320 rl_result = GetReturnAlt(); 1321 } 1322 StoreValue(rl_dest, rl_result); 1323 } 1324} 1325 1326/* 1327 * The following are the first-level codegen routines that analyze the format 1328 * of each bytecode then either dispatch special purpose codegen routines 1329 * or produce corresponding Thumb instructions directly. 1330 */ 1331 1332static bool IsPowerOfTwo(int x) { 1333 return (x & (x - 1)) == 0; 1334} 1335 1336// Returns true if no more than two bits are set in 'x'. 1337static bool IsPopCountLE2(unsigned int x) { 1338 x &= x - 1; 1339 return (x & (x - 1)) == 0; 1340} 1341 1342// Returns the index of the lowest set bit in 'x'. 1343static int LowestSetBit(unsigned int x) { 1344 int bit_posn = 0; 1345 while ((x & 0xf) == 0) { 1346 bit_posn += 4; 1347 x >>= 4; 1348 } 1349 while ((x & 1) == 0) { 1350 bit_posn++; 1351 x >>= 1; 1352 } 1353 return bit_posn; 1354} 1355 1356// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1357// and store the result in 'rl_dest'. 1358bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1359 RegLocation rl_src, RegLocation rl_dest, int lit) { 1360 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1361 return false; 1362 } 1363 // No divide instruction for Arm, so check for more special cases 1364 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1365 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1366 } 1367 int k = LowestSetBit(lit); 1368 if (k >= 30) { 1369 // Avoid special cases. 1370 return false; 1371 } 1372 rl_src = LoadValue(rl_src, kCoreReg); 1373 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1374 if (is_div) { 1375 int t_reg = AllocTemp(); 1376 if (lit == 2) { 1377 // Division by 2 is by far the most common division by constant. 1378 OpRegRegImm(kOpLsr, t_reg, rl_src.low_reg, 32 - k); 1379 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.low_reg); 1380 OpRegRegImm(kOpAsr, rl_result.low_reg, t_reg, k); 1381 } else { 1382 OpRegRegImm(kOpAsr, t_reg, rl_src.low_reg, 31); 1383 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1384 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.low_reg); 1385 OpRegRegImm(kOpAsr, rl_result.low_reg, t_reg, k); 1386 } 1387 } else { 1388 int t_reg1 = AllocTemp(); 1389 int t_reg2 = AllocTemp(); 1390 if (lit == 2) { 1391 OpRegRegImm(kOpLsr, t_reg1, rl_src.low_reg, 32 - k); 1392 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.low_reg); 1393 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1394 OpRegRegReg(kOpSub, rl_result.low_reg, t_reg2, t_reg1); 1395 } else { 1396 OpRegRegImm(kOpAsr, t_reg1, rl_src.low_reg, 31); 1397 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1398 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.low_reg); 1399 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1400 OpRegRegReg(kOpSub, rl_result.low_reg, t_reg2, t_reg1); 1401 } 1402 } 1403 StoreValue(rl_dest, rl_result); 1404 return true; 1405} 1406 1407// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1408// and store the result in 'rl_dest'. 1409bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1410 // Can we simplify this multiplication? 1411 bool power_of_two = false; 1412 bool pop_count_le2 = false; 1413 bool power_of_two_minus_one = false; 1414 if (lit < 2) { 1415 // Avoid special cases. 1416 return false; 1417 } else if (IsPowerOfTwo(lit)) { 1418 power_of_two = true; 1419 } else if (IsPopCountLE2(lit)) { 1420 pop_count_le2 = true; 1421 } else if (IsPowerOfTwo(lit + 1)) { 1422 power_of_two_minus_one = true; 1423 } else { 1424 return false; 1425 } 1426 rl_src = LoadValue(rl_src, kCoreReg); 1427 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1428 if (power_of_two) { 1429 // Shift. 1430 OpRegRegImm(kOpLsl, rl_result.low_reg, rl_src.low_reg, LowestSetBit(lit)); 1431 } else if (pop_count_le2) { 1432 // Shift and add and shift. 1433 int first_bit = LowestSetBit(lit); 1434 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1435 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1436 } else { 1437 // Reverse subtract: (src << (shift + 1)) - src. 1438 DCHECK(power_of_two_minus_one); 1439 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1440 int t_reg = AllocTemp(); 1441 OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, LowestSetBit(lit + 1)); 1442 OpRegRegReg(kOpSub, rl_result.low_reg, t_reg, rl_src.low_reg); 1443 } 1444 StoreValue(rl_dest, rl_result); 1445 return true; 1446} 1447 1448void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1449 int lit) { 1450 RegLocation rl_result; 1451 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1452 int shift_op = false; 1453 bool is_div = false; 1454 1455 switch (opcode) { 1456 case Instruction::RSUB_INT_LIT8: 1457 case Instruction::RSUB_INT: { 1458 rl_src = LoadValue(rl_src, kCoreReg); 1459 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1460 if (cu_->instruction_set == kThumb2) { 1461 OpRegRegImm(kOpRsub, rl_result.low_reg, rl_src.low_reg, lit); 1462 } else { 1463 OpRegReg(kOpNeg, rl_result.low_reg, rl_src.low_reg); 1464 OpRegImm(kOpAdd, rl_result.low_reg, lit); 1465 } 1466 StoreValue(rl_dest, rl_result); 1467 return; 1468 } 1469 1470 case Instruction::SUB_INT: 1471 case Instruction::SUB_INT_2ADDR: 1472 lit = -lit; 1473 // Intended fallthrough 1474 case Instruction::ADD_INT: 1475 case Instruction::ADD_INT_2ADDR: 1476 case Instruction::ADD_INT_LIT8: 1477 case Instruction::ADD_INT_LIT16: 1478 op = kOpAdd; 1479 break; 1480 case Instruction::MUL_INT: 1481 case Instruction::MUL_INT_2ADDR: 1482 case Instruction::MUL_INT_LIT8: 1483 case Instruction::MUL_INT_LIT16: { 1484 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1485 return; 1486 } 1487 op = kOpMul; 1488 break; 1489 } 1490 case Instruction::AND_INT: 1491 case Instruction::AND_INT_2ADDR: 1492 case Instruction::AND_INT_LIT8: 1493 case Instruction::AND_INT_LIT16: 1494 op = kOpAnd; 1495 break; 1496 case Instruction::OR_INT: 1497 case Instruction::OR_INT_2ADDR: 1498 case Instruction::OR_INT_LIT8: 1499 case Instruction::OR_INT_LIT16: 1500 op = kOpOr; 1501 break; 1502 case Instruction::XOR_INT: 1503 case Instruction::XOR_INT_2ADDR: 1504 case Instruction::XOR_INT_LIT8: 1505 case Instruction::XOR_INT_LIT16: 1506 op = kOpXor; 1507 break; 1508 case Instruction::SHL_INT_LIT8: 1509 case Instruction::SHL_INT: 1510 case Instruction::SHL_INT_2ADDR: 1511 lit &= 31; 1512 shift_op = true; 1513 op = kOpLsl; 1514 break; 1515 case Instruction::SHR_INT_LIT8: 1516 case Instruction::SHR_INT: 1517 case Instruction::SHR_INT_2ADDR: 1518 lit &= 31; 1519 shift_op = true; 1520 op = kOpAsr; 1521 break; 1522 case Instruction::USHR_INT_LIT8: 1523 case Instruction::USHR_INT: 1524 case Instruction::USHR_INT_2ADDR: 1525 lit &= 31; 1526 shift_op = true; 1527 op = kOpLsr; 1528 break; 1529 1530 case Instruction::DIV_INT: 1531 case Instruction::DIV_INT_2ADDR: 1532 case Instruction::DIV_INT_LIT8: 1533 case Instruction::DIV_INT_LIT16: 1534 case Instruction::REM_INT: 1535 case Instruction::REM_INT_2ADDR: 1536 case Instruction::REM_INT_LIT8: 1537 case Instruction::REM_INT_LIT16: { 1538 if (lit == 0) { 1539 GenImmedCheck(kCondAl, 0, 0, kThrowDivZero); 1540 return; 1541 } 1542 if ((opcode == Instruction::DIV_INT) || 1543 (opcode == Instruction::DIV_INT_2ADDR) || 1544 (opcode == Instruction::DIV_INT_LIT8) || 1545 (opcode == Instruction::DIV_INT_LIT16)) { 1546 is_div = true; 1547 } else { 1548 is_div = false; 1549 } 1550 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1551 return; 1552 } 1553 if (cu_->instruction_set == kMips) { 1554 rl_src = LoadValue(rl_src, kCoreReg); 1555 rl_result = GenDivRemLit(rl_dest, rl_src.low_reg, lit, is_div); 1556 } else { 1557 FlushAllRegs(); /* Everything to home location */ 1558 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 1559 Clobber(TargetReg(kArg0)); 1560 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1561 CallRuntimeHelperRegImm(func_offset, TargetReg(kArg0), lit, false); 1562 if (is_div) 1563 rl_result = GetReturn(false); 1564 else 1565 rl_result = GetReturnAlt(); 1566 } 1567 StoreValue(rl_dest, rl_result); 1568 return; 1569 } 1570 default: 1571 LOG(FATAL) << "Unexpected opcode " << opcode; 1572 } 1573 rl_src = LoadValue(rl_src, kCoreReg); 1574 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1575 // Avoid shifts by literal 0 - no support in Thumb. Change to copy 1576 if (shift_op && (lit == 0)) { 1577 OpRegCopy(rl_result.low_reg, rl_src.low_reg); 1578 } else { 1579 OpRegRegImm(op, rl_result.low_reg, rl_src.low_reg, lit); 1580 } 1581 StoreValue(rl_dest, rl_result); 1582} 1583 1584void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 1585 RegLocation rl_src1, RegLocation rl_src2) { 1586 RegLocation rl_result; 1587 OpKind first_op = kOpBkpt; 1588 OpKind second_op = kOpBkpt; 1589 bool call_out = false; 1590 bool check_zero = false; 1591 ThreadOffset func_offset(-1); 1592 int ret_reg = TargetReg(kRet0); 1593 1594 switch (opcode) { 1595 case Instruction::NOT_LONG: 1596 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1597 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1598 // Check for destructive overlap 1599 if (rl_result.low_reg == rl_src2.high_reg) { 1600 int t_reg = AllocTemp(); 1601 OpRegCopy(t_reg, rl_src2.high_reg); 1602 OpRegReg(kOpMvn, rl_result.low_reg, rl_src2.low_reg); 1603 OpRegReg(kOpMvn, rl_result.high_reg, t_reg); 1604 FreeTemp(t_reg); 1605 } else { 1606 OpRegReg(kOpMvn, rl_result.low_reg, rl_src2.low_reg); 1607 OpRegReg(kOpMvn, rl_result.high_reg, rl_src2.high_reg); 1608 } 1609 StoreValueWide(rl_dest, rl_result); 1610 return; 1611 case Instruction::ADD_LONG: 1612 case Instruction::ADD_LONG_2ADDR: 1613 if (cu_->instruction_set != kThumb2) { 1614 GenAddLong(rl_dest, rl_src1, rl_src2); 1615 return; 1616 } 1617 first_op = kOpAdd; 1618 second_op = kOpAdc; 1619 break; 1620 case Instruction::SUB_LONG: 1621 case Instruction::SUB_LONG_2ADDR: 1622 if (cu_->instruction_set != kThumb2) { 1623 GenSubLong(rl_dest, rl_src1, rl_src2); 1624 return; 1625 } 1626 first_op = kOpSub; 1627 second_op = kOpSbc; 1628 break; 1629 case Instruction::MUL_LONG: 1630 case Instruction::MUL_LONG_2ADDR: 1631 if (cu_->instruction_set == kThumb2) { 1632 GenMulLong(rl_dest, rl_src1, rl_src2); 1633 return; 1634 } else { 1635 call_out = true; 1636 ret_reg = TargetReg(kRet0); 1637 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul); 1638 } 1639 break; 1640 case Instruction::DIV_LONG: 1641 case Instruction::DIV_LONG_2ADDR: 1642 call_out = true; 1643 check_zero = true; 1644 ret_reg = TargetReg(kRet0); 1645 func_offset = QUICK_ENTRYPOINT_OFFSET(pLdiv); 1646 break; 1647 case Instruction::REM_LONG: 1648 case Instruction::REM_LONG_2ADDR: 1649 call_out = true; 1650 check_zero = true; 1651 func_offset = QUICK_ENTRYPOINT_OFFSET(pLdivmod); 1652 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 1653 ret_reg = (cu_->instruction_set == kThumb2) ? TargetReg(kArg2) : TargetReg(kRet0); 1654 break; 1655 case Instruction::AND_LONG_2ADDR: 1656 case Instruction::AND_LONG: 1657 if (cu_->instruction_set == kX86) { 1658 return GenAndLong(rl_dest, rl_src1, rl_src2); 1659 } 1660 first_op = kOpAnd; 1661 second_op = kOpAnd; 1662 break; 1663 case Instruction::OR_LONG: 1664 case Instruction::OR_LONG_2ADDR: 1665 if (cu_->instruction_set == kX86) { 1666 GenOrLong(rl_dest, rl_src1, rl_src2); 1667 return; 1668 } 1669 first_op = kOpOr; 1670 second_op = kOpOr; 1671 break; 1672 case Instruction::XOR_LONG: 1673 case Instruction::XOR_LONG_2ADDR: 1674 if (cu_->instruction_set == kX86) { 1675 GenXorLong(rl_dest, rl_src1, rl_src2); 1676 return; 1677 } 1678 first_op = kOpXor; 1679 second_op = kOpXor; 1680 break; 1681 case Instruction::NEG_LONG: { 1682 GenNegLong(rl_dest, rl_src2); 1683 return; 1684 } 1685 default: 1686 LOG(FATAL) << "Invalid long arith op"; 1687 } 1688 if (!call_out) { 1689 GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 1690 } else { 1691 FlushAllRegs(); /* Send everything to home location */ 1692 if (check_zero) { 1693 LoadValueDirectWideFixed(rl_src2, TargetReg(kArg2), TargetReg(kArg3)); 1694 int r_tgt = CallHelperSetup(func_offset); 1695 GenDivZeroCheck(TargetReg(kArg2), TargetReg(kArg3)); 1696 LoadValueDirectWideFixed(rl_src1, TargetReg(kArg0), TargetReg(kArg1)); 1697 // NOTE: callout here is not a safepoint 1698 CallHelper(r_tgt, func_offset, false /* not safepoint */); 1699 } else { 1700 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1701 } 1702 // Adjust return regs in to handle case of rem returning kArg2/kArg3 1703 if (ret_reg == TargetReg(kRet0)) 1704 rl_result = GetReturnWide(false); 1705 else 1706 rl_result = GetReturnWideAlt(); 1707 StoreValueWide(rl_dest, rl_result); 1708 } 1709} 1710 1711void Mir2Lir::GenConversionCall(ThreadOffset func_offset, 1712 RegLocation rl_dest, RegLocation rl_src) { 1713 /* 1714 * Don't optimize the register usage since it calls out to support 1715 * functions 1716 */ 1717 FlushAllRegs(); /* Send everything to home location */ 1718 if (rl_src.wide) { 1719 LoadValueDirectWideFixed(rl_src, rl_src.fp ? TargetReg(kFArg0) : TargetReg(kArg0), 1720 rl_src.fp ? TargetReg(kFArg1) : TargetReg(kArg1)); 1721 } else { 1722 LoadValueDirectFixed(rl_src, rl_src.fp ? TargetReg(kFArg0) : TargetReg(kArg0)); 1723 } 1724 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 1725 if (rl_dest.wide) { 1726 RegLocation rl_result; 1727 rl_result = GetReturnWide(rl_dest.fp); 1728 StoreValueWide(rl_dest, rl_result); 1729 } else { 1730 RegLocation rl_result; 1731 rl_result = GetReturn(rl_dest.fp); 1732 StoreValue(rl_dest, rl_result); 1733 } 1734} 1735 1736/* Check if we need to check for pending suspend request */ 1737void Mir2Lir::GenSuspendTest(int opt_flags) { 1738 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1739 return; 1740 } 1741 FlushAllRegs(); 1742 LIR* branch = OpTestSuspend(NULL); 1743 LIR* ret_lab = NewLIR0(kPseudoTargetLabel); 1744 LIR* target = RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, 1745 reinterpret_cast<uintptr_t>(ret_lab), current_dalvik_offset_); 1746 branch->target = target; 1747 suspend_launchpads_.Insert(target); 1748} 1749 1750/* Check if we need to check for pending suspend request */ 1751void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 1752 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1753 OpUnconditionalBranch(target); 1754 return; 1755 } 1756 OpTestSuspend(target); 1757 LIR* launch_pad = 1758 RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, 1759 reinterpret_cast<uintptr_t>(target), current_dalvik_offset_); 1760 FlushAllRegs(); 1761 OpUnconditionalBranch(launch_pad); 1762 suspend_launchpads_.Insert(launch_pad); 1763} 1764 1765} // namespace art 1766