1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgCopyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgThe Weather Channel (TM) funded Tungsten Graphics to develop the 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orginitial release of the Radeon 8500 driver under the XFree86 license. 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgThis notice must be preserved. 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgPermission is hereby granted, free of charge, to any person obtaining 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orga copy of this software and associated documentation files (the 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org"Software"), to deal in the Software without restriction, including 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgwithout limitation the rights to use, copy, modify, merge, publish, 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgdistribute, sublicense, and/or sell copies of the Software, and to 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgpermit persons to whom the Software is furnished to do so, subject to 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgthe following conditions: 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgThe above copyright notice and this permission notice (including the 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgnext paragraph) shall be included in all copies or substantial 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgportions of the Software. 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org*/ 28f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 29f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* 30f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Authors: 31f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Keith Whitwell <keith@tungstengraphics.com> 32f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 33f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 34f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/glheader.h" 35f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/imports.h" 36f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/macros.h" 37f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/context.h" 38f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "main/simple_list.h" 39f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 40f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_common.h" 41f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "r200_context.h" 42f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "r200_ioctl.h" 43f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#include "radeon_reg.h" 44f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 45f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* The state atoms will be emitted in the order they appear in the atom list, 46f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * so this step is important. 47f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 48f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define insert_at_tail_if(atom_list, atom) \ 49f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org do { \ 50f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_state_atom* current_atom = (atom); \ 51f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org if (current_atom->check) \ 52f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail((atom_list), current_atom); \ 53f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } while(0) 54f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 55f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200SetUpAtomList( r200ContextPtr rmesa ) 56f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 57f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int i, mtu; 58f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 59f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org mtu = rmesa->radeon.glCtx->Const.MaxTextureUnits; 60f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 61f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org make_empty_list(&rmesa->radeon.hw.atomlist); 62f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.hw.atomlist.name = "atom-list"; 63f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 64f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ctx ); 65f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.set ); 66f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lin ); 67f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msk ); 68f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpt ); 69f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vtx ); 70f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vap ); 71f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vte ); 72f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msc ); 73f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.cst ); 74f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.zbs ); 75f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl ); 76f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.msl ); 77f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcg ); 78f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.grd ); 79f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.fog ); 80f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tam ); 81f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tf ); 82f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.atf ); 83f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < mtu; ++i) 84f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i] ); 85f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < mtu; ++i) 86f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i] ); 87f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < 6; ++i) 88f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.pix[i] ); 89f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[0] ); 90f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.afs[1] ); 91f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.stp ); 92f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < 8; ++i) 93f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i] ); 94f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < 3 + mtu; ++i) 95f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i] ); 96f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.eye ); 97f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.glt ); 98f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < 2; ++i) 99f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.mtl[i] ); 100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i < 6; ++i) 101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i] ); 102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.spr ); 103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.ptp ); 104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.prf ); 105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.pvs ); 106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[0] ); 107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpp[1] ); 108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[0] ); 109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.vpi[1] ); 110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.sci ); 111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* Fire a section of the retained (indexed_verts) buffer as a regular 114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * primtive. 115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200EmitVbufPrim( r200ContextPtr rmesa, 117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint primitive, 118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_nr ) 119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BATCH_LOCALS(&rmesa->radeon); 121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org assert(!(primitive & R200_VF_PRIM_WALK_IND)); 123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonEmitState(&rmesa->radeon); 125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_print(RADEON_RENDER|RADEON_SWRENDER,RADEON_VERBOSE, 127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org "%s cmd_used/4: %d prim %x nr %d\n", __FUNCTION__, 128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->store.cmd_used/4, primitive, vertex_nr); 129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BEGIN_BATCH(3); 131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_VBUF_2, 0); 132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(primitive | R200_VF_PRIM_WALK_LIST | R200_VF_COLOR_ORDER_RGBA | 133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org (vertex_nr << R200_VF_VERTEX_NUMBER_SHIFT)); 134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org END_BATCH(); 135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgstatic void r200FireEB(r200ContextPtr rmesa, int vertex_count, int type) 138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BATCH_LOCALS(&rmesa->radeon); 140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org if (vertex_count > 0) { 142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BEGIN_BATCH(8+2); 143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_PACKET3_CLIP(R200_CP_CMD_3D_DRAW_INDX_2, 0); 144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(R200_VF_PRIM_WALK_IND | 145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org R200_VF_COLOR_ORDER_RGBA | 146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org ((vertex_count + 0) << 16) | 147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org type); 148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2); 150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810); 151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset); 152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH((vertex_count + 1)/2); 153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.tcl.elt_dma_bo, 155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org RADEON_GEM_DOMAIN_GTT, 0, 0); 156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org END_BATCH(); 157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200FlushElts(struct gl_context *ctx) 161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org r200ContextPtr rmesa = R200_CONTEXT(ctx); 163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int nr, elt_used = rmesa->tcl.elt_used; 164f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 165f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used); 166f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 167f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org assert( rmesa->radeon.dma.flush == r200FlushElts ); 168f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.dma.flush = NULL; 169f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 170f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org nr = elt_used / 2; 171f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 172f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo); 173f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 174f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive); 175f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 176f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo); 177f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.tcl.elt_dma_bo = NULL; 178f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 179f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org if (R200_ELT_BUF_SZ > elt_used) 180f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonReturnDmaRegion(&rmesa->radeon, R200_ELT_BUF_SZ - elt_used); 181f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 182f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 183f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 184f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgGLushort *r200AllocEltsOpenEnded( r200ContextPtr rmesa, 185f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint primitive, 186f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint min_nr ) 187f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 188f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLushort *retval; 189f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 190f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %d prim %x\n", __FUNCTION__, min_nr, primitive); 191f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 192f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org assert((primitive & R200_VF_PRIM_WALK_IND)); 193f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 194f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonEmitState(&rmesa->radeon); 195f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 196f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo, 197f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org &rmesa->radeon.tcl.elt_dma_offset, R200_ELT_BUF_SZ, 4); 198f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->tcl.elt_used = min_nr * 2; 199f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 200f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1); 201f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset; 202f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 203f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org assert(!rmesa->radeon.dma.flush); 204f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.glCtx->Driver.NeedFlush |= FLUSH_STORED_VERTICES; 205f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.dma.flush = r200FlushElts; 206f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 207f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org return retval; 208f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 209f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 210f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200EmitMaxVtxIndex(r200ContextPtr rmesa, int count) 211f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 212f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BATCH_LOCALS(&rmesa->radeon); 213f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 214f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BEGIN_BATCH_NO_AUTOSTATE(2); 215f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(CP_PACKET0(R200_SE_VF_MAX_VTX_INDX, 0)); 216f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(count); 217f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org END_BATCH(); 218f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 219f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 220f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200EmitVertexAOS( r200ContextPtr rmesa, 221f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint vertex_size, 222f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org struct radeon_bo *bo, 223f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org GLuint offset ) 224f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 225f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BATCH_LOCALS(&rmesa->radeon); 226f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 227f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_print(RADEON_SWRENDER, RADEON_VERBOSE, "%s: vertex_size 0x%x offset 0x%x \n", 228f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __FUNCTION__, vertex_size, offset); 229f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 230f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 231f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BEGIN_BATCH(7); 232f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, 2); 233f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(1); 234f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(vertex_size | (vertex_size << 8)); 235f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_RELOC(offset, bo, offset, RADEON_GEM_DOMAIN_GTT, 0, 0); 236f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org END_BATCH(); 237f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 238f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 239f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.orgvoid r200EmitAOS(r200ContextPtr rmesa, GLuint nr, GLuint offset) 240f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org{ 241f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BATCH_LOCALS(&rmesa->radeon); 242f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org uint32_t voffset; 243f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int sz = 1 + (nr >> 1) * 3 + (nr & 1) * 2; 244f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org int i; 245f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 246f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_print(RADEON_RENDER, RADEON_VERBOSE, 247f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org "%s: nr=%d, ofs=0x%08x\n", 248f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org __FUNCTION__, nr, offset); 249f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 250f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org BEGIN_BATCH(sz+2+ (nr*2)); 251f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH_PACKET3(R200_CP_CMD_3D_LOAD_VBPNTR, sz - 1); 252f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(nr); 253f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 254f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org { 255f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i + 1 < nr; i += 2) { 256f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) | 257f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org (rmesa->radeon.tcl.aos[i].stride << 8) | 258f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org (rmesa->radeon.tcl.aos[i + 1].components << 16) | 259f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org (rmesa->radeon.tcl.aos[i + 1].stride << 24)); 260f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 261f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[i + 0].offset + 262f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; 263f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(voffset); 264f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[i + 1].offset + 265f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; 266f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(voffset); 267f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 268f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 269f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org if (nr & 1) { 270f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) | 271f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org (rmesa->radeon.tcl.aos[nr - 1].stride << 8)); 272f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[nr - 1].offset + 273f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; 274f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org OUT_BATCH(voffset); 275f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 276f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org for (i = 0; i + 1 < nr; i += 2) { 277f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[i + 0].offset + 278f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride; 279f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 280f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.tcl.aos[i+0].bo, 281f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org RADEON_GEM_DOMAIN_GTT, 282f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 0, 0); 283f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[i + 1].offset + 284f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride; 285f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 286f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.tcl.aos[i+1].bo, 287f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org RADEON_GEM_DOMAIN_GTT, 288f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 0, 0); 289f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 290f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org if (nr & 1) { 291f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org voffset = rmesa->radeon.tcl.aos[nr - 1].offset + 292f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride; 293f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs, 294f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org rmesa->radeon.tcl.aos[nr-1].bo, 295f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org RADEON_GEM_DOMAIN_GTT, 296f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 0, 0); 297f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 298f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org } 299f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org END_BATCH(); 300f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org} 301