1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/**
2 * \file server/radeon_dri.h
3 * \brief Radeon server-side structures.
4 *
5 * \author Kevin E. Martin <martin@xfree86.org>
6 * \author Rickard E. Faith <faith@valinux.com>
7 */
8
9/*
10 * Copyright 2000 ATI Technologies Inc., Markham, Ontario,
11 *                VA Linux Systems Inc., Fremont, California.
12 *
13 * All Rights Reserved.
14 *
15 * Permission is hereby granted, free of charge, to any person obtaining
16 * a copy of this software and associated documentation files (the
17 * "Software"), to deal in the Software without restriction, including
18 * without limitation on the rights to use, copy, modify, merge,
19 * publish, distribute, sublicense, and/or sell copies of the Software,
20 * and to permit persons to whom the Software is furnished to do so,
21 * subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial
25 * portions of the Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NON-INFRINGEMENT.  IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
31 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
32 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
33 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
34 * DEALINGS IN THE SOFTWARE.
35 */
36
37
38#ifndef _RADEON_DRI_
39#define _RADEON_DRI_
40
41#include "xf86drm.h"
42#include "drm.h"
43#include "radeon_drm.h"
44
45/* DRI Driver defaults */
46#define RADEON_DEFAULT_CP_PIO_MODE    RADEON_CSQ_PRIPIO_INDPIO
47#define RADEON_DEFAULT_CP_BM_MODE     RADEON_CSQ_PRIBM_INDBM
48#define RADEON_DEFAULT_AGP_MODE       1
49#define RADEON_DEFAULT_AGP_FAST_WRITE 0
50#define RADEON_DEFAULT_AGP_SIZE       8 /* MB (must be 2^n and > 4MB) */
51#define RADEON_DEFAULT_RING_SIZE      1 /* MB (must be page aligned) */
52#define RADEON_DEFAULT_BUFFER_SIZE    2 /* MB (must be page aligned) */
53#define RADEON_DEFAULT_AGP_TEX_SIZE   1 /* MB (must be page aligned) */
54#define RADEON_DEFAULT_CP_TIMEOUT     10000  /* usecs */
55#define RADEON_DEFAULT_PAGE_FLIP      0 /* page flipping diabled */
56#define RADEON_BUFFER_ALIGN           0x00000fff
57
58/**
59 * \brief Radeon DRI driver private data.
60 */
61typedef struct {
62    /**
63     * \name DRI screen private data
64     */
65    /*@{*/
66    int           deviceID;	 /**< \brief PCI device ID */
67    int           width;	 /**< \brief width in pixels of display */
68    int           height;	 /**< \brief height in scanlines of display */
69    int           depth;	 /**< \brief depth of display (8, 15, 16, 24) */
70    int           bpp;		 /**< \brief bit depth of display (8, 16, 24, 32) */
71
72    int           IsPCI;	 /**< \brief is current card a PCI card? */
73    int           AGPMode;	 /**< \brief AGP mode */
74
75    int           frontOffset;   /**< \brief front buffer offset */
76    int           frontPitch;	 /**< \brief front buffer pitch */
77    int           backOffset;    /**< \brief shared back buffer offset */
78    int           backPitch;     /**< \brief shared back buffer pitch */
79    int           depthOffset;   /**< \brief shared depth buffer offset */
80    int           depthPitch;    /**< \brief shared depth buffer pitch */
81    int           textureOffset; /**< \brief start of texture data in frame buffer */
82    int           textureSize;   /**< \brief size of texture date */
83    int           log2TexGran;   /**< \brief log2 texture granularity */
84    /*@}*/
85
86    /**
87     * \name MMIO register data
88     */
89    /*@{*/
90    drm_handle_t     registerHandle; /**< \brief MMIO register map size */
91    drmSize       registerSize;   /**< \brief MMIO register map handle */
92    /*@}*/
93
94    /**
95     * \name CP in-memory status information
96     */
97    /*@{*/
98    drm_handle_t     statusHandle;   /**< \brief status map handle */
99    drmSize       statusSize;     /**< \brief status map size */
100    /*@}*/
101
102    /**
103     * \name CP AGP Texture data
104     */
105    /*@{*/
106    drm_handle_t     gartTexHandle;   /**< \brief AGP texture area map handle */
107    drmSize       gartTexMapSize;  /**< \brief AGP texture area map size */
108    int           log2GARTTexGran; /**< \brief AGP texture granularity in log base 2 */
109    int           gartTexOffset;   /**< \brief AGP texture area offset in AGP space */
110    /*@}*/
111
112    unsigned int  sarea_priv_offset; /**< \brief offset of the private SAREA data*/
113} RADEONDRIRec, *RADEONDRIPtr;
114
115#endif
116