1f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* 2f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * VA Linux Systems Inc., Fremont, California. 4f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 5f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * All Rights Reserved. 6f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 7f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Permission is hereby granted, free of charge, to any person obtaining 8f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * a copy of this software and associated documentation files (the 9f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * "Software"), to deal in the Software without restriction, including 10f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * without limitation on the rights to use, copy, modify, merge, 11f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * publish, distribute, sublicense, and/or sell copies of the Software, 12f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * and to permit persons to whom the Software is furnished to do so, 13f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * subject to the following conditions: 14f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 15f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * The above copyright notice and this permission notice (including the 16f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * next paragraph) shall be included in all copies or substantial 17f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * portions of the Software. 18f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 19f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * DEALINGS IN THE SOFTWARE. 27f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 28f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 29f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* 30f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Authors: 31f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Kevin E. Martin <martin@xfree86.org> 32f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Rickard E. Faith <faith@valinux.com> 33f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Alan Hourihane <alanh@fairlite.demon.co.uk> 34f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 35f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * References: 36f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 37f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * !!!! FIXME !!!! 38f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 39f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 40f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 1999. 41f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 42f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * !!!! FIXME !!!! 43f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * RAGE 128 Software Development Manual (Technical Reference Manual P/N 44f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 45f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * 46f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org */ 47f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 48f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h 49f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT 50f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ 51f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 52f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#ifndef _RADEON_REG_H_ 53f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define _RADEON_REG_H_ 54f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 55f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Registers for 2D/Video/Overlay */ 56f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_ADAPTER_ID 0x0f2c /* PCI */ 57f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_BASE 0x0170 58f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_CNTL 0x0174 59f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0) 60f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0) 61f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0) 62f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0) 63f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0) 64f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0) 65f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0) 66f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0) 67f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_COMMAND 0x0f60 /* PCI */ 68f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ 69f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_ENABLE (1<<8) 70f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */ 71f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AGP_STATUS 0x0f5c /* PCI */ 72f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_1X_MODE 0x01 73f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_2X_MODE 0x02 74f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_4X_MODE 0x04 75f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_FW_MODE 0x10 76f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AGP_MODE_MASK 0x17 77f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_ATTRDR 0x03c1 /* VGA */ 78f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_ATTRDW 0x03c0 /* VGA */ 79f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_ATTRX 0x03c0 /* VGA */ 80f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX_SC_CNTL 0x1660 81f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX1_SC_EN (1 << 0) 82f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX1_SC_MODE_OR (0 << 1) 83f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX1_SC_MODE_NAND (1 << 1) 84f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX2_SC_EN (1 << 2) 85f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX2_SC_MODE_OR (0 << 3) 86f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX2_SC_MODE_NAND (1 << 3) 87f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX3_SC_EN (1 << 4) 88f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX3_SC_MODE_OR (0 << 5) 89f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AUX3_SC_MODE_NAND (1 << 5) 90f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX1_SC_BOTTOM 0x1670 91f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX1_SC_LEFT 0x1664 92f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX1_SC_RIGHT 0x1668 93f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX1_SC_TOP 0x166c 94f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX2_SC_BOTTOM 0x1680 95f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX2_SC_LEFT 0x1674 96f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX2_SC_RIGHT 0x1678 97f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX2_SC_TOP 0x167c 98f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX3_SC_BOTTOM 0x1690 99f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX3_SC_LEFT 0x1684 100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX3_SC_RIGHT 0x1688 101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX3_SC_TOP 0x168c 102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8 103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc 104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BASE_CODE 0x0f0b 106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_0_SCRATCH 0x0010 107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_1_SCRATCH 0x0014 108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_2_SCRATCH 0x0018 109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_3_SCRATCH 0x001c 110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_4_SCRATCH 0x0020 111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_5_SCRATCH 0x0024 112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_6_SCRATCH 0x0028 113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_7_SCRATCH 0x002c 114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIOS_ROM 0x0f30 /* PCI */ 115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BIST 0x0f0f /* PCI */ 116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA0 0x1480 117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA1 0x1484 118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA10 0x14a8 119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA11 0x14ac 120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA12 0x14b0 121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA13 0x14b4 122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA14 0x14b8 123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA15 0x14bc 124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA16 0x14c0 125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA17 0x14c4 126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA18 0x14c8 127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA19 0x14cc 128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA2 0x1488 129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA20 0x14d0 130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA21 0x14d4 131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA22 0x14d8 132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA23 0x14dc 133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA24 0x14e0 134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA25 0x14e4 135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA26 0x14e8 136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA27 0x14ec 137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA28 0x14f0 138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA29 0x14f4 139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA3 0x148c 140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA30 0x14f8 141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA31 0x14fc 142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA32 0x1500 143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA33 0x1504 144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA34 0x1508 145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA35 0x150c 146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA36 0x1510 147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA37 0x1514 148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA38 0x1518 149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA39 0x151c 150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA4 0x1490 151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA40 0x1520 152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA41 0x1524 153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA42 0x1528 154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA43 0x152c 155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA44 0x1530 156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA45 0x1534 157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA46 0x1538 158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA47 0x153c 159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA48 0x1540 160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA49 0x1544 161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA5 0x1494 162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA50 0x1548 163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA51 0x154c 164f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA52 0x1550 165f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA53 0x1554 166f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA54 0x1558 167f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA55 0x155c 168f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA56 0x1560 169f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA57 0x1564 170f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA58 0x1568 171f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA59 0x156c 172f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA6 0x1498 173f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA60 0x1570 174f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA61 0x1574 175f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA62 0x1578 176f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA63 0x157c 177f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA7 0x149c 178f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA8 0x14a0 179f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_DATA9 0x14a4 180f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_SCALE 0x1470 181f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BRUSH_Y_X 0x1474 182f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BUS_CNTL 0x0030 183f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_MASTER_DIS (1 << 6) 184f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_RD_DISCARD_EN (1 << 24) 185f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_RD_ABORT_EN (1 << 25) 186f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) 187f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_WRT_BURST (1 << 29) 188f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_READ_BURST (1 << 30) 189f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_BUS_CNTL1 0x0034 190f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 191f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 192f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CACHE_CNTL 0x1724 193f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CACHE_LINE 0x0f0c /* PCI */ 194f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CAP0_TRIG_CNTL 0x0950 /* ? */ 195f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CAP1_TRIG_CNTL 0x09c0 /* ? */ 196f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */ 197f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */ 198f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */ 199f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLOCK_CNTL_DATA 0x000c 200f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLOCK_CNTL_INDEX 0x0008 201f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PLL_WR_EN (1 << 7) 202f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PLL_DIV_SEL (3 << 8) 203f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8) 204f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_CLR_3D 0x1a24 205f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_CLR_DST 0x15c8 206f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_CLR_SRC 0x15c4 207f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_CNTL 0x15c0 208f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_CMP_EQ_COLOR (4 << 0) 209f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0) 210f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24) 211f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_MASK 0x15cc 212f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLR_CMP_MSK 0xffffffff 213f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CLR_CMP_MASK_3D 0x1A28 214f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_COMMAND 0x0f04 /* PCI */ 215f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c 216f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_APER_0_BASE 0x0100 217f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_APER_1_BASE 0x0104 218f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_APER_SIZE 0x0108 219f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_BONDS 0x00e8 220f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_CNTL 0x00e0 221f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CFG_ATI_REV_A11 (0 << 16) 222f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CFG_ATI_REV_A12 (1 << 16) 223f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CFG_ATI_REV_A13 (2 << 16) 224f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16) 225f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_MEMSIZE 0x00f8 226f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114 227f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_REG_1_BASE 0x010c 228f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_REG_APER_SIZE 0x0110 229f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONFIG_XSTRAP 0x00e4 230f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CONSTANT_COLOR_C 0x1d34 231f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff 232f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff 233f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CONSTANT_COLOR_ZERO 0x00000000 234f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRC_CMDFIFO_ADDR 0x0740 235f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRC_CMDFIFO_DOUT 0x0744 236f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GRPH_BUFFER_CNTL 0x02f0 237f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_START_REQ_MASK (0x7f) 238f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_START_REQ_SHIFT 0 239f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8) 240f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_STOP_REQ_SHIFT 8 241f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16) 242f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16 243f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_CRITICAL_CNTL (1<<28) 244f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_BUFFER_SIZE (1<<29) 245f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30) 246f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH_STOP_CNTL (1<<31) 247f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GRPH2_BUFFER_CNTL 0x03f0 248f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_START_REQ_MASK (0x7f) 249f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_START_REQ_SHIFT 0 250f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8) 251f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_STOP_REQ_SHIFT 8 252f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16) 253f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16 254f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_CRITICAL_CNTL (1<<28) 255f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_BUFFER_SIZE (1<<29) 256f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30) 257f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRPH2_STOP_CNTL (1<<31) 258f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_CRNT_FRAME 0x0214 259f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_EXT_CNTL 0x0054 260f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0) 261f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VGA_ATI_LINEAR (1 << 3) 262f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_XCRT_CNT_EN (1 << 6) 263f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_HSYNC_DIS (1 << 8) 264f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_VSYNC_DIS (1 << 9) 265f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_DISPLAY_DIS (1 << 10) 266f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_SYNC_TRISTAT (1 << 11) 267f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_CRT_ON (1 << 15) 268f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055 269f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0) 270f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1) 271f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2) 272f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_GEN_CNTL 0x0050 273f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_DBL_SCAN_EN (1 << 0) 274f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_INTERLACE_EN (1 << 1) 275f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_CSYNC_EN (1 << 4) 276f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_CUR_EN (1 << 16) 277f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_CUR_MODE_MASK (7 << 17) 278f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_ICON_EN (1 << 20) 279f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_EXT_DISP_EN (1 << 24) 280f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_EN (1 << 25) 281f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26) 282f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_GEN_CNTL 0x03f8 283f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0) 284f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_INTERLACE_EN (1 << 1) 285f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4) 286f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5) 287f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6) 288f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_CRT2_ON (1 << 7) 289f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_ICON_EN (1 << 15) 290f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_CUR_EN (1 << 16) 291f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20) 292f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_DISP_DIS (1 << 23) 293f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_EN (1 << 25) 294f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26) 295f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_CSYNC_EN (1 << 27) 296f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_HSYNC_DIS (1 << 28) 297f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_VSYNC_DIS (1 << 29) 298f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_MORE_CNTL 0x27c 299f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 300f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 301f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218 302f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204 303f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0) 304f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) 305f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3 306f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_WID (0x3f << 16) 307f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_WID_SHIFT 16 308f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_SYNC_POL (1 << 23) 309f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304 310f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 311f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) 312f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 313f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16) 314f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16 315f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_SYNC_POL (1 << 23) 316f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_H_TOTAL_DISP 0x0200 317f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_TOTAL (0x03ff << 0) 318f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_TOTAL_SHIFT 0 319f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_DISP (0x01ff << 16) 320f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_H_DISP_SHIFT 16 321f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_H_TOTAL_DISP 0x0300 322f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_TOTAL (0x03ff << 0) 323f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_TOTAL_SHIFT 0 324f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_DISP (0x01ff << 16) 325f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_H_DISP_SHIFT 16 326f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_OFFSET 0x0224 327f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_OFFSET 0x0324 328f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_OFFSET_CNTL 0x0228 329f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_TILE_EN (1 << 15) 330f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_OFFSET_CNTL 0x0328 331f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_TILE_EN (1 << 15) 332f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_PITCH 0x022c 333f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_PITCH 0x032c 334f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_STATUS 0x005c 335f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_VBLANK_SAVE (1 << 1) 336f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1) 337f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_STATUS 0x03fc 338f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_VBLANK_SAVE (1 << 1) 339f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) 340f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c 341f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0) 342f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0 343f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_SYNC_WID (0x1f << 16) 344f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_SYNC_WID_SHIFT 16 345f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_SYNC_POL (1 << 23) 346f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c 347f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0) 348f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0 349f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16) 350f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16 351f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_SYNC_POL (1 << 23) 352f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_V_TOTAL_DISP 0x0208 353f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_TOTAL (0x07ff << 0) 354f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_TOTAL_SHIFT 0 355f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_DISP (0x07ff << 16) 356f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_V_DISP_SHIFT 16 357f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_V_TOTAL_DISP 0x0308 358f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_TOTAL (0x07ff << 0) 359f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_TOTAL_SHIFT 0 360f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_DISP (0x07ff << 16) 361f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC2_V_DISP_SHIFT 16 362f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210 363f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16) 364f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_CRNT_FRAME 0x0314 365f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318 366f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_STATUS 0x03fc 367f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310 368f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 369f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 370f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR_CLR0 0x026c 371f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR_CLR1 0x0270 372f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR_HORZ_VERT_OFF 0x0268 373f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR_HORZ_VERT_POSN 0x0264 374f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR_OFFSET 0x0260 375f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CUR_LOCK (1 << 31) 376f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR2_CLR0 0x036c 377f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR2_CLR1 0x0370 378f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR2_HORZ_VERT_OFF 0x0368 379f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR2_HORZ_VERT_POSN 0x0364 380f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CUR2_OFFSET 0x0360 381f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CUR2_LOCK (1 << 31) 382f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 383f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_CNTL 0x0058 384f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_RANGE_CNTL (3 << 0) 385f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_RANGE_CNTL_MASK 0x03 386f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_BLANKING (1 << 2) 387f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_CMP_EN (1 << 3) 388f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_CMP_OUTPUT (1 << 7) 389f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_8BIT_EN (1 << 8) 390f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_VGA_ADR_EN (1 << 13) 391f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_PDWN (1 << 15) 392f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_MASK_ALL (0xff << 24) 393f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_CNTL2 0x007c 394f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC2_DAC_CLK_SEL (1 << 0) 395f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1) 396f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5) 397f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_EXT_CNTL 0x0280 398f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4) 399f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_FORCE_DATA_EN (1 << 5) 400f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6) 401f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00 402f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DAC_FORCE_DATA_SHIFT 8 403f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TV_DAC_CNTL 0x088c 404f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_DAC_STD_MASK 0x0300 405f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_DAC_RDACPD (1 << 24) 406f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_DAC_GDACPD (1 << 25) 407f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_DAC_BDACPD (1 << 26) 408f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_HW_DEBUG 0x0d14 409f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CRT2_DISP1_SEL (1 << 5) 410f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_OUTPUT_CNTL 0x0d64 411f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_DAC_SOURCE_MASK 0x03 412f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c 413f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01 414f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04 415f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_CRC_SIG 0x02cc 416f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_DATA 0x03c9 /* VGA */ 417f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_MASK 0x03c6 /* VGA */ 418f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */ 419f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */ 420f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DDA_CONFIG 0x02e0 421f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DDA_ON_OFF 0x02e4 422f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DEFAULT_OFFSET 0x16e0 423f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DEFAULT_PITCH 0x16e4 424f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8 425f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 426f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 427f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820 428f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824 429f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DEVICE_ID 0x0f02 /* PCI */ 430f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_MISC_CNTL 0x0d00 431f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_GRPH_PP (1 << 0) 432f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_MERGE_CNTL 0x0d60 433f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_ALPHA_MODE_MASK 0x03 434f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_ALPHA_MODE_KEY 0 435f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1 436f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_ALPHA_MODE_GLOBAL 2 437f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_RGB_OFFSET_EN (1<<8) 438f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16) 439f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24) 440f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9) 441f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP2_MERGE_CNTL 0x0d68 442f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DISP2_RGB_OFFSET_EN (1<<8) 443f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80 444f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84 445f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88 446f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c 447f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90 448f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98 449f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_BRUSH_BKGD_CLR 0x1478 450f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_BRUSH_FRGD_CLR 0x147c 451f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_CNTL 0x16c0 452f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0) 453f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1) 454f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 455f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_Y_MAJOR (1 << 2) 456f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 457f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 458f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_DATATYPE 0x16c4 459f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29) 460f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_GUI_MASTER_CNTL 0x146c 461f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 462f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 463f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_CLIPPING (1 << 2) 464f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_CLIPPING (1 << 3) 465f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 466f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 467f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 468f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 469f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 470f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 471f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 472f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 473f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 474f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4) 475f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4) 476f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4) 477f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BRUSH_NONE (15 << 4) 478f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_8BPP_CI (2 << 8) 479f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_15BPP (3 << 8) 480f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_16BPP (4 << 8) 481f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_24BPP (5 << 8) 482f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_32BPP (6 << 8) 483f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_8BPP_RGB (7 << 8) 484f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_Y8 (8 << 8) 485f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_RGB8 (9 << 8) 486f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_VYUY (11 << 8) 487f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_YVYU (12 << 8) 488f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_AYUV444 (14 << 8) 489f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_ARGB4444 (15 << 8) 490f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8) 491f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_DST_DATATYPE_SHIFT 8 492f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12) 493f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 494f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 495f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12) 496f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14) 497f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14) 498f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14) 499f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_CONVERSION_TEMP (1 << 15) 500f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15) 501f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15) 502f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_ROP3_MASK (0xff << 16) 503f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DP_SRC_SOURCE_MASK (7 << 24) 504f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24) 505f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24) 506f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_3D_FCN_EN (1 << 27) 507f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28) 508f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_AUX_CLIP_DIS (1 << 29) 509f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_WR_MSK_DIS (1 << 30) 510f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31) 511f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_ZERO 0x00000000 512f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSa 0x00880000 513f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_SDna 0x00440000 514f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_S 0x00cc0000 515f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSna 0x00220000 516f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_D 0x00aa0000 517f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSx 0x00660000 518f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSo 0x00ee0000 519f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSon 0x00110000 520f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSxn 0x00990000 521f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_Dn 0x00550000 522f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_SDno 0x00dd0000 523f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_Sn 0x00330000 524f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSno 0x00bb0000 525f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DSan 0x00770000 526f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_ONE 0x00ff0000 527f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPa 0x00a00000 528f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_PDna 0x00500000 529f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_P 0x00f00000 530f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPna 0x000a0000 531f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_D 0x00aa0000 532f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPx 0x005a0000 533f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPo 0x00fa0000 534f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPon 0x00050000 535f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_PDxn 0x00a50000 536f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_PDno 0x00f50000 537f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_Pn 0x000f0000 538f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPno 0x00af0000 539f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP3_DPan 0x005f0000 540f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84 541f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_MIX 0x16c8 542f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_SRC_BKGD_CLR 0x15dc 543f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_SRC_FRGD_CLR 0x15d8 544f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DP_WRITE_MASK 0x16cc 545f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_BRES_DEC 0x1630 546f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_BRES_ERR 0x1628 547f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_BRES_INC 0x162c 548f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_BRES_LNTH 0x1634 549f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_BRES_LNTH_SUB 0x1638 550f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_HEIGHT 0x1410 551f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_HEIGHT_WIDTH 0x143c 552f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_HEIGHT_WIDTH_8 0x158c 553f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4 554f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_HEIGHT_Y 0x15a0 555f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_LINE_START 0x1600 556f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_LINE_END 0x1604 557f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_LINE_PATCOUNT 0x1608 558f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BRES_CNTL_SHIFT 8 559f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_OFFSET 0x1404 560f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_PITCH 0x1408 561f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_PITCH_OFFSET 0x142c 562f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_PITCH_OFFSET_C 0x1c80 563f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PITCH_SHIFT 21 564f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_TILE_LINEAR (0 << 30) 565f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_TILE_MACRO (1 << 30) 566f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_TILE_MICRO (2 << 30) 567f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_TILE_BOTH (3 << 30) 568f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_WIDTH 0x140c 569f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_WIDTH_HEIGHT 0x1598 570f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_WIDTH_X 0x1588 571f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_WIDTH_X_INCY 0x159c 572f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_X 0x141c 573f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_X_SUB 0x15a4 574f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_X_Y 0x1594 575f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_Y 0x1420 576f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_Y_SUB 0x15a8 577f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DST_Y_X 0x1438 578f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 579f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FCP_CNTL 0x0910 580f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_PCICLK 0 581f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_PCLK 1 582f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_PCLKb 2 583f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_HREF 3 584f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_GND 4 585f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FCP0_SRC_HREFb 5 586f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_1 0x1704 587f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_2 0x1708 588f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_3 0x170c 589f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_4 0x1710 590f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_5 0x1714 591f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_6 0x1718 592f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FLUSH_7 0x171c 593f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FOG_3D_TABLE_START 0x1810 594f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FOG_3D_TABLE_END 0x1814 595f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FOG_3D_TABLE_DENSITY 0x181c 596f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FOG_TABLE_INDEX 0x1a14 597f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FOG_TABLE_DATA 0x1a18 598f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250 599f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254 600f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350 601f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354 602f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff 603f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000 604f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff 605f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000 606f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 607f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000 608f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff 609f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000 610f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000 611f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010 612f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000 613f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010 614f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 615f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010 616f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000 617f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010 618f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_GEN_CNTL 0x0284 619f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_FPON (1 << 0) 620f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_TMDS_EN (1 << 2) 621f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_PANEL_FORMAT (1 << 3) 622f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_EN_TMDS (1 << 7) 623f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_DETECT_SENSE (1 << 8) 624f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_SEL_CRTC2 (1 << 13) 625f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 626f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 627f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17) 628f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18) 629f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 630f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_DFP_SYNC_SEL (1 << 21) 631f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22) 632f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRT_SYNC_SEL (1 << 23) 633f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_USE_SHADOW_EN (1 << 24) 634f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP_CRT_SYNC_ALT (1 << 26) 635f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP2_GEN_CNTL 0x0288 636f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_BLANK_EN (1 << 1) 637f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_ON (1 << 2) 638f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_PANEL_FORMAT (1 << 3) 639f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_SOURCE_SEL_MASK (3 << 10) 640f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10) 641f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_SRC_SEL_MASK (3 << 13) 642f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13) 643f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_FP_POL (1 << 16) 644f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_LP_POL (1 << 17) 645f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_SCK_POL (1 << 18) 646f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_LCD_CNTL_MASK (7 << 19) 647f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_PAD_FLOP_EN (1 << 22) 648f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_CRC_EN (1 << 23) 649f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_CRC_READ_EN (1 << 24) 650f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_DV0_EN (1 << 25) 651f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26) 652f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_H_SYNC_STRT_WID 0x02c4 653f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4 654f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_HORZ_STRETCH 0x028c 655f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_HORZ2_STRETCH 0x038c 656f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff 657f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_STRETCH_RATIO_MAX 4096 658f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16) 659f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_PANEL_SHIFT 16 660f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_STRETCH_PIXREP (0 << 25) 661f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_STRETCH_BLEND (1 << 26) 662f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_STRETCH_ENABLE (1 << 25) 663f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_AUTO_RATIO (1 << 27) 664f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28) 665f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31) 666f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_V_SYNC_STRT_WID 0x02c8 667f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_VERT_STRETCH 0x0290 668f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8 669f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_FP_VERT2_STRETCH 0x0390 670f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_PANEL_SIZE (0xfff << 12) 671f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_PANEL_SHIFT 12 672f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff 673f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_RATIO_SHIFT 0 674f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_RATIO_MAX 4096 675f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_ENABLE (1 << 25) 676f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_LINEREP (0 << 26) 677f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_BLEND (1 << 26) 678f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_AUTO_RATIO_EN (1 << 27) 679f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERT_STRETCH_RESERVED 0xf1000000 680f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 681f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GEN_INT_CNTL 0x0040 682f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GEN_INT_STATUS 0x0044 683f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VSYNC_INT_AK (1 << 2) 684f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VSYNC_INT (1 << 2) 685f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VSYNC2_INT_AK (1 << 6) 686f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VSYNC2_INT (1 << 6) 687f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENENB 0x03c3 /* VGA */ 688f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENFC_RD 0x03ca /* VGA */ 689f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */ 690f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENMO_RD 0x03cc /* VGA */ 691f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENMO_WT 0x03c2 /* VGA */ 692f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENS0 0x03c2 /* VGA */ 693f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GENS1 0x03da /* VGA, 0x03ba */ 694f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ 695f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GPIO_MONIDB 0x006c 696f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GPIO_CRT2_DDC 0x006c 697f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GPIO_DVI_DDC 0x0064 698f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GPIO_VGA_DDC 0x0060 699f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_A_0 (1 << 0) 700f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_A_1 (1 << 1) 701f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_Y_0 (1 << 8) 702f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_Y_1 (1 << 9) 703f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_Y_SHIFT_0 8 704f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_Y_SHIFT_1 9 705f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_EN_0 (1 << 16) 706f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_EN_1 (1 << 17) 707f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/ 708f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/ 709f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GRPH8_DATA 0x03cf /* VGA */ 710f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GRPH8_IDX 0x03ce /* VGA */ 711f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG0 0x15e0 712f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG1 0x15e4 713f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG2 0x15e8 714f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG3 0x15ec 715f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG4 0x15f0 716f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_GUI_SCRATCH_REG5 0x15f4 717f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 718f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HEADER 0x0f0e /* PCI */ 719f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA0 0x17c0 720f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA1 0x17c4 721f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA2 0x17c8 722f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA3 0x17cc 723f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA4 0x17d0 724f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA5 0x17d4 725f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA6 0x17d8 726f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA7 0x17dc 727f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_DATA_LAST 0x17e0 728f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HOST_PATH_CNTL 0x0130 729f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HDP_SOFT_RESET (1 << 26) 730f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */ 731f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */ 732f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 733f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_I2C_CNTL_1 0x0094 /* ? */ 734f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DVI_I2C_CNTL_1 0x02e4 /* ? */ 735f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */ 736f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */ 737f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_IO_BASE 0x0f14 /* PCI */ 738f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 739f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LATENCY 0x0f0d /* PCI */ 740f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LEAD_BRES_DEC 0x1608 741f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LEAD_BRES_LNTH 0x161c 742f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LEAD_BRES_LNTH_SUB 0x1624 743f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LVDS_GEN_CNTL 0x02d0 744f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_ON (1 << 0) 745f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_DISPLAY_DIS (1 << 1) 746f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_PANEL_TYPE (1 << 2) 747f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_PANEL_FORMAT (1 << 3) 748f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_EN (1 << 7) 749f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_DIGON (1 << 18) 750f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_BLON (1 << 19) 751f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LVDS_SEL_CRTC2 (1 << 23) 752f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LVDS_PLL_CNTL 0x02d4 753f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HSYNC_DELAY_SHIFT 28 754f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HSYNC_DELAY_MASK (0xf << 28) 755f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 756f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MAX_LATENCY 0x0f3f /* PCI */ 757f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MC_AGP_LOCATION 0x014c 758f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MC_FB_LOCATION 0x0148 759f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISPLAY_BASE_ADDR 0x23c 760f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_DISPLAY2_BASE_ADDR 0x33c 761f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_BASE_ADDR 0x43c 762f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_NB_TOM 0x15c 763f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MCLK_CNTL 0x0012 /* PLL */ 764f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_MCLKA (1 << 16) 765f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_MCLKB (1 << 17) 766f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_YCLKA (1 << 18) 767f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_YCLKB (1 << 19) 768f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_MC (1 << 20) 769f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCEON_AIC (1 << 21) 770f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MDGPIO_A_REG 0x01ac 771f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MDGPIO_EN_REG 0x01b0 772f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MDGPIO_MASK 0x0198 773f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MDGPIO_Y_REG 0x01b4 774f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_ADDR_CONFIG 0x0148 775f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_BASE 0x0f10 /* PCI */ 776f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_CNTL 0x0140 777f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MEM_NUM_CHANNELS_MASK 0x01 778f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MEM_USE_B_CH_ONLY (1<<1) 779f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RV100_HALF_MODE (1<<3) 780f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ 781f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_INIT_LAT_TIMER 0x0154 782f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_INTF_CNTL 0x014c 783f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_SDRAM_MODE_REG 0x0158 784f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_STR_CNTL 0x0150 785f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_VGA_RP_SEL 0x003c 786f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MEM_VGA_WP_SEL 0x0038 787f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MIN_GRANT 0x0f3e /* PCI */ 788f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MM_DATA 0x0004 789f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MM_INDEX 0x0000 790f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MPLL_CNTL 0x000e /* PLL */ 791f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */ 792f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */ 793f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 794f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_N_VIF_COUNT 0x0248 795f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 796f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470 797f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_COLOUR_CNTL 0x04E0 798f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474 799f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408 800f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_HORZ_START_MASK 0x000000ff 801f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00 802f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 803f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000 804f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_EXCLUSIVE_VERT 0x040C 805f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_VERT_START_MASK 0x000003ff 806f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EXCL_VERT_END_MASK 0x03ff0000 807f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FILTER_CNTL 0x04A0 808f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0 809f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4 810f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8 811f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC 812f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0 813f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_000_00F 0x0d40 814f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_010_01F 0x0d44 815f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_020_03F 0x0d48 816f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_040_07F 0x0d4c 817f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_080_0BF 0x0e00 818f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04 819f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_100_13F 0x0e08 820f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_140_17F 0x0e0c 821f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_180_1BF 0x0e10 822f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14 823f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_200_23F 0x0e18 824f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_240_27F 0x0e1c 825f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_280_2BF 0x0e20 826f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24 827f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_300_33F 0x0e28 828f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_340_37F 0x0e2c 829f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_380_3BF 0x0d50 830f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54 831f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC 832f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0 833f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_H_INC 0x0480 834f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_KEY_CNTL 0x04F4 835f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L 836f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L 837f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L 838f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L 839f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIDEO_KEY_FN_NE 0x00000003L 840f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L 841f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L 842f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L 843f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L 844f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L 845f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CMP_MIX_MASK 0x00000100L 846f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CMP_MIX_OR 0x00000000L 847f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CMP_MIX_AND 0x00000100L 848f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_A 0x0d20 849f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_B 0x0d24 850f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_C 0x0d28 851f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_D 0x0d2c 852f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_E 0x0d30 853f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_LIN_TRANS_F 0x0d34 854f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430 855f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL 856f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L 857f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488 858f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428 859f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L 860f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L 861f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P1_X_START_END 0x0494 862f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P2_X_START_END 0x0498 863f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434 864f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL 865f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L 866f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C 867f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C 868f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_P3_X_START_END 0x049C 869f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_REG_LOAD_CNTL 0x0410 870f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_REG_LD_CTL_LOCK 0x00000001L 871f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L 872f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L 873f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L 874f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_SCALE_CNTL 0x0420 875f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L 876f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L 877f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SIGNED_UV 0x00000010L 878f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L 879f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L 880f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L 881f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L 882f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L 883f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L 884f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L 885f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_15BPP 0x00000300L 886f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_16BPP 0x00000400L 887f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_32BPP 0x00000600L 888f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_YUV9 0x00000900L 889f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L 890f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L 891f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L 892f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 893f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L 894f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SMART_SWITCH 0x00008000L 895f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L 896f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L 897f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_DIS_LIMIT 0x08000000L 898f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_INT_EMU 0x20000000L 899f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_ENABLE 0x40000000L 900f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_SOFT_RESET 0x80000000L 901f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L 902f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_STEP_BY 0x0484 903f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_TEST 0x04F8 904f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_V_INC 0x0424 905f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460 906f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464 907f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440 908f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L 909f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L 910f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L 911f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L 912f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444 913f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L 914f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L 915f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L 916f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L 917f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448 918f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L 919f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L 920f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L 921f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L 922f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C 923f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450 924f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454 925f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8 926f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4 927f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_Y_X_START 0x0400 928f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV0_Y_X_END 0x0404 929f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV1_Y_X_START 0x0600 930f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OV1_Y_X_END 0x0604 931f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OVR_CLR 0x0230 932f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OVR_WID_LEFT_RIGHT 0x0234 933f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_OVR_WID_TOP_BOTTOM 0x0238 934f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 935f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */ 936f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_RESET (1 << 0) 937f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_SLEEP (1 << 1) 938f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16) 939f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 940f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 941f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_P2PLL_DIV_0 0x002c 942f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff 943f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000 944f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */ 945f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_REF_DIV_MASK 0x03ff 946f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 947f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 948f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PALETTE_DATA 0x00b4 949f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PALETTE_30_DATA 0x00b8 950f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PALETTE_INDEX 0x00b0 951f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PCI_GART_PAGE 0x017c 952f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PIXCLKS_CNTL 0x002d 953f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03 954f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00 955f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01 956f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02 957f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03 958f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6) 959f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7) 960f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8) 961f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 962f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 963f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PLANE_3D_MASK_C 0x1d44 964f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */ 965f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */ 966f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_DATA 0x0f63 /* PCI */ 967f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 968f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */ 969f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */ 970f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PMI_REGISTER 0x0f5c /* PCI */ 971f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_CNTL 0x0002 /* PLL */ 972f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_RESET (1 << 0) 973f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_SLEEP (1 << 1) 974f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16) 975f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 976f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 977f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_DIV_0 0x0004 /* PLL */ 978f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_DIV_1 0x0005 /* PLL */ 979f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_DIV_2 0x0006 /* PLL */ 980f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_DIV_3 0x0007 /* PLL */ 981f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_FB3_DIV_MASK 0x07ff 982f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_POST3_DIV_MASK 0x00070000 983f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */ 984f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_REF_DIV_MASK 0x03ff 985f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 986f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 987f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 988f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 989f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RBBM_GUICNTL 0x172c 990f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HOST_DATA_SWAP_NONE (0 << 0) 991f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0) 992f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0) 993f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_HOST_DATA_SWAP_HDW (3 << 0) 994f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RBBM_SOFT_RESET 0x00f0 995f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_CP (1 << 0) 996f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_HI (1 << 1) 997f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_SE (1 << 2) 998f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_RE (1 << 3) 999f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_PP (1 << 4) 1000f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_E2 (1 << 5) 1001f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_RB (1 << 6) 1002f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SOFT_RESET_HDP (1 << 7) 1003f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RBBM_STATUS 0x0e40 1004f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RBBM_FIFOCNT_MASK 0x007f 1005f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RBBM_ACTIVE (1 << 31) 1006f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c 1007f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RB2D_DC_FLUSH (3 << 0) 1008f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RB2D_DC_FREE (3 << 2) 1009f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RB2D_DC_FLUSH_ALL 0xf 1010f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RB2D_DC_BUSY (1 << 31) 1011f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB2D_DSTCACHE_MODE 0x3428 1012f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_REG_BASE 0x0f18 /* PCI */ 1013f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_REGPROG_INF 0x0f09 /* PCI */ 1014f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_REVISION_ID 0x0f08 /* PCI */ 1015f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1016f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_BOTTOM 0x164c 1017f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_BOTTOM_RIGHT 0x16f0 1018f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c 1019f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_LEFT 0x1640 1020f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_RIGHT 0x1644 1021f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_TOP 0x1648 1022f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_TOP_LEFT 0x16ec 1023f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SC_TOP_LEFT_C 0x1c88 1024f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SC_SIGN_MASK_LO 0x8000 1025f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SC_SIGN_MASK_HI 0x80000000 1026f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SCLK_CNTL 0x000d /* PLL */ 1027f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8 1028f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008 1029f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCLK_FORCEON_MASK 0xffff8000 1030f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */ 1031f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCLK_MORE_FORCEON 0x0700 1032f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SDRAM_MODE_REG 0x0158 1033f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SEQ8_DATA 0x03c5 /* VGA */ 1034f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SEQ8_IDX 0x03c4 /* VGA */ 1035f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SNAPSHOT_F_COUNT 0x0244 1036f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SNAPSHOT_VH_COUNTS 0x0240 1037f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SNAPSHOT_VIF_COUNT 0x024c 1038f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_OFFSET 0x15ac 1039f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_PITCH 0x15b0 1040f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_PITCH_OFFSET 0x1428 1041f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_SC_BOTTOM 0x165c 1042f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4 1043f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_SC_RIGHT 0x1654 1044f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_X 0x1414 1045f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_X_Y 0x1590 1046f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_Y 0x1418 1047f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SRC_Y_X 0x1434 1048f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_STATUS 0x0f06 /* PCI */ 1049f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SUBPIC_CNTL 0x0540 /* ? */ 1050f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SUB_CLASS 0x0f0a /* PCI */ 1051f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE_CNTL 0x0b00 1052f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_TRANSLATION_DIS (1 << 8) 1053f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) 1054f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) 1055f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE0_INFO 0x0b0c 1056f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16) 1057f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16) 1058f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16) 1059f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16) 1060f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_NONE (0 << 16) 1061f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_COLOR_MACRO (1 << 16) 1062f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_COLOR_MICRO (2 << 16) 1063f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_COLOR_BOTH (3 << 16) 1064f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_DEPTH_32BPP (4 << 16) 1065f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define R200_SURF_TILE_DEPTH_16BPP (5 << 16) 1066f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_AP0_SWP_16BPP (1 << 20) 1067f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_AP0_SWP_32BPP (1 << 21) 1068f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_AP1_SWP_16BPP (1 << 22) 1069f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SURF_AP1_SWP_32BPP (1 << 23) 1070f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE0_LOWER_BOUND 0x0b04 1071f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE0_UPPER_BOUND 0x0b08 1072f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE1_INFO 0x0b1c 1073f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE1_LOWER_BOUND 0x0b14 1074f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE1_UPPER_BOUND 0x0b18 1075f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE2_INFO 0x0b2c 1076f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE2_LOWER_BOUND 0x0b24 1077f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE2_UPPER_BOUND 0x0b28 1078f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE3_INFO 0x0b3c 1079f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE3_LOWER_BOUND 0x0b34 1080f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE3_UPPER_BOUND 0x0b38 1081f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE4_INFO 0x0b4c 1082f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE4_LOWER_BOUND 0x0b44 1083f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE4_UPPER_BOUND 0x0b48 1084f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE5_INFO 0x0b5c 1085f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE5_LOWER_BOUND 0x0b54 1086f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE5_UPPER_BOUND 0x0b58 1087f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE6_INFO 0x0b6c 1088f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE6_LOWER_BOUND 0x0b64 1089f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE6_UPPER_BOUND 0x0b68 1090f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE7_INFO 0x0b7c 1091f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE7_LOWER_BOUND 0x0b74 1092f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SURFACE7_UPPER_BOUND 0x0b78 1093f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SW_SEMAPHORE 0x013c 1094f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1095f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TEST_DEBUG_CNTL 0x0120 1096f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TEST_DEBUG_MUX 0x0124 1097f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TEST_DEBUG_OUT 0x012c 1098f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TMDS_PLL_CNTL 0x02a8 1099f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4 1100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TMDS_TRANSMITTER_PLLEN 1 1101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TMDS_TRANSMITTER_PLLRST 2 1102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TRAIL_BRES_DEC 0x1614 1103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TRAIL_BRES_ERR 0x160c 1104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TRAIL_BRES_INC 0x1610 1105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TRAIL_X 0x1618 1106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TRAIL_X_SUB 0x1620 1107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */ 1109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VCLK_SRC_SEL_MASK 0x03 1110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00 1111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01 1112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02 1113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03 1114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIXCLK_ALWAYS_ONb (1<<6) 1115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7) 1116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VENDOR_ID 0x0f00 /* PCI */ 1118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VGA_DDA_CONFIG 0x02e8 1119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VGA_DDA_ON_OFF 0x02ec 1120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VID_BUFFER_CONTROL 0x0900 1121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VIDEOMUX_CNTL 0x0190 1122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VIPH_CONTROL 0x0c40 /* ? */ 1123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_WAIT_UNTIL 0x1720 1125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WAIT_CRTC_PFLIP (1 << 0) 1126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WAIT_2D_IDLECLEAN (1 << 16) 1127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WAIT_3D_IDLECLEAN (1 << 17) 1128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) 1129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_XCLK_CNTL 0x000d /* PLL */ 1132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_XDLL_CNTL 0x000c /* PLL */ 1133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_XPLL_CNTL 0x000b /* PLL */ 1134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Registers for 3D/TCL */ 1138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_BORDER_COLOR_0 0x1d40 1139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_BORDER_COLOR_1 0x1d44 1140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_BORDER_COLOR_2 0x1d48 1141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CNTL 0x1c38 1142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_ENABLE (1 << 0) 1143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCISSOR_ENABLE (1 << 1) 1144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PATTERN_ENABLE (1 << 2) 1145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_ENABLE (1 << 3) 1146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_ENABLE_MASK (0xf << 4) 1147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_0_ENABLE (1 << 4) 1148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_1_ENABLE (1 << 5) 1149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_2_ENABLE (1 << 6) 1150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_3_ENABLE (1 << 7) 1151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12) 1152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_BLEND_0_ENABLE (1 << 12) 1153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_BLEND_1_ENABLE (1 << 13) 1154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_BLEND_2_ENABLE (1 << 14) 1155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_BLEND_3_ENABLE (1 << 15) 1156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PLANAR_YUV_ENABLE (1 << 20) 1157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_ENABLE (1 << 21) 1158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_ENABLE (1 << 22) 1159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_ENABLE (1 << 23) 1160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ANTI_ALIAS_NONE (0 << 24) 1161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ANTI_ALIAS_LINE (1 << 24) 1162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ANTI_ALIAS_POLY (2 << 24) 1163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24) 1164f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUMP_MAP_ENABLE (1 << 26) 1165f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUMPED_MAP_T0 (0 << 27) 1166f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUMPED_MAP_T1 (1 << 27) 1167f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BUMPED_MAP_T2 (2 << 27) 1168f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_3D_ENABLE_0 (1 << 29) 1169f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_3D_ENABLE_1 (1 << 30) 1170f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MC_ENABLE (1 << 31) 1171f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_FOG_COLOR 0x1c18 1172f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_COLOR_MASK 0x00ffffff 1173f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_VERTEX (0 << 24) 1174f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_TABLE (1 << 24) 1175f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_USE_DEPTH (0 << 25) 1176f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25) 1177f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25) 1178f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_LUM_MATRIX 0x1d00 1179f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_MISC 0x1c14 1180f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_REF_ALPHA_MASK 0x000000ff 1181f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_FAIL (0 << 8) 1182f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_LESS (1 << 8) 1183f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_LEQUAL (2 << 8) 1184f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_EQUAL (3 << 8) 1185f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_GEQUAL (4 << 8) 1186f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_GREATER (5 << 8) 1187f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_NEQUAL (6 << 8) 1188f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_PASS (7 << 8) 1189f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_TEST_OP_MASK (7 << 8) 1190f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_FUNC_FAIL (0 << 16) 1191f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_FUNC_PASS (1 << 16) 1192f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16) 1193f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_FUNC_EQUAL (3 << 16) 1194f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_KEY_NEAREST (0 << 18) 1195f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CHROMA_KEY_ZERO (1 << 18) 1196f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_ID_AUTO_INC (1 << 20) 1197f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_FUNC_EQUAL (0 << 21) 1198f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21) 1199f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_PASS_1 (0 << 22) 1200f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SHADOW_PASS_2 (1 << 22) 1201f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24) 1202f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24) 1203f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_ROT_MATRIX_0 0x1d58 1204f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_ROT_MATRIX_1 0x1d5c 1205f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFILTER_0 0x1c54 1206f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFILTER_1 0x1c6c 1207f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFILTER_2 0x1c84 1208f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAG_FILTER_NEAREST (0 << 0) 1209f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAG_FILTER_LINEAR (1 << 0) 1210f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAG_FILTER_MASK (1 << 0) 1211f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_NEAREST (0 << 1) 1212f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_LINEAR (1 << 1) 1213f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 1214f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 1215f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 1216f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 1217f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1) 1218f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1) 1219f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 1220f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 1221f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MIN_FILTER_MASK (15 << 1) 1222f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_1_TO_1 (0 << 5) 1223f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_2_TO_1 (1 << 5) 1224f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_4_TO_1 (2 << 5) 1225f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_8_TO_1 (3 << 5) 1226f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_16_TO_1 (4 << 5) 1227f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_ANISO_MASK (7 << 5) 1228f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LOD_BIAS_MASK (0xff << 8) 1229f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LOD_BIAS_SHIFT 8 1230f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16) 1231f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MAX_MIP_LEVEL_SHIFT 16 1232f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_YUV_TO_RGB (1 << 20) 1233f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_YUV_TEMPERATURE_COOL (0 << 21) 1234f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_YUV_TEMPERATURE_HOT (1 << 21) 1235f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_YUV_TEMPERATURE_MASK (1 << 21) 1236f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WRAPEN_S (1 << 22) 1237f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_WRAP (0 << 23) 1238f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_MIRROR (1 << 23) 1239f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23) 1240f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 1241f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23) 1242f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 1243f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_CLAMP_GL (6 << 23) 1244f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 1245f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_S_MASK (7 << 23) 1246f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WRAPEN_T (1 << 26) 1247f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_WRAP (0 << 27) 1248f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_MIRROR (1 << 27) 1249f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27) 1250f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 1251f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27) 1252f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 1253f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_CLAMP_GL (6 << 27) 1254f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 1255f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_T_MASK (7 << 27) 1256f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BORDER_MODE_OGL (0 << 31) 1257f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BORDER_MODE_D3D (1 << 31) 1258f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFORMAT_0 0x1c58 1259f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFORMAT_1 0x1c70 1260f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXFORMAT_2 0x1c88 1261f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_I8 (0 << 0) 1262f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_AI88 (1 << 0) 1263f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_RGB332 (2 << 0) 1264f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ARGB1555 (3 << 0) 1265f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_RGB565 (4 << 0) 1266f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ARGB4444 (5 << 0) 1267f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ARGB8888 (6 << 0) 1268f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_RGBA8888 (7 << 0) 1269f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_Y8 (8 << 0) 1270f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_VYUY422 (10 << 0) 1271f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_YVYU422 (11 << 0) 1272f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_DXT1 (12 << 0) 1273f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_DXT23 (14 << 0) 1274f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_DXT45 (15 << 0) 1275f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_SHADOW16 (16 << 0) 1276f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_SHADOW32 (17 << 0) 1277f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_DUDV88 (18 << 0) 1278f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_LDUDV655 (19 << 0) 1279f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0) 1280f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0) 1281f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_FORMAT_SHIFT 0 1282f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5) 1283f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6) 1284f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_NON_POWER2 (1 << 7) 1285f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8) 1286f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_WIDTH_SHIFT 8 1287f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12) 1288f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_HEIGHT_SHIFT 12 1289f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16) 1290f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16 1291f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 1292f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20 1293f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 1294f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24) 1295f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 1296f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 1297f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26) 1298f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) 1299f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) 1300f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) 1301f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 1302f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 1303f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 1304f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) 1305f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_FACES_0 0x1d24 1306f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_FACES_1 0x1d28 1307f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_FACES_2 0x1d2c 1308f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_1_SHIFT 0 1309f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_1_SHIFT 4 1310f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_1_MASK (0xf << 0) 1311f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4) 1312f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_2_SHIFT 8 1313f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_2_SHIFT 12 1314f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_2_MASK (0xf << 8) 1315f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12) 1316f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_3_SHIFT 16 1317f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_3_SHIFT 20 1318f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_3_MASK (0xf << 16) 1319f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20) 1320f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_4_SHIFT 24 1321f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_4_SHIFT 28 1322f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_WIDTH_4_MASK (0xf << 24) 1323f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28) 1324f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1325f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXOFFSET_0 0x1c5c 1326f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXOFFSET_1 0x1c74 1327f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXOFFSET_2 0x1c8c 1328f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0) 1329f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0) 1330f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0) 1331f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1332f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_MACRO_LINEAR (0 << 2) 1333f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_MACRO_TILE (1 << 2) 1334f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_MICRO_LINEAR (0 << 3) 1335f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_MICRO_TILE_X2 (1 << 3) 1336f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_MICRO_TILE_OPT (2 << 3) 1337f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_OFFSET_MASK 0xffffffe0 1338f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TXO_OFFSET_SHIFT 5 1339f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1340f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1341f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4 1342f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8 1343f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc 1344f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0 1345f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 1346f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04 1347f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08 1348f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c 1349f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10 1350f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 1351f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18 1352f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c 1353f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20 1354f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24 1355f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1356f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1357f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_SIZE_1 0x1d0c 1358f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_SIZE_2 0x1d14 1359f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_USIZE_MASK (0x7ff << 0) 1360f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_USIZE_SHIFT 0 1361f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_VSIZE_MASK (0x7ff << 16) 1362f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX_VSIZE_SHIFT 16 1363f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SIGNED_RGB_MASK (1 << 30) 1364f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SIGNED_RGB_SHIFT 30 1365f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SIGNED_ALPHA_MASK (1 << 31) 1366f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SIGNED_ALPHA_SHIFT 31 1367f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */ 1368f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */ 1369f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */ 1370f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org/* note: bits 13-5: 32 byte aligned stride of texture map */ 1371f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1372f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXCBLEND_0 0x1c60 1373f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXCBLEND_1 0x1c78 1374f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXCBLEND_2 0x1c90 1375f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_SHIFT 0 1376f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_MASK (0x1f << 0) 1377f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_ZERO (0 << 0) 1378f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0) 1379f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0) 1380f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) 1381f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) 1382f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0) 1383f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) 1384f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0) 1385f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) 1386f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0) 1387f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0) 1388f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0) 1389f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0) 1390f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0) 1391f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0) 1392f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0) 1393f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0) 1394f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_SHIFT 5 1395f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_MASK (0x1f << 5) 1396f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_ZERO (0 << 5) 1397f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5) 1398f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5) 1399f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) 1400f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) 1401f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5) 1402f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) 1403f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5) 1404f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) 1405f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5) 1406f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5) 1407f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5) 1408f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5) 1409f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5) 1410f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5) 1411f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5) 1412f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5) 1413f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_SHIFT 10 1414f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_MASK (0x1f << 10) 1415f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_ZERO (0 << 10) 1416f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10) 1417f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10) 1418f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) 1419f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) 1420f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10) 1421f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) 1422f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10) 1423f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) 1424f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10) 1425f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10) 1426f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10) 1427f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10) 1428f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10) 1429f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10) 1430f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10) 1431f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10) 1432f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_A (1 << 15) 1433f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_A_SHIFT 15 1434f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_B (1 << 16) 1435f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_B_SHIFT 16 1436f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_C (1 << 17) 1437f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_C_SHIFT 17 1438f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_MASK (7 << 18) 1439f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_ADD (0 << 18) 1440f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_SUBTRACT (1 << 18) 1441f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18) 1442f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_BLEND (3 << 18) 1443f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_CTL_DOT3 (4 << 18) 1444f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_SHIFT 21 1445f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_MASK (3 << 21) 1446f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_1X (0 << 21) 1447f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_2X (1 << 21) 1448f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_4X (2 << 21) 1449f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLAMP_TX (1 << 23) 1450f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_T0_EQ_TCUR (1 << 24) 1451f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_T1_EQ_TCUR (1 << 25) 1452f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_T2_EQ_TCUR (1 << 26) 1453f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_T3_EQ_TCUR (1 << 27) 1454f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ARG_MASK 0x1f 1455f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMP_ARG_SHIFT 15 1456f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXABLEND_0 0x1c64 1457f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXABLEND_1 0x1c7c 1458f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TXABLEND_2 0x1c94 1459f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_SHIFT 0 1460f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_MASK (0xf << 0) 1461f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_ZERO (0 << 0) 1462f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) 1463f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) 1464f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) 1465f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) 1466f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0) 1467f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0) 1468f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0) 1469f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0) 1470f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_SHIFT 4 1471f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_MASK (0xf << 4) 1472f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_ZERO (0 << 4) 1473f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) 1474f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) 1475f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) 1476f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) 1477f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4) 1478f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4) 1479f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4) 1480f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4) 1481f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_SHIFT 8 1482f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_MASK (0xf << 8) 1483f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_ZERO (0 << 8) 1484f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) 1485f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) 1486f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) 1487f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) 1488f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8) 1489f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8) 1490f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8) 1491f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8) 1492f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 12) 1493f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_ARG_MASK 0xf 1494f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1495f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TFACTOR_0 0x1c68 1496f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TFACTOR_1 0x1c80 1497f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_PP_TFACTOR_2 0x1c98 1498f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1499f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_BLENDCNTL 0x1c20 1500f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMB_FCN_MASK (3 << 12) 1501f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12) 1502f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12) 1503f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12) 1504f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12) 1505f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ZERO (32 << 16) 1506f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ONE (33 << 16) 1507f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16) 1508f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 1509f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16) 1510f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 1511f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16) 1512f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 1513f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16) 1514f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 1515f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 1516f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SRC_BLEND_MASK (63 << 16) 1517f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ZERO (32 << 24) 1518f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ONE (33 << 24) 1519f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24) 1520f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 1521f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24) 1522f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 1523f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24) 1524f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 1525f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24) 1526f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 1527f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DST_BLEND_MASK (63 << 24) 1528f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_CNTL 0x1c3c 1529f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_BLEND_ENABLE (1 << 0) 1530f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PLANE_MASK_ENABLE (1 << 1) 1531f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DITHER_ENABLE (1 << 2) 1532f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_ENABLE (1 << 3) 1533f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SCALE_DITHER_ENABLE (1 << 4) 1534f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DITHER_INIT (1 << 5) 1535f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_ENABLE (1 << 6) 1536f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ENABLE (1 << 7) 1537f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_ENABLE (1 << 8) 1538f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9) 1539f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10) 1540f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_RGB565 (4 << 10) 1541f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10) 1542f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_RGB332 (7 << 10) 1543f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_Y8 (8 << 10) 1544f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_RGB8 (9 << 10) 1545f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10) 1546f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10) 1547f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10) 1548f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10) 1549f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14) 1550f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ZBLOCK16 (1 << 15) 1551f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_COLOROFFSET 0x1c40 1552f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOROFFSET_MASK 0xfffffff0 1553f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_COLORPITCH 0x1c48 1554f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLORPITCH_MASK 0x000001ff8 1555f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_TILE_ENABLE (1 << 16) 1556f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17) 1557f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18) 1558f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18) 1559f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18) 1560f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_DEPTHOFFSET 0x1c24 1561f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_DEPTHPITCH 0x1c28 1562f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTHPITCH_MASK 0x00001ff8 1563f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_HYPERZ (3 << 16) 1564f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18) 1565f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18) 1566f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 1567f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_PLANEMASK 0x1d84 1568f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_ROPCNTL 0x1d80 1569f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_MASK (15 << 8) 1570f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_CLEAR (0 << 8) 1571f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_NOR (1 << 8) 1572f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_AND_INVERTED (2 << 8) 1573f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_COPY_INVERTED (3 << 8) 1574f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_AND_REVERSE (4 << 8) 1575f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_INVERT (5 << 8) 1576f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_XOR (6 << 8) 1577f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_NAND (7 << 8) 1578f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_AND (8 << 8) 1579f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_EQUIV (9 << 8) 1580f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_NOOP (10 << 8) 1581f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_OR_INVERTED (11 << 8) 1582f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_COPY (12 << 8) 1583f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_OR_REVERSE (13 << 8) 1584f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_OR (14 << 8) 1585f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROP_SET (15 << 8) 1586f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_STENCILREFMASK 0x1d7c 1587f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_REF_SHIFT 0 1588f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_REF_MASK (0xff << 0) 1589f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_MASK_SHIFT 16 1590f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_VALUE_MASK (0xff << 16) 1591f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_WRITEMASK_SHIFT 24 1592f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_WRITE_MASK (0xff << 24) 1593f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_ZPASS_DATA 0x3290 1594f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_ZPASS_ADDR 0x3294 1595f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c 1596f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_MASK (0xf << 0) 1597f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1598f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1599f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 1600f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 1601f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 1602f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) 1603f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 1604f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 1605f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_NEVER (0 << 4) 1606f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_LESS (1 << 4) 1607f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_LEQUAL (2 << 4) 1608f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_EQUAL (3 << 4) 1609f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_GEQUAL (4 << 4) 1610f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_GREATER (5 << 4) 1611f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_NEQUAL (6 << 4) 1612f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_ALWAYS (7 << 4) 1613f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_TEST_MASK (7 << 4) 1614f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_HIERARCHY_ENABLE (1 << 8) 1615f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_NEVER (0 << 12) 1616f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_LESS (1 << 12) 1617f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_LEQUAL (2 << 12) 1618f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_EQUAL (3 << 12) 1619f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_GEQUAL (4 << 12) 1620f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_GREATER (5 << 12) 1621f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_NEQUAL (6 << 12) 1622f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_ALWAYS (7 << 12) 1623f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_TEST_MASK (0x7 << 12) 1624f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_KEEP (0 << 16) 1625f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_ZERO (1 << 16) 1626f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_REPLACE (2 << 16) 1627f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_INC (3 << 16) 1628f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_DEC (4 << 16) 1629f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_INVERT (5 << 16) 1630f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_INC_WRAP (6 << 16) 1631f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_DEC_WRAP (7 << 16) 1632f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_FAIL_MASK (0x7 << 16) 1633f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_KEEP (0 << 20) 1634f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_ZERO (1 << 20) 1635f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20) 1636f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_INC (3 << 20) 1637f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_DEC (4 << 20) 1638f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_INVERT (5 << 20) 1639f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_INC_WRAP (6 << 20) 1640f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_DEC_WRAP (7 << 20) 1641f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20) 1642f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24) 1643f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24) 1644f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24) 1645f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_INC (3 << 24) 1646f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_DEC (4 << 24) 1647f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24) 1648f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_INC_WRAP (6 << 24) 1649f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_DEC_WRAP (7 << 24) 1650f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24) 1651f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_COMPRESSION_ENABLE (1 << 28) 1652f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCE_Z_DIRTY (1 << 29) 1653f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_WRITE_ENABLE (1 << 30) 1654f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31) 1655f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1656f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_STIPPLE_ADDR 0x1cc8 1657f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_STIPPLE_DATA 0x1ccc 1658f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_LINE_PATTERN 0x1cd0 1659f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_PATTERN_MASK 0x0000ffff 1660f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_REPEAT_COUNT_SHIFT 16 1661f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_PATTERN_START_SHIFT 24 1662f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 1663f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 1664f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29) 1665f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_LINE_STATE 0x1cd4 1666f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_CURRENT_PTR_SHIFT 0 1667f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LINE_CURRENT_COUNT_SHIFT 8 1668f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_MISC 0x26c4 1669f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_COORD_MASK 0x1f 1670f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_X_OFFSET_SHIFT 0 1671f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0) 1672f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8 1673f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8) 1674f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16) 1675f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16) 1676f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_SOLID_COLOR 0x1c1c 1677f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_TOP_LEFT 0x26c0 1678f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RE_LEFT_SHIFT 0 1679f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RE_TOP_SHIFT 16 1680f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_RE_WIDTH_HEIGHT 0x1c44 1681f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RE_WIDTH_SHIFT 0 1682f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RE_HEIGHT_SHIFT 16 1683f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1684f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_CNTL 0x1c4c 1685f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_CULL_CW (0 << 0) 1686f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_CULL_CCW (1 << 0) 1687f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_CULL_DIR_MASK (1 << 0) 1688f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BFACE_CULL (0 << 1) 1689f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BFACE_SOLID (3 << 1) 1690f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_CULL (0 << 3) 1691f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_SOLID (3 << 3) 1692f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FFACE_CULL_MASK (3 << 3) 1693f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BADVTX_CULL_DISABLE (1 << 5) 1694f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FLAT_SHADE_VTX_0 (0 << 6) 1695f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FLAT_SHADE_VTX_1 (1 << 6) 1696f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FLAT_SHADE_VTX_2 (2 << 6) 1697f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6) 1698f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8) 1699f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8) 1700f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8) 1701f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SHADE_MASK (3 << 8) 1702f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_SHADE_SOLID (0 << 10) 1703f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_SHADE_FLAT (1 << 10) 1704f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10) 1705f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ALPHA_SHADE_MASK (3 << 10) 1706f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_SHADE_SOLID (0 << 12) 1707f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_SHADE_FLAT (1 << 12) 1708f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12) 1709f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_SHADE_MASK (3 << 12) 1710f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_SHADE_SOLID (0 << 14) 1711f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_SHADE_FLAT (1 << 14) 1712f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_SHADE_GOURAUD (2 << 14) 1713f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FOG_SHADE_MASK (3 << 14) 1714f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ZBIAS_ENABLE_POINT (1 << 16) 1715f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ZBIAS_ENABLE_LINE (1 << 17) 1716f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ZBIAS_ENABLE_TRI (1 << 18) 1717f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_WIDELINE_ENABLE (1 << 20) 1718f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24) 1719f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25) 1720f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_PIX_CENTER_D3D (0 << 27) 1721f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_PIX_CENTER_OGL (1 << 27) 1722f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_MODE_TRUNC (0 << 28) 1723f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_MODE_ROUND (1 << 28) 1724f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28) 1725f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28) 1726f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_PREC_16TH_PIX (0 << 30) 1727f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_PREC_8TH_PIX (1 << 30) 1728f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_PREC_4TH_PIX (2 << 30) 1729f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_ROUND_PREC_HALF_PIX (3 << 30) 1730f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_CNTL_STATUS 0x2140 1731f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VC_NO_SWAP (0 << 0) 1732f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VC_16BIT_SWAP (1 << 0) 1733f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VC_32BIT_SWAP (2 << 0) 1734f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VC_HALF_DWORD_SWAP (3 << 0) 1735f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_BYPASS (1 << 8) 1736f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_COORD_FMT 0x1c50 1737f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) 1738f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) 1739f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8) 1740f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9) 1741f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10) 1742f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11) 1743f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_W0_NORMALIZE (1 << 12) 1744f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) 1745f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) 1746f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) 1747f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) 1748f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) 1749f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26) 1750f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26) 1751f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_LINE_WIDTH 0x1db8 1752f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c 1753f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHTING_ENABLE (1 << 0) 1754f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_IN_MODELSPACE (1 << 1) 1755f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LOCAL_VIEWER (1 << 2) 1756f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_NORMALIZE_NORMALS (1 << 3) 1757f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RESCALE_NORMALS (1 << 4) 1758f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_LIGHTS (1 << 5) 1759f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6) 1760f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_ALPHA (1 << 7) 1761f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8) 1762f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) 1763f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LM_SOURCE_STATE_PREMULT 0 1764f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LM_SOURCE_STATE_MULT 1 1765f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2 1766f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3 1767f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_EMISSIVE_SOURCE_SHIFT 16 1768f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_AMBIENT_SOURCE_SHIFT 18 1769f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_DIFFUSE_SOURCE_SHIFT 20 1770f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SPECULAR_SOURCE_SHIFT 22 1771f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220 1772f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 1773f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 1774f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c 1775f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 1776f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 1777f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 1778f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c 1779f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 1780f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 1781f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 1782f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c 1783f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240 1784f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 1785f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 1786f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c 1787f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c 1788f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELVIEW_0_SHIFT 0 1789f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELVIEW_1_SHIFT 4 1790f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELVIEW_2_SHIFT 8 1791f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELVIEW_3_SHIFT 12 1792f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_IT_MODELVIEW_0_SHIFT 16 1793f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_IT_MODELVIEW_1_SHIFT 20 1794f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_IT_MODELVIEW_2_SHIFT 24 1795f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_IT_MODELVIEW_3_SHIFT 28 1796f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260 1797f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELPROJECT_0_SHIFT 0 1798f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELPROJECT_1_SHIFT 4 1799f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELPROJECT_2_SHIFT 8 1800f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_MODELPROJECT_3_SHIFT 12 1801f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_0_SHIFT 16 1802f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_1_SHIFT 20 1803f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_2_SHIFT 24 1804f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_3_SHIFT 28 1805f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1806f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1807f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254 1808f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_W0 (1 << 0) 1809f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1) 1810f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_FP_ALPHA (1 << 2) 1811f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3) 1812f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_FP_SPEC (1 << 4) 1813f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_FP_FOG (1 << 5) 1814f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_PK_SPEC (1 << 6) 1815f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_ST0 (1 << 7) 1816f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_ST1 (1 << 8) 1817f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Q1 (1 << 9) 1818f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_ST2 (1 << 10) 1819f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Q2 (1 << 11) 1820f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_ST3 (1 << 12) 1821f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Q3 (1 << 13) 1822f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Q0 (1 << 14) 1823f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15 1824f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_NORM0 (1 << 18) 1825f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_XY1 (1 << 27) 1826f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Z1 (1 << 28) 1827f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_W1 (1 << 29) 1828f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_NORM1 (1 << 30) 1829f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_VTX_Z0 (1 << 31) 1830f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1831f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258 1832f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_COMPUTE_XYZW (1 << 0) 1833f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1) 1834f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2) 1835f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) 1836f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4) 1837f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_INPUT_TEX_0 0 1838f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_INPUT_TEX_1 1 1839f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_INPUT_TEX_2 2 1840f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_INPUT_TEX_3 3 1841f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_COMPUTED_TEX_0 8 1842f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_COMPUTED_TEX_1 9 1843f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_COMPUTED_TEX_2 10 1844f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_COMPUTED_TEX_3 11 1845f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16 1846f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20 1847f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24 1848f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28 1849f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1850f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270 1851f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_ENABLE (1 << 0) 1852f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1) 1853f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2) 1854f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_IS_LOCAL (1 << 3) 1855f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_IS_SPOT (1 << 4) 1856f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_DUAL_CONE (1 << 5) 1857f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) 1858f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) 1859f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_0_SHIFT 0 1860f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_ENABLE (1 << 16) 1861f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17) 1862f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18) 1863f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_IS_LOCAL (1 << 19) 1864f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_IS_SPOT (1 << 20) 1865f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_DUAL_CONE (1 << 21) 1866f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) 1867f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) 1868f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_1_SHIFT 16 1869f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274 1870f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_2_SHIFT 0 1871f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_3_SHIFT 16 1872f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278 1873f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_4_SHIFT 0 1874f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_5_SHIFT 16 1875f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c 1876f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_6_SHIFT 0 1877f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_7_SHIFT 16 1878f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1879f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_STATE_FLUSH 0x2284 1880f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1881f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_SHININESS 0x2250 1882f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1883f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268 1884f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0) 1885f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1) 1886f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2) 1887f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3) 1888f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_0_ENABLE (1 << 4) 1889f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_1_ENABLE (1 << 5) 1890f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_2_ENABLE (1 << 6) 1891f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXMAT_3_ENABLE (1 << 7) 1892f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_MASK 0xf 1893f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0 1894f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1 1895f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2 1896f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3 1897f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_OBJ 4 1898f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_EYE 5 1899f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6 1900f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7 1901f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8 1902f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_0_INPUT_SHIFT 16 1903f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_1_INPUT_SHIFT 20 1904f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_2_INPUT_SHIFT 24 1905f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TEXGEN_3_INPUT_SHIFT 28 1906f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1907f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264 1908f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_IN_CLIP_SPACE (1 << 0) 1909f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_IN_MODEL_SPACE (1 << 1) 1910f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_0 (1 << 2) 1911f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_1 (1 << 3) 1912f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_2 (1 << 4) 1913f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_3 (1 << 5) 1914f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_4 (1 << 6) 1915f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_UCP_ENABLE_5 (1 << 7) 1916f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FOG_MASK (3 << 8) 1917f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FOG_DISABLE (0 << 8) 1918f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FOG_EXP (1 << 8) 1919f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FOG_EXP2 (2 << 8) 1920f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TCL_FOG_LINEAR (3 << 8) 1921f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RNG_BASED_FOG (1 << 10) 1922f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_LIGHT_TWOSIDE (1 << 11) 1923f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_OP_COUNT_MASK (7 << 12) 1924f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLEND_OP_COUNT_SHIFT 12 1925f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16) 1926f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17) 1927f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (0 << 18) 1928f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) 1929f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (0 << 19) 1930f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) 1931f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (0 << 20) 1932f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) 1933f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (0 << 21) 1934f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) 1935f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) 1936f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CULL_FRONT_IS_CW (0 << 28) 1937f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CULL_FRONT_IS_CCW (1 << 28) 1938f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CULL_FRONT (1 << 29) 1939f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CULL_BACK (1 << 30) 1940f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_FORCE_W_TO_ONE (1 << 31) 1941f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1942f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_XSCALE 0x1d98 1943f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_XOFFSET 0x1d9c 1944f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_YSCALE 0x1da0 1945f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_YOFFSET 0x1da4 1946f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_ZSCALE 0x1da8 1947f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VPORT_ZOFFSET 0x1dac 1948f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_ZBIAS_FACTOR 0x1db0 1949f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_ZBIAS_CONSTANT 0x1db4 1950f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1951f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SE_VTX_FMT 0x2080 1952f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_XY 0x00000000 1953f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_W0 0x00000001 1954f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002 1955f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004 1956f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008 1957f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010 1958f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_FPFOG 0x00000020 1959f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040 1960f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_ST0 0x00000080 1961f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_ST1 0x00000100 1962f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Q1 0x00000200 1963f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_ST2 0x00000400 1964f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Q2 0x00000800 1965f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_ST3 0x00001000 1966f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Q3 0x00002000 1967f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Q0 0x00004000 1968f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 1969f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_N0 0x00040000 1970f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_XY1 0x08000000 1971f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Z1 0x10000000 1972f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_W1 0x20000000 1973f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_N1 0x40000000 1974f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_SE_VTX_FMT_Z 0x80000000 1975f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1976f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Registers for CP and Microcode Engine */ 1977f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_ME_RAM_ADDR 0x07d4 1978f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_ME_RAM_RADDR 0x07d8 1979f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_ME_RAM_DATAH 0x07dc 1980f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_ME_RAM_DATAL 0x07e0 1981f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1982f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_BASE 0x0700 1983f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_CNTL 0x0704 1984f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_RPTR_ADDR 0x070c 1985f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_RPTR 0x0710 1986f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_WPTR 0x0714 1987f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1988f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_IB_BASE 0x0738 1989f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_IB_BUFSZ 0x073c 1990f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 1991f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_CNTL 0x0740 1992f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0) 1993f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28) 1994f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28) 1995f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIBM_INDDIS (2 << 28) 1996f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIPIO_INDBM (3 << 28) 1997f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIBM_INDBM (4 << 28) 1998f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28) 1999f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_STAT 0x07f8 2000f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0) 2001f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8) 2002f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16) 2003f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24) 2004f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_ADDR 0x07f0 2005f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_DATA 0x07f4 2006f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_APER_PRIMARY 0x1000 2007f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_CSQ_APER_INDIRECT 0x1300 2008f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2009f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_RB_WPTR_DELAY 0x0718 2010f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PRE_WRITE_TIMER_SHIFT 0 2011f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PRE_WRITE_LIMIT_SHIFT 23 2012f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2013f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AIC_CNTL 0x01d0 2014f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 2015f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_AIC_LO_ADDR 0x01dc 2016f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2017f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2018f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2019f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* Constants */ 2020f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 2021f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 2022f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2023f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2024f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2025f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org /* CP packet types */ 2026f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET0 0x00000000 2027f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET1 0x40000000 2028f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET2 0x80000000 2029f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3 0xC0000000 2030f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET_MASK 0xC0000000 2031f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 2032f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12) 2033f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET0_REG_MASK 0x000007ff 2034f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff 2035f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800 2036f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2037f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000 2038f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2039f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_NOP 0xC0001000 2040f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900 2041f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 2042f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00 2043f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 2044f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400 2045f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 2046f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800 2047f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900 2048f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00 2049f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00 2050f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 2051f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_CP_CMD_3D_DRAW_VBUF_2 0xC0003400 2052f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_CP_CMD_3D_DRAW_IMMD_2 0xC0003500 2053f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define R200_CP_CMD_3D_DRAW_INDX_2 0xC0003600 2054f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100 2055f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200 2056f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 2057f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 2058f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500 2059f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 2060f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 2061f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 2062f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 2063f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2064f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2065f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_XY 0x00000000 2066f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_W0 0x00000001 2067f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002 2068f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004 2069f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008 2070f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010 2071f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_FPFOG 0x00000020 2072f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040 2073f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_ST0 0x00000080 2074f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_ST1 0x00000100 2075f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Q1 0x00000200 2076f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_ST2 0x00000400 2077f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Q2 0x00000800 2078f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_ST3 0x00001000 2079f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Q3 0x00002000 2080f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Q0 0x00004000 2081f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 2082f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_N0 0x00040000 2083f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_XY1 0x08000000 2084f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Z1 0x10000000 2085f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_W1 0x20000000 2086f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_N1 0x40000000 2087f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_FRMT_Z 0x80000000 2088f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2089f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 2090f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 2091f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 2092f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 2093f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 2094f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 2095f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 2096f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 2097f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 2098f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 2099f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a 2100f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010 2101f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 2102f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030 2103f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 2104f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 2105f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080 2106f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000 2107f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100 2108f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000 2109f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200 2110f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_CP_VC_CNTL_NUM_SHIFT 16 2111f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2112f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_0_ADDR 0 2113f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_1_ADDR 4 2114f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_2_ADDR 8 2115f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_3_ADDR 12 2116f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_4_ADDR 16 2117f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_5_ADDR 20 2118f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_6_ADDR 24 2119f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_7_ADDR 28 2120f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_8_ADDR 32 2121f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_9_ADDR 36 2122f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_10_ADDR 40 2123f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_11_ADDR 44 2124f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_12_ADDR 48 2125f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_13_ADDR 52 2126f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_14_ADDR 56 2127f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_15_ADDR 60 2128f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_AMBIENT_ADDR 64 2129f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72 2130f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_SPECULAR_ADDR 80 2131f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_DIRPOS_ADDR 88 2132f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96 2133f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104 2134f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112 2135f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_UCP_ADDR 116 2136f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122 2137f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_FOG_PARAM_ADDR 123 2138f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_VS_EYE_VECTOR_ADDR 124 2139f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2140f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_LIGHT_DCD_ADDR 0 2141f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8 2142f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16 2143f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24 2144f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32 2145f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48 2146f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 2147f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 2148f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 2149f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_SS_SHININESS 60 2150f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org 2151f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TV_MASTER_CNTL 0x0800 2152f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TVCLK_ALWAYS_ONb (1 << 30) 2153f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TV_DAC_CNTL 0x088c 2154f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_DAC_CMPOUT (1 << 5) 2155f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888 2156f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_Y_RED_EN (1 << 0) 2157f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_C_GRN_EN (1 << 1) 2158f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_CMP_BLU_EN (1 << 2) 2159f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4) 2160f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8) 2161f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12) 2162f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16 2163f2ba7591b1407a7ee9209f842c50696914dc2dedkbr@chromium.org#endif 2164