1// RUN: %clang_cc1 -O3 -triple arm64-apple-ios7 -target-feature +neon -S -ffreestanding %s -o - -target-cpu cyclone | FileCheck %s 2// REQUIRES: aarch64-registered-target 3// test code generation for <rdar://problem/11487757> 4#include <arm_neon.h> 5 6unsigned bar(); 7 8// Branch if any lane of V0 is zero; 64 bit => !min 9unsigned anyZero64(uint16x4_t a) { 10// CHECK: anyZero64: 11// CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 12// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 13// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 14// CHECK: [[LABEL]]: 15// CHECK-NEXT: b {{_bar|bar}} 16 if (!vminv_u8(a)) 17 return bar(); 18 return 0; 19} 20 21// Branch if any lane of V0 is zero; 128 bit => !min 22unsigned anyZero128(uint16x8_t a) { 23// CHECK: anyZero128: 24// CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 25// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 26// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 27// CHECK: [[LABEL]]: 28// CHECK-NEXT: b {{_bar|bar}} 29 if (!vminvq_u8(a)) 30 return bar(); 31 return 0; 32} 33 34// Branch if any lane of V0 is non-zero; 64 bit => max 35unsigned anyNonZero64(uint16x4_t a) { 36// CHECK: anyNonZero64: 37// CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0 38// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 39// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 40// CHECK: [[LABEL]]: 41// CHECK-NEXT: movz w0, #0 42 if (vmaxv_u8(a)) 43 return bar(); 44 return 0; 45} 46 47// Branch if any lane of V0 is non-zero; 128 bit => max 48unsigned anyNonZero128(uint16x8_t a) { 49// CHECK: anyNonZero128: 50// CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0 51// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 52// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 53// CHECK: [[LABEL]]: 54// CHECK-NEXT: movz w0, #0 55 if (vmaxvq_u8(a)) 56 return bar(); 57 return 0; 58} 59 60// Branch if all lanes of V0 are zero; 64 bit => !max 61unsigned allZero64(uint16x4_t a) { 62// CHECK: allZero64: 63// CHECK: umaxv.8b b[[REGNO1:[0-9]+]], v0 64// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 65// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 66// CHECK: [[LABEL]]: 67// CHECK-NEXT: b {{_bar|bar}} 68 if (!vmaxv_u8(a)) 69 return bar(); 70 return 0; 71} 72 73// Branch if all lanes of V0 are zero; 128 bit => !max 74unsigned allZero128(uint16x8_t a) { 75// CHECK: allZero128: 76// CHECK: umaxv.16b b[[REGNO1:[0-9]+]], v0 77// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 78// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 79// CHECK: [[LABEL]]: 80// CHECK-NEXT: b {{_bar|bar}} 81 if (!vmaxvq_u8(a)) 82 return bar(); 83 return 0; 84} 85 86// Branch if all lanes of V0 are non-zero; 64 bit => min 87unsigned allNonZero64(uint16x4_t a) { 88// CHECK: allNonZero64: 89// CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 90// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 91// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 92// CHECK: [[LABEL]]: 93// CHECK-NEXT: movz w0, #0 94 if (vminv_u8(a)) 95 return bar(); 96 return 0; 97} 98 99// Branch if all lanes of V0 are non-zero; 128 bit => min 100unsigned allNonZero128(uint16x8_t a) { 101// CHECK: allNonZero128: 102// CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 103// CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] 104// CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[.A-Z_0-9]+]] 105// CHECK: [[LABEL]]: 106// CHECK-NEXT: movz w0, #0 107 if (vminvq_u8(a)) 108 return bar(); 109 return 0; 110} 111 112