1@/*****************************************************************************
2@*
3@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
4@*
5@* Licensed under the Apache License, Version 2.0 (the "License");
6@* you may not use this file except in compliance with the License.
7@* You may obtain a copy of the License at:
8@*
9@* http://www.apache.org/licenses/LICENSE-2.0
10@*
11@* Unless required by applicable law or agreed to in writing, software
12@* distributed under the License is distributed on an "AS IS" BASIS,
13@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14@* See the License for the specific language governing permissions and
15@* limitations under the License.
16@*
17@*****************************************************************************/
18@/**
19@ *******************************************************************************
20@ * @file
21@ *  ihevc_itrans_recon_4x4_ttype1.s
22@ *
23@ * @brief
24@ *  contains function definitions for inverse transform  and reconstruction
25@ *
26@ *
27@ * @author
28@ *  naveen sr
29@ *
30@ * @par list of functions:
31@ *  - ihevc_itrans_recon_4x4_ttype1()
32@ *
33@ * @remarks
34@ *  none
35@ *
36@ *******************************************************************************
37@ */
38
39@/* all the functions here are replicated from ihevc_itrans.c and modified to */
40@/* include reconstruction */
41@
42@/**
43@ *******************************************************************************
44@ *
45@ * @brief
46@ *  this function performs inverse transform type 1 (dst)  and reconstruction
47@ * for 4x4 input block
48@ *
49@ * @par description:
50@ *  performs inverse transform and adds the prediction  data and clips output
51@ * to 8 bit
52@ *
53@ * @param[in] pi2_src
54@ *  input 4x4 coefficients
55@ *
56@ * @param[in] pi2_tmp
57@ *  temporary 4x4 buffer for storing inverse
58@ *
59@ *  transform
60@ *  1st stage output
61@ *
62@ * @param[in] pu1_pred
63@ *  prediction 4x4 block
64@ *
65@ * @param[out] pu1_dst
66@ *  output 4x4 block
67@ *
68@ * @param[in] src_strd
69@ *  input stride
70@ *
71@ * @param[in] pred_strd
72@ *  prediction stride
73@ *
74@ * @param[in] dst_strd
75@ *  output stride
76@ *
77@ * @param[in] zero_cols
78@ *  zero columns in pi2_src
79@ *
80@ * @returns  void
81@ *
82@ * @remarks
83@ *  none
84@ *
85@ *******************************************************************************
86@ */
87@void ihevc_itrans_recon_4x4_ttype1(word16 *pi2_src,
88@       word16 *pi2_tmp,
89@       uword8 *pu1_pred,
90@       uword8 *pu1_dst,
91@       word32 src_strd,
92@       word32 pred_strd,
93@       word32 dst_strd,
94@       word32 zero_cols)
95
96@**************variables vs registers*************************
97@   r0 => *pi2_src
98@   r1 => *pi2_tmp
99@   r2 => *pu1_pred
100@   r3 => *pu1_dst
101@   r4 => src_strd
102@   r5 => pred_strd
103@   r6 => dst_strd
104@   r7 => zero_cols
105
106.text
107.align 4
108
109
110
111
112.set shift_stage1_idct ,   7
113.set shift_stage2_idct ,   12
114
115.globl ihevc_itrans_recon_4x4_ttype1_a9q
116
117.type ihevc_itrans_recon_4x4_ttype1_a9q, %function
118
119ihevc_itrans_recon_4x4_ttype1_a9q:
120
121    stmfd       sp!, {r4-r12, r14}          @stack stores the values of the arguments
122    ldr         r4,[sp,#40]                 @loading src_strd
123    ldr         r5,[sp,#44]                 @loading pred_strd
124    ldr         r6,[sp,#48]                 @loading dst_strd
125    ldr         r7,[sp,#52]                 @loading zero_cols
126
127    add         r4,r4,r4                    @ src_strd in terms of word16
128
129    mov         r8,#29
130    mov         r9,#55
131    mov         r10,#74
132    mov         r11,#84
133    vmov.i16    d4[0],r8
134    vld1.16     d0,[r0],r4                  @loading pi2_src 1st row
135    vmov.i16    d4[1],r9
136    vld1.16     d1,[r0],r4                  @loading pi2_src 2nd row
137    vmov.i16    d4[2],r10
138    vld1.16     d2,[r0],r4                  @loading pi2_src 3rd row
139    vmov.i16    d4[3],r11
140    vld1.16     d3,[r0],r4                  @loading pi2_src 4th row
141
142    @ first stage computation starts
143    vmull.s16   q3,d1,d4[2]                 @74 * pi2_src[1]
144    vmlal.s16   q3,d0,d4[0]                 @74 * pi2_src[1] + 29 * pi2_src[0]
145    vmlal.s16   q3,d3,d4[1]                 @74 * pi2_src[1] + 29 * pi2_src[0] + 55 * pi2_src[3]
146    vmlal.s16   q3,d2,d4[3]                 @pi2_out[0] = 29* pi2_src[0] + 74 * pi2_src[1] + 84* pi2_src[2] + 55 * pi2_src[3]
147
148    vmull.s16   q4,d1,d4[2]                 @74 * pi2_src[1]
149    vmlal.s16   q4,d0,d4[1]                 @74 * pi2_src[1] + 55 * pi2_src[0]
150    vmlsl.s16   q4,d2,d4[0]                 @74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2]
151    vmlsl.s16   q4,d3,d4[3]                 @pi2_out[1] = 74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2] - 84 * pi2_src[3])
152
153    vmull.s16   q5,d0,d4[2]                 @ 74 * pi2_src[0]
154    vmlsl.s16   q5,d2,d4[2]                 @ 74 * pi2_src[0] - 74 * pi2_src[2]
155    vmlal.s16   q5,d3,d4[2]                 @pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
156
157    vmull.s16   q6,d2,d4[1]                 @ 55 * pi2_src[2]
158    vmlsl.s16   q6,d1,d4[2]                 @ 55 * pi2_src[2] - 74 * pi2_src[1]
159    vmlsl.s16   q6,d3,d4[0]                 @ - 74 * pi2_src[1] +   55 * pi2_src[2] - 29 * pi2_src[3]
160    vmlal.s16   q6,d0,d4[3]                 @pi2_out[3] = 84 * pi2_src[0] - 74 * pi2_src[1] + 55 * pi2_src[2] - 29 * pi2_src[3]
161
162    vqrshrn.s32 d14,q3,#shift_stage1_idct   @ (pi2_out[0] + rounding ) >> shift_stage1_idct
163    vqrshrn.s32 d15,q4,#shift_stage1_idct   @ (pi2_out[1] + rounding ) >> shift_stage1_idct
164    vqrshrn.s32 d16,q5,#shift_stage1_idct   @ (pi2_out[2] + rounding ) >> shift_stage1_idct
165    vqrshrn.s32 d17,q6,#shift_stage1_idct   @ (pi2_out[3] + rounding ) >> shift_stage1_idct
166    vld1.32     d18[0], [r2],r5
167
168    vtrn.16     d14,d15
169    vtrn.16     d16,d17
170    vtrn.32     d14,d16
171    vtrn.32     d15,d17
172    @ output in d14,d15,d16,d17
173    @ first stage computation ends
174
175    @ second stage computation starts  :  copy pasting 1st stage
176    @ register changes
177    @ d14 - d0
178    @ d15 - d1
179    @ d16 - d2
180    @ d17 - d3
181    vld1.32     d18[1], [r2],r5
182    vmull.s16   q3,d15,d4[2]                @74 * pi2_src[1]
183    vmlal.s16   q3,d14,d4[0]                @74 * pi2_src[1] + 29 * pi2_src[0]
184    vmlal.s16   q3,d17,d4[1]                @74 * pi2_src[1] + 29 * pi2_src[0] + 55 * pi2_src[3]
185    vmlal.s16   q3,d16,d4[3]                @pi2_out[0] = 29* pi2_src[0] + 74 * pi2_src[1] + 84* pi2_src[2] + 55 * pi2_src[3]
186
187    vmull.s16   q4,d15,d4[2]                @74 * pi2_src[1]
188    vmlal.s16   q4,d14,d4[1]                @74 * pi2_src[1] + 55 * pi2_src[0]
189    vmlsl.s16   q4,d16,d4[0]                @74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2]
190    vmlsl.s16   q4,d17,d4[3]                @pi2_out[1] = 74 * pi2_src[1] + 55 * pi2_src[0] -  29 * pi2_src[2] - 84 * pi2_src[3])
191
192    vmull.s16   q5,d14,d4[2]                @ 74 * pi2_src[0]
193    vmlsl.s16   q5,d16,d4[2]                @ 74 * pi2_src[0] - 74 * pi2_src[2]
194    vmlal.s16   q5,d17,d4[2]                @pi2_out[2] = 74 * pi2_src[0] - 74 * pi2_src[2] + 74 * pi2_src[3]
195    vld1.32     d19[0], [r2],r5
196
197    vmull.s16   q6,d16,d4[1]                @ 55 * pi2_src[2]
198    vmlsl.s16   q6,d15,d4[2]                @  - 74 * pi2_src[1] +   55 * pi2_src[2]
199    vmlsl.s16   q6,d17,d4[0]                @ - 74 * pi2_src[1] +   55 * pi2_src[2] - 29 * pi2_src[3]
200    vmlal.s16   q6,d14,d4[3]                @pi2_out[3] = 84 * pi2_src[0] - 74 * pi2_src[1] + 55 * pi2_src[2] - 29 * pi2_src[3]
201
202    vqrshrn.s32 d0,q3,#shift_stage2_idct    @ (pi2_out[0] + rounding ) >> shift_stage1_idct
203    vqrshrn.s32 d1,q4,#shift_stage2_idct    @ (pi2_out[1] + rounding ) >> shift_stage1_idct
204    vqrshrn.s32 d2,q5,#shift_stage2_idct    @ (pi2_out[2] + rounding ) >> shift_stage1_idct
205    vqrshrn.s32 d3,q6,#shift_stage2_idct    @ (pi2_out[3] + rounding ) >> shift_stage1_idct
206    vld1.32     d19[1], [r2],r5
207    vtrn.16     d0,d1
208    vtrn.16     d2,d3
209    vtrn.32     d0,d2
210    vtrn.32     d1,d3
211    @ output in d0,d1,d2,d3
212    @ second stage computation ends
213
214    @ loading pred
215
216    vaddw.u8    q0,q0,d18                   @ pi2_out(16bit) + pu1_pred(8bit)
217    vqmovun.s16 d0,q0                       @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
218    vaddw.u8    q1,q1,d19                   @ pi2_out(16bit) + pu1_pred(8bit)
219    vqmovun.s16 d1,q1                       @ clip_u8(pi2_out(16bit) + pu1_pred(8bit))
220
221    @ storing destination
222    vst1.32     {d0[0]},[r3],r6
223    vst1.32     {d0[1]},[r3],r6
224    vst1.32     {d1[0]},[r3],r6
225    vst1.32     {d1[1]},[r3],r6
226
227    ldmfd       sp!,{r4-r12,r15}            @reload the registers from sp
228
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