MachineRegisterInfo.h revision 51458ed09e6db0e424cd528e10b879f59915abe4
184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// The LLVM Compiler Infrastructure 484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file is distributed under the University of Illinois Open Source 684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// License. See LICENSE.TXT for details. 784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// This file defines the MachineRegisterInfo class. 1184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner// 1284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner//===----------------------------------------------------------------------===// 1384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 1584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 1684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 176f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman#include "llvm/Target/TargetRegisterInfo.h" 1884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include "llvm/ADT/BitVector.h" 19994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen#include "llvm/ADT/IndexedMap.h" 2084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#include <vector> 2184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 2284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnernamespace llvm { 2384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 241213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// MachineRegisterInfo - Keep track of information for virtual and physical 251213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// registers, including vreg register classes, use/def chains for registers, 261213d672653d7fee471d91d05b559e137d70ba56Chris Lattner/// etc. 2784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerclass MachineRegisterInfo { 28994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen /// VRegInfo - Information we keep for each virtual register. 2962ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// 3062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// Each element in this list contains the register class of the vreg and the 3162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// start of the use/def list for the register. 32994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 33994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen VirtReg2IndexFunctor> VRegInfo; 3411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 3590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// RegAllocHints - This vector records register allocation hints for virtual 36358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// registers. For each virtual register, it keeps a register and hint type 37358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// pair making up the allocation hint. Hint type is target specific except 38358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// for the value 0 which means the second value of the pair is the preferred 39358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// register for allocation. For example, if the hint is <0, 1024>, it means 40358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng /// the allocator should prefer the physical register allocated to the virtual 4190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// register of the hint. 42994c727b5790e5c976e32c75364d78eb9b22a568Jakob Stoklund Olesen IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 4362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 4462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// PhysRegUseDefLists - This is an array of the head of the use/def list for 4562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// physical registers. 4662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand **PhysRegUseDefLists; 4784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 4884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// UsedPhysRegs - This is a bit vector that is computed and set by the 4984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocator, and must be kept up to date by passes that run after 5084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// register allocation (though most don't modify this). This is used 5184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// so that the code generator knows which callee save registers to save and 5284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// for other target specific uses. 5384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner BitVector UsedPhysRegs; 5484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 5584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIns/LiveOuts - Keep track of the physical registers that are 5684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// livein/liveout of the function. Live in values are typically arguments in 5784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// registers, live out values are typically return values in registers. 5884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// LiveIn values are allowed to have virtual registers associated with them, 5984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// stored in the second element. 6084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<std::pair<unsigned, unsigned> > LiveIns; 6184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner std::vector<unsigned> LiveOuts; 6268e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 6362ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 6584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattnerpublic: 666f0d024a534af18d9e60b3ea757376cd8a3a980eDan Gohman explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 6762ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner ~MachineRegisterInfo(); 6862ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner 696c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 706c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Register Info 716c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner //===--------------------------------------------------------------------===// 726c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// reg_begin/reg_end - Provide iteration support to walk over all definitions 746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// and uses of a register within the MachineFunction that corresponds to this 756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// MachineRegisterInfo object. 76a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool Uses, bool Defs, bool SkipDebug> 77c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator; 78c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 79c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 80c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// register. 81a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,true,false> reg_iterator; 826c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner reg_iterator reg_begin(unsigned RegNo) const { 836c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return reg_iterator(getRegUseDefListHead(RegNo)); 846c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 856c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner static reg_iterator reg_end() { return reg_iterator(0); } 86c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 8700ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// reg_empty - Return true if there are no instructions using or defining the 8800ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 8900ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 9000ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 91c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 92c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// of the specified register, skipping those marked as Debug. 93c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 94c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 95c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 96c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 97c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 98c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 99c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// reg_nodbg_empty - Return true if the only instructions using or defining 100c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen /// Reg are Debug instructions. 101c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen bool reg_nodbg_empty(unsigned RegNo) const { 102c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 103c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen } 104c66c78c6846631a9f6a44fee69d218f900e63140Jakob Stoklund Olesen 105c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 106a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<false,true,false> def_iterator; 107c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner def_iterator def_begin(unsigned RegNo) const { 108c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return def_iterator(getRegUseDefListHead(RegNo)); 109c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 110c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static def_iterator def_end() { return def_iterator(0); } 111c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 11200ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// def_empty - Return true if there are no instructions defining the 11300ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman /// specified register (it may be live-in). 11400ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 11500ffd505d327782eb51fa55e47967fd8e62ba40aDan Gohman 116c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 117a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,false> use_iterator; 118c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner use_iterator use_begin(unsigned RegNo) const { 119c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner return use_iterator(getRegUseDefListHead(RegNo)); 120c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 121c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner static use_iterator use_end() { return use_iterator(0); } 122c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 123ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// use_empty - Return true if there are no instructions using the specified 124ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng /// register. 125ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 126ce049437d6986cfb4c0dba6bf99cadd8c301351aEvan Cheng 1271423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneUse - Return true if there is exactly one instruction using the 1281423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// specified register. 1291423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneUse(unsigned RegNo) const; 1301423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 131a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 132a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// specified register, skipping those marked as Debug. 133a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 134a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 135a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 136a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 137a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1386c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 139a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// use_nodbg_empty - Return true if there are no non-Debug instructions 140a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// using the specified register. 141a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen bool use_nodbg_empty(unsigned RegNo) const { 142a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen return use_nodbg_begin(RegNo) == use_nodbg_end(); 143a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen } 144a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen 1451423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1461423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng /// instruction using the specified register. 1471423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng bool hasOneNonDBGUse(unsigned RegNo) const; 1481423c70b8f1b1a757c640fac9a17cb015012e8e9Evan Cheng 149e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// replaceRegWith - Replace all instances of FromReg with ToReg in the 150e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 151e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// except that it also changes any definitions of the register as well. 152e138b3dd1ff02d826233482831318708a166ed93Chris Lattner void replaceRegWith(unsigned FromReg, unsigned ToReg); 153e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 15462ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// getRegUseDefListHead - Return the head pointer for the register use/def 15562ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner /// list for the specified virtual or physical register. 15662ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 157c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 158c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 159c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 16062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner } 16184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 1626c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 163c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen if (TargetRegisterInfo::isVirtualRegister(RegNo)) 164c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return VRegInfo[RegNo].second; 165c9df025e33ac435adb3b3318d237c36ca7cec659Jakob Stoklund Olesen return PhysRegUseDefLists[RegNo]; 1666c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 1671eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1681eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// getVRegDef - Return the machine instr that defines the specified virtual 1691eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// register or null if none is found. This assumes that the code is in SSA 1701eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng /// form, so there should only be one definition. 1711eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng MachineInstr *getVRegDef(unsigned Reg) const; 17249b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman 17349b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clearKillFlags - Iterate over all the uses of the given register and 17449b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// clear the kill flag from the MachineOperand. This function is used by 17549b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// optimization passes which extend register lifetimes and need only 17649b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman /// preserve conservative kill flag information. 17749b4589978ca181537c8ae694ac4c8d58d27a09aDan Gohman void clearKillFlags(unsigned Reg) const; 1781eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng 1791eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#ifndef NDEBUG 1801eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng void dumpUses(unsigned RegNo) const; 1811eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng#endif 18284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 18384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 18484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Virtual Register Info 18584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 18684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 18784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// getRegClass - Return the register class of the specified virtual register. 18811a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 1891eb5cf9c7d0b0b04402eddc007b0de414488baf4Evan Cheng const TargetRegisterClass *getRegClass(unsigned Reg) const { 19062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner return VRegInfo[Reg].first; 19184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 192bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng 193bdf34bc12bfc39de02c19fa250e83edb5924a6cfEvan Cheng /// setRegClass - Set the register class of the specified virtual register. 19411a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng /// 19533f1c68cba4e905fdd2bf7d2848c52052d46fbffDan Gohman void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 19611a26f3697ea6520022ea6d3fa6a07b3c1b988cdEvan Cheng 197bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// constrainRegClass - Constrain the register class of the specified virtual 198bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// register to be a common subclass of RC and the current register class. 199bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// Return the new register class, or NULL if no such class exists. 200bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// This should only be used when the constraint is known to be trivial, like 201bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 202bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *constrainRegClass(unsigned Reg, 203bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen const TargetRegisterClass *RC); 204bf4699c56100a0184bbe4fb53937c7204ca1ceb0Jakob Stoklund Olesen 20584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// createVirtualRegister - Create and return a new virtual register in the 20684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function with the specified register class. 20784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// 2082e3e5bf42742a7421b513829101501f2de6d2b02Dan Gohman unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 20984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 210b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// getNumVirtRegs - Return the number of virtual registers created. 211b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen /// 212b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen unsigned getNumVirtRegs() const { return VRegInfo.size(); } 213b421c566f512ed0ec87851866d335e9086c3f8beJakob Stoklund Olesen 21490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// setRegAllocationHint - Specify a register allocation hint for the 21590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 216358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 21790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].first = Type; 21890f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng RegAllocHints[Reg].second = PrefReg; 21990f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 22090f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 22190f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// getRegAllocationHint - Return the register allocation hint for the 22290f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng /// specified virtual register. 223358dec51804ee52e47ea3a47c9248086e458ad7cEvan Cheng std::pair<unsigned, unsigned> 22490f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng getRegAllocationHint(unsigned Reg) const { 22590f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng return RegAllocHints[Reg]; 22690f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng } 22790f95f88c6ce09c6744777dc9d140c3c77203b92Evan Cheng 22851458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 22951458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen /// standard simple hint (Type == 0) is not set. 23051458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen unsigned getSimpleHint(unsigned Reg) const { 23151458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 23251458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen return Hint.first ? 0 : Hint.second; 23351458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen } 23451458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 23551458ed09e6db0e424cd528e10b879f59915abe4Jakob Stoklund Olesen 23684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 23784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Physical Register Use Info 23884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 23984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 24084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// isPhysRegUsed - Return true if the specified register is used in this 24184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// function. This only works after register allocation. 24284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 24384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 24484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUsed - Mark the specified register used in this function. 24584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 24684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 24782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 24882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// addPhysRegsUsed - Mark the specified registers used in this function. 24982b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// This should only be called during and after register allocation. 25082b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 25182b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 25284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// setPhysRegUnused - Mark the specified register unused in this function. 25384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// This should only be called during and after register allocation. 25484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 25582b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen 25682b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 25782b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen /// subregisters. That means that if R is used, so are all subregisters. 25882b07dc4995d48065bd95affff4d8513a5cad4f2Jakob Stoklund Olesen void closePhysRegsUsed(const TargetRegisterInfo&); 25984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 26084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 26184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // LiveIn/LiveOut Management 26284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner //===--------------------------------------------------------------------===// 26384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 26484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 26584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner /// is an error to add the same register to the same set more than once. 26684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveIn(unsigned Reg, unsigned vreg = 0) { 26784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner LiveIns.push_back(std::make_pair(Reg, vreg)); 26884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner } 26984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 27068e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1Devang Patel 27184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // Iteration support for live in/out sets. These sets are kept in sorted 27284bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner // order by their register number. 27384bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 27484bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator; 27584bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner typedef std::vector<unsigned>::const_iterator liveout_iterator; 27684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_begin() const { return LiveIns.begin(); } 27784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner livein_iterator livein_end() const { return LiveIns.end(); } 27884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool livein_empty() const { return LiveIns.empty(); } 27984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 28084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner liveout_iterator liveout_end() const { return LiveOuts.end(); } 28184bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner bool liveout_empty() const { return LiveOuts.empty(); } 2826d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 28313e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveIn(unsigned Reg) const; 28413e73f483ef2ba630962dad3125393292533b756Dan Gohman bool isLiveOut(unsigned Reg) const; 2856d69ba8a6901c69d78488cbc41f8dbf080618fdeDan Gohman 2862ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2872ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng /// corresponding live-in physical register. 2882ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng unsigned getLiveInPhysReg(unsigned VReg) const; 2892ad0fcf794924f618a7240741cc14a39be99d0f2Evan Cheng 2903946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// getLiveInVirtReg - If PReg is a live-in physical register, return the 2913946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng /// corresponding live-in physical register. 2923946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng unsigned getLiveInVirtReg(unsigned PReg) const; 2933946043a80a043b3cf43b34bf068feaadc46485bEvan Cheng 29498708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 29598708260f55cab997a5db77e930a2bd35f4172aaDan Gohman /// into the given entry block. 29698708260f55cab997a5db77e930a2bd35f4172aaDan Gohman void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 29798708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetRegisterInfo &TRI, 29898708260f55cab997a5db77e930a2bd35f4172aaDan Gohman const TargetInstrInfo &TII); 29998708260f55cab997a5db77e930a2bd35f4172aaDan Gohman 30062ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattnerprivate: 30162ed6b9ade63bf01717ce5274fa11e93e873d245Chris Lattner void HandleVRegListReallocation(); 3026c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3036c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattnerpublic: 304c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// defusechain_iterator - This class provides iterator support for machine 305c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// operands in the function that use or define a specific register. If 306c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 307c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner /// returns defs. If neither are true then you are silly and it always 308a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// returns end(). If SkipDebug is true it skips uses marked Debug 309a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen /// when incrementing. 310a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 311c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner class defusechain_iterator 312f0891be8bdbeeadb39da5575273b6645755fa383Gabor Greif : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 3136c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner MachineOperand *Op; 3141327f69d98a2cb527b275ffc93080cf31ddf6dc5Dan Gohman explicit defusechain_iterator(MachineOperand *op) : Op(op) { 315c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If the first node isn't one we're interested in, advance to one that 316c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // we are interested in. 317c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner if (op) { 318ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov if ((!ReturnUses && op->isUse()) || 319a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && op->isDef()) || 320a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && op->isDebug())) 321c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner ++*this; 322c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 323c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner } 3246c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner friend class MachineRegisterInfo; 3256c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner public: 3267362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3277362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::reference reference; 3287362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif typedef std::iterator<std::forward_iterator_tag, 3297362ce08cb2c1f0b544b18dbc21630fb4baebcfcGabor Greif MachineInstr, ptrdiff_t>::pointer pointer; 3306c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 331c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 332c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator() : Op(0) {} 3336c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 334c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator==(const defusechain_iterator &x) const { 3356c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return Op == x.Op; 3366c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 337c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner bool operator!=(const defusechain_iterator &x) const { 3386c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return !operator==(x); 3396c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3406c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3416c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner /// atEnd - return true if this iterator is equal to reg_end() on the value. 3426c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner bool atEnd() const { return Op == 0; } 3436c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 3446c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner // Iterator traversal: forward iteration only 345c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator &operator++() { // Preincrement 3466c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot increment end iterator!"); 3476c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner Op = Op->getNextOperandForReg(); 348c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 349c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner // If this is an operand we don't care about, skip it. 350ae9f3a3b7c915f725aef5a7250e88eaeddda03c6Anton Korobeynikov while (Op && ((!ReturnUses && Op->isUse()) || 351a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (!ReturnDefs && Op->isDef()) || 352a65aa0f0bba1ef2322d63d05c074a92168684c63Dale Johannesen (SkipDebug && Op->isDebug()))) 353c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner Op = Op->getNextOperandForReg(); 354c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner 3556c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *this; 3566c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 357c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator operator++(int) { // Postincrement 358c637d6f4525e417260cf2ce08643dc62283e523fChris Lattner defusechain_iterator tmp = *this; ++*this; return tmp; 3596c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 360914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 361914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// skipInstruction - move forward until reaching a different instruction. 362914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// Return the skipped instruction that is no longer pointed to, or NULL if 363914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen /// already pointing to end(). 364914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *skipInstruction() { 365914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen if (!Op) return 0; 366914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen MachineInstr *MI = Op->getParent(); 367914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen do ++*this; 368914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen while (Op && Op->getParent() == MI); 369914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen return MI; 370914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen } 371914f2ff9e6969214d84a75745ec2851f045000f7Jakob Stoklund Olesen 372e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineOperand &getOperand() const { 3736c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner assert(Op && "Cannot dereference end iterator!"); 3746c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner return *Op; 3756c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner } 3766c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 377e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// getOperandNo - Return the operand # of this MachineOperand in its 378e138b3dd1ff02d826233482831318708a166ed93Chris Lattner /// MachineInstr. 379e138b3dd1ff02d826233482831318708a166ed93Chris Lattner unsigned getOperandNo() const { 380e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 381e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op - &Op->getParent()->getOperand(0); 382e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 383e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 384e138b3dd1ff02d826233482831318708a166ed93Chris Lattner // Retrieve a reference to the current operand. 385e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr &operator*() const { 386e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 387e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return *Op->getParent(); 388e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 389e138b3dd1ff02d826233482831318708a166ed93Chris Lattner 390e138b3dd1ff02d826233482831318708a166ed93Chris Lattner MachineInstr *operator->() const { 391e138b3dd1ff02d826233482831318708a166ed93Chris Lattner assert(Op && "Cannot dereference end iterator!"); 392e138b3dd1ff02d826233482831318708a166ed93Chris Lattner return Op->getParent(); 393e138b3dd1ff02d826233482831318708a166ed93Chris Lattner } 3946c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner }; 3956c5757e4e85bb190097be13c1630bb107a1fbcfeChris Lattner 39684bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner}; 39784bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 39884bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner} // End llvm namespace 39984bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner 40084bc5427d6883f73cfeae3da640acd011d35c006Chris Lattner#endif 401