MachineRegisterInfo.h revision 54d69668b22b8c37aa6e45f14445f3988cc430d4
10e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 20e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// 30e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// The LLVM Compiler Infrastructure 40e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// 50e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// This file is distributed under the University of Illinois Open Source 60e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// License. See LICENSE.TXT for details. 70e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// 80e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org//===----------------------------------------------------------------------===// 90e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// 100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// This file defines the MachineRegisterInfo class. 110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org// 120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org//===----------------------------------------------------------------------===// 130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#include "llvm/Target/TargetRegisterInfo.h" 180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#include "llvm/CodeGen/MachineInstrBundle.h" 190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#include "llvm/ADT/BitVector.h" 200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#include "llvm/ADT/IndexedMap.h" 210e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#include <vector> 220e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 230e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.orgnamespace llvm { 240e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 250e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org/// MachineRegisterInfo - Keep track of information for virtual and physical 260e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org/// registers, including vreg register classes, use/def chains for registers, 270e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org/// etc. 280e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.orgclass MachineRegisterInfo { 290e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetRegisterInfo *const TRI; 300e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 310e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// IsSSA - True when the machine function is in SSA form and virtual 320e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// registers have a single def. 330e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool IsSSA; 340e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 350e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// TracksLiveness - True while register liveness is being tracked accurately. 362a86ce22ccc387dfa6f8a98ce3eba5c1e6f9e538buildbot@webrtc.org /// Basic block live-in lists, kill flags, and implicit defs may not be 372a86ce22ccc387dfa6f8a98ce3eba5c1e6f9e538buildbot@webrtc.org /// accurate when after this flag is cleared. 382a86ce22ccc387dfa6f8a98ce3eba5c1e6f9e538buildbot@webrtc.org bool TracksLiveness; 390e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 402a86ce22ccc387dfa6f8a98ce3eba5c1e6f9e538buildbot@webrtc.org /// VRegInfo - Information we keep for each virtual register. 410e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 420e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// Each element in this list contains the register class of the vreg and the 430e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// start of the use/def list for the register. 440e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 450e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org VirtReg2IndexFunctor> VRegInfo; 460e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 470e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// RegAllocHints - This vector records register allocation hints for virtual 480e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// registers. For each virtual register, it keeps a register and hint type 490e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// pair making up the allocation hint. Hint type is target specific except 500e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// for the value 0 which means the second value of the pair is the preferred 510e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register for allocation. For example, if the hint is <0, 1024>, it means 520e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// the allocator should prefer the physical register allocated to the virtual 530e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register of the hint. 540e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 550e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 560e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// PhysRegUseDefLists - This is an array of the head of the use/def list for 570e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// physical registers. 580e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineOperand **PhysRegUseDefLists; 590e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 600e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// UsedPhysRegs - This is a bit vector that is computed and set by the 610e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register allocator, and must be kept up to date by passes that run after 620e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register allocation (though most don't modify this). This is used 630e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// so that the code generator knows which callee save registers to save and 640e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// for other target specific uses. 650e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This vector only has bits set for registers explicitly used, not their 660e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// aliases. 670e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org BitVector UsedPhysRegs; 680e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 690e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// UsedPhysRegMask - Additional used physregs, but including aliases. 700e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org BitVector UsedPhysRegMask; 710e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 720e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// ReservedRegs - This is a bit vector of reserved registers. The target 730e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// may change its mind about which registers should be reserved. This 740e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// vector is the frozen set of reserved registers when register allocation 750e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// started. 760e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org BitVector ReservedRegs; 770e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 780e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// AllocatableRegs - From TRI->getAllocatableSet. 790e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org mutable BitVector AllocatableRegs; 800e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 810e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// LiveIns/LiveOuts - Keep track of the physical registers that are 820e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// livein/liveout of the function. Live in values are typically arguments in 830e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// registers, live out values are typically return values in registers. 840e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// LiveIn values are allowed to have virtual registers associated with them, 850e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// stored in the second element. 860e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org std::vector<std::pair<unsigned, unsigned> > LiveIns; 870e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org std::vector<unsigned> LiveOuts; 880e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 890e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 900e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 910e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.orgpublic: 920e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 930e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org ~MachineRegisterInfo(); 940e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 950e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 960e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Function State 970e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 980e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 990e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // isSSA - Returns true when the machine function is in SSA form. Early 1000e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // passes require the machine function to be in SSA form where every virtual 1010e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // register has a single defining instruction. 1020e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // 1030e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // The TwoAddressInstructionPass and PHIElimination passes take the machine 1040e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // function out of SSA form when they introduce multiple defs per virtual 1050e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // register. 1060e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isSSA() const { return IsSSA; } 1070e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1080e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // leaveSSA - Indicates that the machine function is no longer in SSA form. 1090e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void leaveSSA() { IsSSA = false; } 1100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// tracksLiveness - Returns true when tracking register liveness accurately. 1120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 1130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// While this flag is true, register liveness information in basic block 1140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// live-in lists and machine instruction operands is accurate. This means it 1150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// can be used to change the code in ways that affect the values in 1160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// registers, for example by the register scavenger. 1170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 1180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// When this flag is false, liveness is no longer reliable. 1190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool tracksLiveness() const { return TracksLiveness; } 1200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1210e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// invalidateLiveness - Indicates that register liveness is no longer being 1220e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// tracked accurately. 1230e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 1240e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This should be called by late passes that invalidate the liveness 1250e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// information. 1260e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void invalidateLiveness() { TracksLiveness = false; } 1270e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1280e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 1290e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Register Info 1300e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 1310e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1320e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reg_begin/reg_end - Provide iteration support to walk over all definitions 1330e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// and uses of a register within the MachineFunction that corresponds to this 1340e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// MachineRegisterInfo object. 1350e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org template<bool Uses, bool Defs, bool SkipDebug> 1360e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org class defusechain_iterator; 1370e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1380e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 1390e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register. 1400e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef defusechain_iterator<true,true,false> reg_iterator; 1410e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org reg_iterator reg_begin(unsigned RegNo) const { 1420e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return reg_iterator(getRegUseDefListHead(RegNo)); 1430e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1440e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org static reg_iterator reg_end() { return reg_iterator(0); } 1450e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1460e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reg_empty - Return true if there are no instructions using or defining the 1470e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified register (it may be live-in). 1480e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 1490e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1500e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 1510e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// of the specified register, skipping those marked as Debug. 1520e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 1530e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 1540e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 1550e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1560e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 1570e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1580e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reg_nodbg_empty - Return true if the only instructions using or defining 1590e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// Reg are Debug instructions. 1600e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool reg_nodbg_empty(unsigned RegNo) const { 1610e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 1620e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1630e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1640e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 1650e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef defusechain_iterator<false,true,false> def_iterator; 1660e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org def_iterator def_begin(unsigned RegNo) const { 1670e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return def_iterator(getRegUseDefListHead(RegNo)); 1680e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1690e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org static def_iterator def_end() { return def_iterator(0); } 1700e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1710e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// def_empty - Return true if there are no instructions defining the 1720e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified register (it may be live-in). 1730e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 1740e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1750e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 1760e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef defusechain_iterator<true,false,false> use_iterator; 1770e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org use_iterator use_begin(unsigned RegNo) const { 1780e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return use_iterator(getRegUseDefListHead(RegNo)); 1790e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1800e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org static use_iterator use_end() { return use_iterator(0); } 1810e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1820e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// use_empty - Return true if there are no instructions using the specified 1830e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register. 1840e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 1850e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1860e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// hasOneUse - Return true if there is exactly one instruction using the 1870e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified register. 1880e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool hasOneUse(unsigned RegNo) const; 1890e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1900e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 1910e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified register, skipping those marked as Debug. 1920e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 1930e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 1940e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 1950e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 1960e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1970e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 1980e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// use_nodbg_empty - Return true if there are no non-Debug instructions 1990e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// using the specified register. 2000e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool use_nodbg_empty(unsigned RegNo) const { 2010e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return use_nodbg_begin(RegNo) == use_nodbg_end(); 2020e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 2030e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2040e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 2050e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// instruction using the specified register. 2060e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool hasOneNonDBGUse(unsigned RegNo) const; 2070e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2080e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// replaceRegWith - Replace all instances of FromReg with ToReg in the 2090e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 2100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// except that it also changes any definitions of the register as well. 2110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// Note that it is usually necessary to first constrain ToReg's register 2130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// class to match the FromReg constraints using: 2140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// constrainRegClass(ToReg, getRegClass(FromReg)) 2160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// That function will return NULL if the virtual registers have incompatible 2180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// constraints. 2190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void replaceRegWith(unsigned FromReg, unsigned ToReg); 2200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2210e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getRegUseDefListHead - Return the head pointer for the register use/def 2220e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// list for the specified virtual or physical register. 2230e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 2240e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (TargetRegisterInfo::isVirtualRegister(RegNo)) 2250e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return VRegInfo[RegNo].second; 2260e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return PhysRegUseDefLists[RegNo]; 2270e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 2280e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2290e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 2300e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (TargetRegisterInfo::isVirtualRegister(RegNo)) 2310e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return VRegInfo[RegNo].second; 2320e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return PhysRegUseDefLists[RegNo]; 2330e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 2340e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2350e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getVRegDef - Return the machine instr that defines the specified virtual 2360e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register or null if none is found. This assumes that the code is in SSA 2370e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// form, so there should only be one definition. 2380e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *getVRegDef(unsigned Reg) const; 2390e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2400e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getUniqueVRegDef - Return the unique machine instr that defines the 2410e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified virtual register or null if none is found. If there are 2420e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// multiple definitions or no definition, return null. 2430e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *getUniqueVRegDef(unsigned Reg) const; 2440e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2450e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// clearKillFlags - Iterate over all the uses of the given register and 2460e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// clear the kill flag from the MachineOperand. This function is used by 2470e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// optimization passes which extend register lifetimes and need only 2480e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// preserve conservative kill flag information. 2490e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void clearKillFlags(unsigned Reg) const; 2500e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2510e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#ifndef NDEBUG 2520e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void dumpUses(unsigned RegNo) const; 2530e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org#endif 2540e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2550e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant 2560e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// throughout the function. It is safe to move instructions that read such 2570e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// a physreg. 2580e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const; 2590e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2600e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 2610e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Virtual Register Info 2620e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 2630e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2640e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getRegClass - Return the register class of the specified virtual register. 2650e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2660e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetRegisterClass *getRegClass(unsigned Reg) const { 2670e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return VRegInfo[Reg].first; 2680e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 2690e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2700e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// setRegClass - Set the register class of the specified virtual register. 2710e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2720e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 2730e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2740e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// constrainRegClass - Constrain the register class of the specified virtual 2750e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register to be a common subclass of RC and the current register class, 2760e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// but only if the new class has at least MinNumRegs registers. Return the 2770e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// new register class, or NULL if no such class exists. 2780e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This should only be used when the constraint is known to be trivial, like 2790e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 2800e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2810e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetRegisterClass *constrainRegClass(unsigned Reg, 2820e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetRegisterClass *RC, 2830e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned MinNumRegs = 0); 2840e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2850e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// recomputeRegClass - Try to find a legal super-class of Reg's register 2860e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// class that still satisfies the constraints from the instructions using 2870e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// Reg. Returns true if Reg was upgraded. 2880e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2890e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This method can be used after constraints have been removed from a 2900e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// virtual register, for example after removing instructions or splitting 2910e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// the live range. 2920e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2930e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool recomputeRegClass(unsigned Reg, const TargetMachine&); 2940e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 2950e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// createVirtualRegister - Create and return a new virtual register in the 2960e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// function with the specified register class. 2970e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 2980e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 2990e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3000e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getNumVirtRegs - Return the number of virtual registers created. 3010e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// 3020e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned getNumVirtRegs() const { return VRegInfo.size(); } 3030e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3040e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// clearVirtRegs - Remove all virtual registers (after physreg assignment). 3050e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void clearVirtRegs(); 3060e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3070e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// setRegAllocationHint - Specify a register allocation hint for the 3080e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified virtual register. 3090e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 3100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org RegAllocHints[Reg].first = Type; 3110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org RegAllocHints[Reg].second = PrefReg; 3120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getRegAllocationHint - Return the register allocation hint for the 3150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// specified virtual register. 3160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org std::pair<unsigned, unsigned> 3170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org getRegAllocationHint(unsigned Reg) const { 3180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return RegAllocHints[Reg]; 3190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3210e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getSimpleHint - Return the preferred register allocation hint, or 0 if a 3220e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// standard simple hint (Type == 0) is not set. 3230e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned getSimpleHint(unsigned Reg) const { 3240e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg); 3250e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return Hint.first ? 0 : Hint.second; 3260e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3270e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3280e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3290e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 3300e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Physical Register Use Info 3310e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 3320e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3330e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// isPhysRegUsed - Return true if the specified register is used in this 3340e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// function. This only works after register allocation. 3350e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isPhysRegUsed(unsigned Reg) const { 3360e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg); 3370e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3380e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3390e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register 3400e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// is used in this function. 3410e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isPhysRegOrOverlapUsed(unsigned Reg) const { 3420e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (UsedPhysRegMask.test(Reg)) 3430e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return true; 3440e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 3450e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (UsedPhysRegs.test(*AI)) 3460e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return true; 3470e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return false; 3480e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3490e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3500e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// setPhysRegUsed - Mark the specified register used in this function. 3510e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This should only be called during and after register allocation. 3520e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); } 3530e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3540e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// addPhysRegsUsed - Mark the specified registers used in this function. 3550e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This should only be called during and after register allocation. 3560e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 3570e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3580e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used. 3590e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This corresponds to the bit mask attached to register mask operands. 3600e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { 3610e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org UsedPhysRegMask.setBitsNotInMask(RegMask); 3620e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3630e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3640e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// setPhysRegUnused - Mark the specified register unused in this function. 3650e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// This should only be called during and after register allocation. 3660e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void setPhysRegUnused(unsigned Reg) { 3670e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org UsedPhysRegs.reset(Reg); 3680e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org UsedPhysRegMask.reset(Reg); 3690e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3700e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3710e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3720e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 3730e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Reserved Register Info 3740e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 3750e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // 3760e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // The set of reserved registers must be invariant during register 3770e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // allocation. For example, the target cannot suddenly decide it needs a 3780e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // frame pointer when the register allocator has already used the frame 3790e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // pointer register for something else. 3800e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // 3810e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // These methods can be used by target hooks like hasFP() to avoid changing 3820e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // the reserved register set during register allocation. 3830e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3840e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// freezeReservedRegs - Called by the register allocator to freeze the set 3850e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// of reserved registers before allocation begins. 3860e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void freezeReservedRegs(const MachineFunction&); 3870e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3880e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called 3890e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// to ensure the set of reserved registers stays constant. 3900e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool reservedRegsFrozen() const { 3910e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return !ReservedRegs.empty(); 3920e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 3930e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 3940e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// canReserveReg - Returns true if PhysReg can be used as a reserved 3950e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// register. Any register can be reserved before freezeReservedRegs() is 3960e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// called. 3970e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool canReserveReg(unsigned PhysReg) const { 3980e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return !reservedRegsFrozen() || ReservedRegs.test(PhysReg); 3990e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4000e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4010e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4020e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 4030e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // LiveIn/LiveOut Management 4040e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org //===--------------------------------------------------------------------===// 4050e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4060e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 4070e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// is an error to add the same register to the same set more than once. 4080e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void addLiveIn(unsigned Reg, unsigned vreg = 0) { 4090e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org LiveIns.push_back(std::make_pair(Reg, vreg)); 4100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 4120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Iteration support for live in/out sets. These sets are kept in sorted 4140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // order by their register number. 4150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 4160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org livein_iterator; 4170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef std::vector<unsigned>::const_iterator liveout_iterator; 4180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org livein_iterator livein_begin() const { return LiveIns.begin(); } 4190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org livein_iterator livein_end() const { return LiveIns.end(); } 4200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool livein_empty() const { return LiveIns.empty(); } 4210e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 4220e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org liveout_iterator liveout_end() const { return LiveOuts.end(); } 4230e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool liveout_empty() const { return LiveOuts.empty(); } 4240e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4250e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isLiveIn(unsigned Reg) const; 4260e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool isLiveOut(unsigned Reg) const; 4270e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4280e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 4290e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// corresponding live-in physical register. 4300e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned getLiveInPhysReg(unsigned VReg) const; 4310e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4320e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// getLiveInVirtReg - If PReg is a live-in physical register, return the 4330e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// corresponding live-in physical register. 4340e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org unsigned getLiveInVirtReg(unsigned PReg) const; 4350e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4360e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 4370e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// into the given entry block. 4380e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 4390e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetRegisterInfo &TRI, 4400e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org const TargetInstrInfo &TII); 4410e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4420e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.orgprivate: 4430e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org void HandleVRegListReallocation(); 4440e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4450e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.orgpublic: 4460e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// defusechain_iterator - This class provides iterator support for machine 4470e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// operands in the function that use or define a specific register. If 4480e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 4490e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// returns defs. If neither are true then you are silly and it always 4500e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// returns end(). If SkipDebug is true it skips uses marked Debug 4510e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// when incrementing. 4520e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 4530e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org class defusechain_iterator 4540e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 4550e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineOperand *Op; 4560e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org explicit defusechain_iterator(MachineOperand *op) : Op(op) { 4570e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // If the first node isn't one we're interested in, advance to one that 4580e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // we are interested in. 4590e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (op) { 4600e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if ((!ReturnUses && op->isUse()) || 4610e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org (!ReturnDefs && op->isDef()) || 4620e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org (SkipDebug && op->isDebug())) 4630e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org ++*this; 4640e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4650e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4660e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org friend class MachineRegisterInfo; 4670e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org public: 4680e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef std::iterator<std::forward_iterator_tag, 4690e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr, ptrdiff_t>::reference reference; 4700e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org typedef std::iterator<std::forward_iterator_tag, 4710e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr, ptrdiff_t>::pointer pointer; 4720e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4730e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 4740e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org defusechain_iterator() : Op(0) {} 4750e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4760e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool operator==(const defusechain_iterator &x) const { 4770e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return Op == x.Op; 4780e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4790e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool operator!=(const defusechain_iterator &x) const { 4800e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return !operator==(x); 4810e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4820e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4830e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// atEnd - return true if this iterator is equal to reg_end() on the value. 4840e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org bool atEnd() const { return Op == 0; } 4850e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4860e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // Iterator traversal: forward iteration only 4870e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org defusechain_iterator &operator++() { // Preincrement 4880e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org assert(Op && "Cannot increment end iterator!"); 4890e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org Op = Op->getNextOperandForReg(); 4900e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4910e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org // If this is an operand we don't care about, skip it. 4920e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org while (Op && ((!ReturnUses && Op->isUse()) || 4930e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org (!ReturnDefs && Op->isDef()) || 4940e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org (SkipDebug && Op->isDebug()))) 4950e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org Op = Op->getNextOperandForReg(); 4960e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 4970e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return *this; 4980e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 4990e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org defusechain_iterator operator++(int) { // Postincrement 5000e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org defusechain_iterator tmp = *this; ++*this; return tmp; 5010e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 5020e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 5030e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// skipInstruction - move forward until reaching a different instruction. 5040e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// Return the skipped instruction that is no longer pointed to, or NULL if 5050e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org /// already pointing to end(). 5060e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *skipInstruction() { 5070e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (!Op) return 0; 5080e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *MI = Op->getParent(); 5090e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org do ++*this; 5100e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org while (Op && Op->getParent() == MI); 5110e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return MI; 5120e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 5130e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org 5140e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *skipBundle() { 5150e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org if (!Op) return 0; 5160e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org MachineInstr *MI = getBundleStart(Op->getParent()); 5170e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org do ++*this; 5180e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org while (Op && getBundleStart(Op->getParent()) == MI); 5190e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org return MI; 5200e118e7129884fbea117e78d6f2068139a414dbhenrike@webrtc.org } 521 522 MachineOperand &getOperand() const { 523 assert(Op && "Cannot dereference end iterator!"); 524 return *Op; 525 } 526 527 /// getOperandNo - Return the operand # of this MachineOperand in its 528 /// MachineInstr. 529 unsigned getOperandNo() const { 530 assert(Op && "Cannot dereference end iterator!"); 531 return Op - &Op->getParent()->getOperand(0); 532 } 533 534 // Retrieve a reference to the current operand. 535 MachineInstr &operator*() const { 536 assert(Op && "Cannot dereference end iterator!"); 537 return *Op->getParent(); 538 } 539 540 MachineInstr *operator->() const { 541 assert(Op && "Cannot dereference end iterator!"); 542 return Op->getParent(); 543 } 544 }; 545 546}; 547 548} // End llvm namespace 549 550#endif 551