MachineRegisterInfo.h revision 82b07dc4995d48065bd95affff4d8513a5cad4f2
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include <vector> 20 21namespace llvm { 22 23/// MachineRegisterInfo - Keep track of information for virtual and physical 24/// registers, including vreg register classes, use/def chains for registers, 25/// etc. 26class MachineRegisterInfo { 27 /// VRegInfo - Information we keep for each virtual register. The entries in 28 /// this vector are actually converted to vreg numbers by adding the 29 /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 30 /// 31 /// Each element in this list contains the register class of the vreg and the 32 /// start of the use/def list for the register. 33 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 34 35 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 36 /// virtual registers. For each target register class, it keeps a list of 37 /// virtual registers belonging to the class. 38 std::vector<std::vector<unsigned> > RegClass2VRegMap; 39 40 /// RegAllocHints - This vector records register allocation hints for virtual 41 /// registers. For each virtual register, it keeps a register and hint type 42 /// pair making up the allocation hint. Hint type is target specific except 43 /// for the value 0 which means the second value of the pair is the preferred 44 /// register for allocation. For example, if the hint is <0, 1024>, it means 45 /// the allocator should prefer the physical register allocated to the virtual 46 /// register of the hint. 47 std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 48 49 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 50 /// physical registers. 51 MachineOperand **PhysRegUseDefLists; 52 53 /// UsedPhysRegs - This is a bit vector that is computed and set by the 54 /// register allocator, and must be kept up to date by passes that run after 55 /// register allocation (though most don't modify this). This is used 56 /// so that the code generator knows which callee save registers to save and 57 /// for other target specific uses. 58 BitVector UsedPhysRegs; 59 60 /// LiveIns/LiveOuts - Keep track of the physical registers that are 61 /// livein/liveout of the function. Live in values are typically arguments in 62 /// registers, live out values are typically return values in registers. 63 /// LiveIn values are allowed to have virtual registers associated with them, 64 /// stored in the second element. 65 std::vector<std::pair<unsigned, unsigned> > LiveIns; 66 std::vector<unsigned> LiveOuts; 67 68 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 70public: 71 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 72 ~MachineRegisterInfo(); 73 74 //===--------------------------------------------------------------------===// 75 // Register Info 76 //===--------------------------------------------------------------------===// 77 78 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 79 /// and uses of a register within the MachineFunction that corresponds to this 80 /// MachineRegisterInfo object. 81 template<bool Uses, bool Defs, bool SkipDebug> 82 class defusechain_iterator; 83 84 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 85 /// register. 86 typedef defusechain_iterator<true,true,false> reg_iterator; 87 reg_iterator reg_begin(unsigned RegNo) const { 88 return reg_iterator(getRegUseDefListHead(RegNo)); 89 } 90 static reg_iterator reg_end() { return reg_iterator(0); } 91 92 /// reg_empty - Return true if there are no instructions using or defining the 93 /// specified register (it may be live-in). 94 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 95 96 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 97 typedef defusechain_iterator<false,true,false> def_iterator; 98 def_iterator def_begin(unsigned RegNo) const { 99 return def_iterator(getRegUseDefListHead(RegNo)); 100 } 101 static def_iterator def_end() { return def_iterator(0); } 102 103 /// def_empty - Return true if there are no instructions defining the 104 /// specified register (it may be live-in). 105 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 106 107 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 108 typedef defusechain_iterator<true,false,false> use_iterator; 109 use_iterator use_begin(unsigned RegNo) const { 110 return use_iterator(getRegUseDefListHead(RegNo)); 111 } 112 static use_iterator use_end() { return use_iterator(0); } 113 114 /// use_empty - Return true if there are no instructions using the specified 115 /// register. 116 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 117 118 /// hasOneUse - Return true if there is exactly one instruction using the 119 /// specified register. 120 bool hasOneUse(unsigned RegNo) const; 121 122 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 123 /// specified register, skipping those marked as Debug. 124 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 125 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 126 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 127 } 128 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 129 130 /// use_nodbg_empty - Return true if there are no non-Debug instructions 131 /// using the specified register. 132 bool use_nodbg_empty(unsigned RegNo) const { 133 return use_nodbg_begin(RegNo) == use_nodbg_end(); 134 } 135 136 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 137 /// instruction using the specified register. 138 bool hasOneNonDBGUse(unsigned RegNo) const; 139 140 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 141 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 142 /// except that it also changes any definitions of the register as well. 143 void replaceRegWith(unsigned FromReg, unsigned ToReg); 144 145 /// getRegUseDefListHead - Return the head pointer for the register use/def 146 /// list for the specified virtual or physical register. 147 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 148 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 149 return PhysRegUseDefLists[RegNo]; 150 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 151 return VRegInfo[RegNo].second; 152 } 153 154 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 155 if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 156 return PhysRegUseDefLists[RegNo]; 157 RegNo -= TargetRegisterInfo::FirstVirtualRegister; 158 return VRegInfo[RegNo].second; 159 } 160 161 /// getVRegDef - Return the machine instr that defines the specified virtual 162 /// register or null if none is found. This assumes that the code is in SSA 163 /// form, so there should only be one definition. 164 MachineInstr *getVRegDef(unsigned Reg) const; 165 166#ifndef NDEBUG 167 void dumpUses(unsigned RegNo) const; 168#endif 169 170 //===--------------------------------------------------------------------===// 171 // Virtual Register Info 172 //===--------------------------------------------------------------------===// 173 174 /// getRegClass - Return the register class of the specified virtual register. 175 /// 176 const TargetRegisterClass *getRegClass(unsigned Reg) const { 177 Reg -= TargetRegisterInfo::FirstVirtualRegister; 178 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 179 return VRegInfo[Reg].first; 180 } 181 182 /// setRegClass - Set the register class of the specified virtual register. 183 /// 184 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 185 186 /// createVirtualRegister - Create and return a new virtual register in the 187 /// function with the specified register class. 188 /// 189 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 190 191 /// getLastVirtReg - Return the highest currently assigned virtual register. 192 /// 193 unsigned getLastVirtReg() const { 194 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 195 } 196 197 /// getRegClassVirtRegs - Return the list of virtual registers of the given 198 /// target register class. 199 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 200 return RegClass2VRegMap[RC->getID()]; 201 } 202 203 /// setRegAllocationHint - Specify a register allocation hint for the 204 /// specified virtual register. 205 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 206 Reg -= TargetRegisterInfo::FirstVirtualRegister; 207 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 208 RegAllocHints[Reg].first = Type; 209 RegAllocHints[Reg].second = PrefReg; 210 } 211 212 /// getRegAllocationHint - Return the register allocation hint for the 213 /// specified virtual register. 214 std::pair<unsigned, unsigned> 215 getRegAllocationHint(unsigned Reg) const { 216 Reg -= TargetRegisterInfo::FirstVirtualRegister; 217 assert(Reg < VRegInfo.size() && "Invalid vreg!"); 218 return RegAllocHints[Reg]; 219 } 220 221 //===--------------------------------------------------------------------===// 222 // Physical Register Use Info 223 //===--------------------------------------------------------------------===// 224 225 /// isPhysRegUsed - Return true if the specified register is used in this 226 /// function. This only works after register allocation. 227 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 228 229 /// setPhysRegUsed - Mark the specified register used in this function. 230 /// This should only be called during and after register allocation. 231 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 232 233 /// addPhysRegsUsed - Mark the specified registers used in this function. 234 /// This should only be called during and after register allocation. 235 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 236 237 /// setPhysRegUnused - Mark the specified register unused in this function. 238 /// This should only be called during and after register allocation. 239 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 240 241 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 242 /// subregisters. That means that if R is used, so are all subregisters. 243 void closePhysRegsUsed(const TargetRegisterInfo&); 244 245 //===--------------------------------------------------------------------===// 246 // LiveIn/LiveOut Management 247 //===--------------------------------------------------------------------===// 248 249 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 250 /// is an error to add the same register to the same set more than once. 251 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 252 LiveIns.push_back(std::make_pair(Reg, vreg)); 253 } 254 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 255 256 // Iteration support for live in/out sets. These sets are kept in sorted 257 // order by their register number. 258 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 259 livein_iterator; 260 typedef std::vector<unsigned>::const_iterator liveout_iterator; 261 livein_iterator livein_begin() const { return LiveIns.begin(); } 262 livein_iterator livein_end() const { return LiveIns.end(); } 263 bool livein_empty() const { return LiveIns.empty(); } 264 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 265 liveout_iterator liveout_end() const { return LiveOuts.end(); } 266 bool liveout_empty() const { return LiveOuts.empty(); } 267 268 bool isLiveIn(unsigned Reg) const; 269 bool isLiveOut(unsigned Reg) const; 270 271 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 272 /// corresponding live-in physical register. 273 unsigned getLiveInPhysReg(unsigned VReg) const; 274 275 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 276 /// into the given entry block. 277 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 278 const TargetRegisterInfo &TRI, 279 const TargetInstrInfo &TII); 280 281private: 282 void HandleVRegListReallocation(); 283 284public: 285 /// defusechain_iterator - This class provides iterator support for machine 286 /// operands in the function that use or define a specific register. If 287 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 288 /// returns defs. If neither are true then you are silly and it always 289 /// returns end(). If SkipDebug is true it skips uses marked Debug 290 /// when incrementing. 291 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 292 class defusechain_iterator 293 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 294 MachineOperand *Op; 295 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 296 // If the first node isn't one we're interested in, advance to one that 297 // we are interested in. 298 if (op) { 299 if ((!ReturnUses && op->isUse()) || 300 (!ReturnDefs && op->isDef()) || 301 (SkipDebug && op->isDebug())) 302 ++*this; 303 } 304 } 305 friend class MachineRegisterInfo; 306 public: 307 typedef std::iterator<std::forward_iterator_tag, 308 MachineInstr, ptrdiff_t>::reference reference; 309 typedef std::iterator<std::forward_iterator_tag, 310 MachineInstr, ptrdiff_t>::pointer pointer; 311 312 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 313 defusechain_iterator() : Op(0) {} 314 315 bool operator==(const defusechain_iterator &x) const { 316 return Op == x.Op; 317 } 318 bool operator!=(const defusechain_iterator &x) const { 319 return !operator==(x); 320 } 321 322 /// atEnd - return true if this iterator is equal to reg_end() on the value. 323 bool atEnd() const { return Op == 0; } 324 325 // Iterator traversal: forward iteration only 326 defusechain_iterator &operator++() { // Preincrement 327 assert(Op && "Cannot increment end iterator!"); 328 Op = Op->getNextOperandForReg(); 329 330 // If this is an operand we don't care about, skip it. 331 while (Op && ((!ReturnUses && Op->isUse()) || 332 (!ReturnDefs && Op->isDef()) || 333 (SkipDebug && Op->isDebug()))) 334 Op = Op->getNextOperandForReg(); 335 336 return *this; 337 } 338 defusechain_iterator operator++(int) { // Postincrement 339 defusechain_iterator tmp = *this; ++*this; return tmp; 340 } 341 342 MachineOperand &getOperand() const { 343 assert(Op && "Cannot dereference end iterator!"); 344 return *Op; 345 } 346 347 /// getOperandNo - Return the operand # of this MachineOperand in its 348 /// MachineInstr. 349 unsigned getOperandNo() const { 350 assert(Op && "Cannot dereference end iterator!"); 351 return Op - &Op->getParent()->getOperand(0); 352 } 353 354 // Retrieve a reference to the current operand. 355 MachineInstr &operator*() const { 356 assert(Op && "Cannot dereference end iterator!"); 357 return *Op->getParent(); 358 } 359 360 MachineInstr *operator->() const { 361 assert(Op && "Cannot dereference end iterator!"); 362 return Op->getParent(); 363 } 364 }; 365 366}; 367 368} // End llvm namespace 369 370#endif 371