MachineRegisterInfo.h revision c66c78c6846631a9f6a44fee69d218f900e63140
12a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 25821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 35821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// The LLVM Compiler Infrastructure 45821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 5b2df76ea8fec9e32f6f3718986dba0d95315b29cTorne (Richard Coles)// This file is distributed under the University of Illinois Open Source 65821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// License. See LICENSE.TXT for details. 75821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 85821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 95821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// This file defines the MachineRegisterInfo class. 115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)// 125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)//===----------------------------------------------------------------------===// 135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/Target/TargetRegisterInfo.h" 185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include "llvm/ADT/BitVector.h" 195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#include <vector> 205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)namespace llvm { 22c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) 232a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles)/// MachineRegisterInfo - Keep track of information for virtual and physical 247dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch/// registers, including vreg register classes, use/def chains for registers, 255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)/// etc. 265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)class MachineRegisterInfo { 275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// VRegInfo - Information we keep for each virtual register. The entries in 285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// this vector are actually converted to vreg numbers by adding the 295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// TargetRegisterInfo::FirstVirtualRegister delta to their index. 305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Each element in this list contains the register class of the vreg and the 325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// start of the use/def list for the register. 335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo; 345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to 365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// virtual registers. For each target register class, it keeps a list of 375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// virtual registers belonging to the class. 385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::vector<std::vector<unsigned> > RegClass2VRegMap; 395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// RegAllocHints - This vector records register allocation hints for virtual 415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// registers. For each virtual register, it keeps a register and hint type 425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// pair making up the allocation hint. Hint type is target specific except 435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// for the value 0 which means the second value of the pair is the preferred 445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register for allocation. For example, if the hint is <0, 1024>, it means 452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// the allocator should prefer the physical register allocated to the virtual 465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register of the hint. 472a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) std::vector<std::pair<unsigned, unsigned> > RegAllocHints; 485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 492a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// PhysRegUseDefLists - This is an array of the head of the use/def list for 505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// physical registers. 512a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) MachineOperand **PhysRegUseDefLists; 525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// UsedPhysRegs - This is a bit vector that is computed and set by the 545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register allocator, and must be kept up to date by passes that run after 555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register allocation (though most don't modify this). This is used 565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// so that the code generator knows which callee save registers to save and 575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// for other target specific uses. 585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) BitVector UsedPhysRegs; 59a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// LiveIns/LiveOuts - Keep track of the physical registers that are 615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// livein/liveout of the function. Live in values are typically arguments in 625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// registers, live out values are typically return values in registers. 635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// LiveIn values are allowed to have virtual registers associated with them, 645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// stored in the second element. 655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::vector<std::pair<unsigned, unsigned> > LiveIns; 665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::vector<unsigned> LiveOuts; 675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 68a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 69a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ~MachineRegisterInfo(); 735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Register Info 765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 772a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reg_begin/reg_end - Provide iteration support to walk over all definitions 795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// and uses of a register within the MachineFunction that corresponds to this 805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// MachineRegisterInfo object. 812a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) template<bool Uses, bool Defs, bool SkipDebug> 825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class defusechain_iterator; 832a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) 845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register. 865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<true,true,false> reg_iterator; 872a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) reg_iterator reg_begin(unsigned RegNo) const { 885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return reg_iterator(getRegUseDefListHead(RegNo)); 892a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) } 905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static reg_iterator reg_end() { return reg_iterator(0); } 915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reg_empty - Return true if there are no instructions using or defining the 932a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// specified register (it may be live-in). 945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// of the specified register, skipping those marked as Debug. 98c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 1005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 1015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 1035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// reg_nodbg_empty - Return true if the only instructions using or defining 1055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// Reg are Debug instructions. 1065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool reg_nodbg_empty(unsigned RegNo) const { 1075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 1085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 1115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<false,true,false> def_iterator; 1125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) def_iterator def_begin(unsigned RegNo) const { 113c2e0dbddbe15c98d52c4786dac06cb8952a8ae6dTorne (Richard Coles) return def_iterator(getRegUseDefListHead(RegNo)); 1145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static def_iterator def_end() { return def_iterator(0); } 1165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// def_empty - Return true if there are no instructions defining the 1185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified register (it may be live-in). 1195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 1205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 1225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<true,false,false> use_iterator; 1235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) use_iterator use_begin(unsigned RegNo) const { 1245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return use_iterator(getRegUseDefListHead(RegNo)); 1255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) static use_iterator use_end() { return use_iterator(0); } 1275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_empty - Return true if there are no instructions using the specified 1295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// register. 1305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 1315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasOneUse - Return true if there is exactly one instruction using the 1335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified register. 1345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool hasOneUse(unsigned RegNo) const; 1355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 1375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified register, skipping those marked as Debug. 1385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 1395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 1405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 1415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1422a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 1435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// use_nodbg_empty - Return true if there are no non-Debug instructions 1455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// using the specified register. 1465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool use_nodbg_empty(unsigned RegNo) const { 1475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return use_nodbg_begin(RegNo) == use_nodbg_end(); 1485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 1515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// instruction using the specified register. 1525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool hasOneNonDBGUse(unsigned RegNo) const; 1535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// replaceRegWith - Replace all instances of FromReg with ToReg in the 1555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 1565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// except that it also changes any definitions of the register as well. 1575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void replaceRegWith(unsigned FromReg, unsigned ToReg); 1585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegUseDefListHead - Return the head pointer for the register use/def 1605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// list for the specified virtual or physical register. 1615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 1625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return PhysRegUseDefLists[RegNo]; 1645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return VRegInfo[RegNo].second; 1665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 1695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (RegNo < TargetRegisterInfo::FirstVirtualRegister) 1705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return PhysRegUseDefLists[RegNo]; 1715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegNo -= TargetRegisterInfo::FirstVirtualRegister; 1725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return VRegInfo[RegNo].second; 1735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 1743551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) 1753551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// getVRegDef - Return the machine instr that defines the specified virtual 1763551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// register or null if none is found. This assumes that the code is in SSA 1773551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) /// form, so there should only be one definition. 1783551c9c881056c480085172ff9840cab31610854Torne (Richard Coles) MachineInstr *getVRegDef(unsigned Reg) const; 1795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// clearKillFlags - Iterate over all the uses of the given register and 1815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// clear the kill flag from the MachineOperand. This function is used by 1825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// optimization passes which extend register lifetimes and need only 1835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// preserve conservative kill flag information. 1845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void clearKillFlags(unsigned Reg) const; 1855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#ifndef NDEBUG 1875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void dumpUses(unsigned RegNo) const; 1885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 1895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 1915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Virtual Register Info 1925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 1935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 1945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegClass - Return the register class of the specified virtual register. 1955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 1965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterClass *getRegClass(unsigned Reg) const { 1975821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Reg -= TargetRegisterInfo::FirstVirtualRegister; 1985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Reg < VRegInfo.size() && "Invalid vreg!"); 1995821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return VRegInfo[Reg].first; 2005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setRegClass - Set the register class of the specified virtual register. 2035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 2055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2065821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// createVirtualRegister - Create and return a new virtual register in the 2075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// function with the specified register class. 2085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 2105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getLastVirtReg - Return the highest currently assigned virtual register. 2125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// 2135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getLastVirtReg() const { 2145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1; 2155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegClassVirtRegs - Return the list of virtual registers of the given 2185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// target register class. 2195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { 2205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return RegClass2VRegMap[RC->getID()]; 2215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setRegAllocationHint - Specify a register allocation hint for the 2245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified virtual register. 2255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 2265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Reg -= TargetRegisterInfo::FirstVirtualRegister; 2275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Reg < VRegInfo.size() && "Invalid vreg!"); 2285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegAllocHints[Reg].first = Type; 2295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) RegAllocHints[Reg].second = PrefReg; 2305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getRegAllocationHint - Return the register allocation hint for the 2335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// specified virtual register. 2345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) std::pair<unsigned, unsigned> 2355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) getRegAllocationHint(unsigned Reg) const { 2365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Reg -= TargetRegisterInfo::FirstVirtualRegister; 2375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Reg < VRegInfo.size() && "Invalid vreg!"); 2385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return RegAllocHints[Reg]; 2395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Physical Register Use Info 2435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2455821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// isPhysRegUsed - Return true if the specified register is used in this 2465821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// function. This only works after register allocation. 2475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 2485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// setPhysRegUsed - Mark the specified register used in this function. 2505821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be called during and after register allocation. 2515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 2525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// addPhysRegsUsed - Mark the specified registers used in this function. 2545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// This should only be called during and after register allocation. 2555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 2565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2572a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// setPhysRegUnused - Mark the specified register unused in this function. 2582a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// This should only be called during and after register allocation. 2595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 2605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 2625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// subregisters. That means that if R is used, so are all subregisters. 2635821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void closePhysRegsUsed(const TargetRegisterInfo&); 2645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2665821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // LiveIn/LiveOut Management 2675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) //===--------------------------------------------------------------------===// 2685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2692a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 2702a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) /// is an error to add the same register to the same set more than once. 2715821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void addLiveIn(unsigned Reg, unsigned vreg = 0) { 2725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) LiveIns.push_back(std::make_pair(Reg, vreg)); 2735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 2745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 2755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2762a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Iteration support for live in/out sets. These sets are kept in sorted 2775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // order by their register number. 2785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 2795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator; 2805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef std::vector<unsigned>::const_iterator liveout_iterator; 2815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator livein_begin() const { return LiveIns.begin(); } 2825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) livein_iterator livein_end() const { return LiveIns.end(); } 2835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool livein_empty() const { return LiveIns.empty(); } 2845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 2855821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) liveout_iterator liveout_end() const { return LiveOuts.end(); } 2865821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool liveout_empty() const { return LiveOuts.empty(); } 2875821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2885821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isLiveIn(unsigned Reg) const; 2895821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool isLiveOut(unsigned Reg) const; 2905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 2925821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// corresponding live-in physical register. 2935821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getLiveInPhysReg(unsigned VReg) const; 2945821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 2955821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 2965821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// into the given entry block. 2972a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 2985821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) const TargetRegisterInfo &TRI, 2992a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) const TargetInstrInfo &TII); 3005821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3015821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)private: 3025821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) void HandleVRegListReallocation(); 3035821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3045821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)public: 3055821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// defusechain_iterator - This class provides iterator support for machine 306eb525c5499e34cc9c4b825d6d9e75bb07cc06aceBen Murdoch /// operands in the function that use or define a specific register. If 3075821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 3085821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// returns defs. If neither are true then you are silly and it always 3095821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// returns end(). If SkipDebug is true it skips uses marked Debug 3105821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// when incrementing. 3115821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 3125821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) class defusechain_iterator 3135821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 3145821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineOperand *Op; 3155821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) explicit defusechain_iterator(MachineOperand *op) : Op(op) { 3165821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // If the first node isn't one we're interested in, advance to one that 3175821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // we are interested in. 3185821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if (op) { 3195821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) if ((!ReturnUses && op->isUse()) || 3205821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (!ReturnDefs && op->isDef()) || 3215821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (SkipDebug && op->isDebug())) 3225821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) ++*this; 3235821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3245821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3255821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) friend class MachineRegisterInfo; 3265821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) public: 3275821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef std::iterator<std::forward_iterator_tag, 3285821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr, ptrdiff_t>::reference reference; 3295821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) typedef std::iterator<std::forward_iterator_tag, 3305821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr, ptrdiff_t>::pointer pointer; 3315821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3325821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 3335821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) defusechain_iterator() : Op(0) {} 3345821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3355821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool operator==(const defusechain_iterator &x) const { 3365821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Op == x.Op; 3375821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3385821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool operator!=(const defusechain_iterator &x) const { 3395821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return !operator==(x); 3405821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3415821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3425821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// atEnd - return true if this iterator is equal to reg_end() on the value. 3435821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) bool atEnd() const { return Op == 0; } 3445821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3452a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) // Iterator traversal: forward iteration only 3462a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) defusechain_iterator &operator++() { // Preincrement 3475821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Op && "Cannot increment end iterator!"); 3485821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Op = Op->getNextOperandForReg(); 3495821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3507dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch // If this is an operand we don't care about, skip it. 3515821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) while (Op && ((!ReturnUses && Op->isUse()) || 3525821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (!ReturnDefs && Op->isDef()) || 3535821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) (SkipDebug && Op->isDebug()))) 3545821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) Op = Op->getNextOperandForReg(); 3555821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3565821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return *this; 3575821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3585821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) defusechain_iterator operator++(int) { // Postincrement 3595821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) defusechain_iterator tmp = *this; ++*this; return tmp; 3605821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3615821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3625821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineOperand &getOperand() const { 3632a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 3645821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return *Op; 3655821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3667dbb3d5cf0c15f500944d211057644d6a2f37371Ben Murdoch 3675821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// getOperandNo - Return the operand # of this MachineOperand in its 3685821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) /// MachineInstr. 3695821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) unsigned getOperandNo() const { 3705821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 3712a99a7e74a7f215066514fe81d2bfa6639d9edddTorne (Richard Coles) return Op - &Op->getParent()->getOperand(0); 3725821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3735821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3745821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) // Retrieve a reference to the current operand. 3755821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr &operator*() const { 3765821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 3775821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return *Op->getParent(); 3785821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3795821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) 3805821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) MachineInstr *operator->() const { 3815821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) assert(Op && "Cannot dereference end iterator!"); 3825821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) return Op->getParent(); 3835821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) } 3845821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles) }; 385a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 386a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)}; 387a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 388a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles)} // End llvm namespace 389a36e5920737c6adbddd3e43b760e5de8431db6e0Torne (Richard Coles) 3905821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)#endif 3915821806d5e7f356e8fa4b058a389a808ea183019Torne (Richard Coles)