MachineRegisterInfo.h revision f46e7e3d7ff56d91572350c45ade83f4deea0139
1//===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the MachineRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H 15#define LLVM_CODEGEN_MACHINEREGISTERINFO_H 16 17#include "llvm/Target/TargetRegisterInfo.h" 18#include "llvm/ADT/BitVector.h" 19#include "llvm/ADT/IndexedMap.h" 20#include <vector> 21 22namespace llvm { 23 24/// MachineRegisterInfo - Keep track of information for virtual and physical 25/// registers, including vreg register classes, use/def chains for registers, 26/// etc. 27class MachineRegisterInfo { 28 /// VRegInfo - Information we keep for each virtual register. 29 /// 30 /// Each element in this list contains the register class of the vreg and the 31 /// start of the use/def list for the register. 32 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>, 33 VirtReg2IndexFunctor> VRegInfo; 34 35 /// RegAllocHints - This vector records register allocation hints for virtual 36 /// registers. For each virtual register, it keeps a register and hint type 37 /// pair making up the allocation hint. Hint type is target specific except 38 /// for the value 0 which means the second value of the pair is the preferred 39 /// register for allocation. For example, if the hint is <0, 1024>, it means 40 /// the allocator should prefer the physical register allocated to the virtual 41 /// register of the hint. 42 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints; 43 44 /// PhysRegUseDefLists - This is an array of the head of the use/def list for 45 /// physical registers. 46 MachineOperand **PhysRegUseDefLists; 47 48 /// UsedPhysRegs - This is a bit vector that is computed and set by the 49 /// register allocator, and must be kept up to date by passes that run after 50 /// register allocation (though most don't modify this). This is used 51 /// so that the code generator knows which callee save registers to save and 52 /// for other target specific uses. 53 BitVector UsedPhysRegs; 54 55 /// LiveIns/LiveOuts - Keep track of the physical registers that are 56 /// livein/liveout of the function. Live in values are typically arguments in 57 /// registers, live out values are typically return values in registers. 58 /// LiveIn values are allowed to have virtual registers associated with them, 59 /// stored in the second element. 60 std::vector<std::pair<unsigned, unsigned> > LiveIns; 61 std::vector<unsigned> LiveOuts; 62 63 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT 64 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT 65public: 66 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI); 67 ~MachineRegisterInfo(); 68 69 //===--------------------------------------------------------------------===// 70 // Register Info 71 //===--------------------------------------------------------------------===// 72 73 /// reg_begin/reg_end - Provide iteration support to walk over all definitions 74 /// and uses of a register within the MachineFunction that corresponds to this 75 /// MachineRegisterInfo object. 76 template<bool Uses, bool Defs, bool SkipDebug> 77 class defusechain_iterator; 78 79 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified 80 /// register. 81 typedef defusechain_iterator<true,true,false> reg_iterator; 82 reg_iterator reg_begin(unsigned RegNo) const { 83 return reg_iterator(getRegUseDefListHead(RegNo)); 84 } 85 static reg_iterator reg_end() { return reg_iterator(0); } 86 87 /// reg_empty - Return true if there are no instructions using or defining the 88 /// specified register (it may be live-in). 89 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } 90 91 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses 92 /// of the specified register, skipping those marked as Debug. 93 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; 94 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { 95 return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); 96 } 97 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } 98 99 /// reg_nodbg_empty - Return true if the only instructions using or defining 100 /// Reg are Debug instructions. 101 bool reg_nodbg_empty(unsigned RegNo) const { 102 return reg_nodbg_begin(RegNo) == reg_nodbg_end(); 103 } 104 105 /// def_iterator/def_begin/def_end - Walk all defs of the specified register. 106 typedef defusechain_iterator<false,true,false> def_iterator; 107 def_iterator def_begin(unsigned RegNo) const { 108 return def_iterator(getRegUseDefListHead(RegNo)); 109 } 110 static def_iterator def_end() { return def_iterator(0); } 111 112 /// def_empty - Return true if there are no instructions defining the 113 /// specified register (it may be live-in). 114 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); } 115 116 /// use_iterator/use_begin/use_end - Walk all uses of the specified register. 117 typedef defusechain_iterator<true,false,false> use_iterator; 118 use_iterator use_begin(unsigned RegNo) const { 119 return use_iterator(getRegUseDefListHead(RegNo)); 120 } 121 static use_iterator use_end() { return use_iterator(0); } 122 123 /// use_empty - Return true if there are no instructions using the specified 124 /// register. 125 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); } 126 127 /// hasOneUse - Return true if there is exactly one instruction using the 128 /// specified register. 129 bool hasOneUse(unsigned RegNo) const; 130 131 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the 132 /// specified register, skipping those marked as Debug. 133 typedef defusechain_iterator<true,false,true> use_nodbg_iterator; 134 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const { 135 return use_nodbg_iterator(getRegUseDefListHead(RegNo)); 136 } 137 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); } 138 139 /// use_nodbg_empty - Return true if there are no non-Debug instructions 140 /// using the specified register. 141 bool use_nodbg_empty(unsigned RegNo) const { 142 return use_nodbg_begin(RegNo) == use_nodbg_end(); 143 } 144 145 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug 146 /// instruction using the specified register. 147 bool hasOneNonDBGUse(unsigned RegNo) const; 148 149 /// replaceRegWith - Replace all instances of FromReg with ToReg in the 150 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y), 151 /// except that it also changes any definitions of the register as well. 152 void replaceRegWith(unsigned FromReg, unsigned ToReg); 153 154 /// getRegUseDefListHead - Return the head pointer for the register use/def 155 /// list for the specified virtual or physical register. 156 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { 157 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 158 return VRegInfo[RegNo].second; 159 return PhysRegUseDefLists[RegNo]; 160 } 161 162 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 163 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 164 return VRegInfo[RegNo].second; 165 return PhysRegUseDefLists[RegNo]; 166 } 167 168 /// getVRegDef - Return the machine instr that defines the specified virtual 169 /// register or null if none is found. This assumes that the code is in SSA 170 /// form, so there should only be one definition. 171 MachineInstr *getVRegDef(unsigned Reg) const; 172 173 /// clearKillFlags - Iterate over all the uses of the given register and 174 /// clear the kill flag from the MachineOperand. This function is used by 175 /// optimization passes which extend register lifetimes and need only 176 /// preserve conservative kill flag information. 177 void clearKillFlags(unsigned Reg) const; 178 179#ifndef NDEBUG 180 void dumpUses(unsigned RegNo) const; 181#endif 182 183 //===--------------------------------------------------------------------===// 184 // Virtual Register Info 185 //===--------------------------------------------------------------------===// 186 187 /// getRegClass - Return the register class of the specified virtual register. 188 /// 189 const TargetRegisterClass *getRegClass(unsigned Reg) const { 190 return VRegInfo[Reg].first; 191 } 192 193 /// setRegClass - Set the register class of the specified virtual register. 194 /// 195 void setRegClass(unsigned Reg, const TargetRegisterClass *RC); 196 197 /// constrainRegClass - Constrain the register class of the specified virtual 198 /// register to be a common subclass of RC and the current register class. 199 /// Return the new register class, or NULL if no such class exists. 200 /// This should only be used when the constraint is known to be trivial, like 201 /// GR32 -> GR32_NOSP. Beware of increasing register pressure. 202 const TargetRegisterClass *constrainRegClass(unsigned Reg, 203 const TargetRegisterClass *RC); 204 205 /// createVirtualRegister - Create and return a new virtual register in the 206 /// function with the specified register class. 207 /// 208 unsigned createVirtualRegister(const TargetRegisterClass *RegClass); 209 210 /// getNumVirtRegs - Return the number of virtual registers created. 211 /// 212 unsigned getNumVirtRegs() const { return VRegInfo.size(); } 213 214 /// setRegAllocationHint - Specify a register allocation hint for the 215 /// specified virtual register. 216 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { 217 RegAllocHints[Reg].first = Type; 218 RegAllocHints[Reg].second = PrefReg; 219 } 220 221 /// getRegAllocationHint - Return the register allocation hint for the 222 /// specified virtual register. 223 std::pair<unsigned, unsigned> 224 getRegAllocationHint(unsigned Reg) const { 225 return RegAllocHints[Reg]; 226 } 227 228 //===--------------------------------------------------------------------===// 229 // Physical Register Use Info 230 //===--------------------------------------------------------------------===// 231 232 /// isPhysRegUsed - Return true if the specified register is used in this 233 /// function. This only works after register allocation. 234 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; } 235 236 /// setPhysRegUsed - Mark the specified register used in this function. 237 /// This should only be called during and after register allocation. 238 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } 239 240 /// addPhysRegsUsed - Mark the specified registers used in this function. 241 /// This should only be called during and after register allocation. 242 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } 243 244 /// setPhysRegUnused - Mark the specified register unused in this function. 245 /// This should only be called during and after register allocation. 246 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } 247 248 /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over 249 /// subregisters. That means that if R is used, so are all subregisters. 250 void closePhysRegsUsed(const TargetRegisterInfo&); 251 252 //===--------------------------------------------------------------------===// 253 // LiveIn/LiveOut Management 254 //===--------------------------------------------------------------------===// 255 256 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it 257 /// is an error to add the same register to the same set more than once. 258 void addLiveIn(unsigned Reg, unsigned vreg = 0) { 259 LiveIns.push_back(std::make_pair(Reg, vreg)); 260 } 261 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); } 262 263 // Iteration support for live in/out sets. These sets are kept in sorted 264 // order by their register number. 265 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator 266 livein_iterator; 267 typedef std::vector<unsigned>::const_iterator liveout_iterator; 268 livein_iterator livein_begin() const { return LiveIns.begin(); } 269 livein_iterator livein_end() const { return LiveIns.end(); } 270 bool livein_empty() const { return LiveIns.empty(); } 271 liveout_iterator liveout_begin() const { return LiveOuts.begin(); } 272 liveout_iterator liveout_end() const { return LiveOuts.end(); } 273 bool liveout_empty() const { return LiveOuts.empty(); } 274 275 bool isLiveIn(unsigned Reg) const; 276 bool isLiveOut(unsigned Reg) const; 277 278 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the 279 /// corresponding live-in physical register. 280 unsigned getLiveInPhysReg(unsigned VReg) const; 281 282 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 283 /// corresponding live-in physical register. 284 unsigned getLiveInVirtReg(unsigned PReg) const; 285 286 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers 287 /// into the given entry block. 288 void EmitLiveInCopies(MachineBasicBlock *EntryMBB, 289 const TargetRegisterInfo &TRI, 290 const TargetInstrInfo &TII); 291 292private: 293 void HandleVRegListReallocation(); 294 295public: 296 /// defusechain_iterator - This class provides iterator support for machine 297 /// operands in the function that use or define a specific register. If 298 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it 299 /// returns defs. If neither are true then you are silly and it always 300 /// returns end(). If SkipDebug is true it skips uses marked Debug 301 /// when incrementing. 302 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug> 303 class defusechain_iterator 304 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> { 305 MachineOperand *Op; 306 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 307 // If the first node isn't one we're interested in, advance to one that 308 // we are interested in. 309 if (op) { 310 if ((!ReturnUses && op->isUse()) || 311 (!ReturnDefs && op->isDef()) || 312 (SkipDebug && op->isDebug())) 313 ++*this; 314 } 315 } 316 friend class MachineRegisterInfo; 317 public: 318 typedef std::iterator<std::forward_iterator_tag, 319 MachineInstr, ptrdiff_t>::reference reference; 320 typedef std::iterator<std::forward_iterator_tag, 321 MachineInstr, ptrdiff_t>::pointer pointer; 322 323 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 324 defusechain_iterator() : Op(0) {} 325 326 bool operator==(const defusechain_iterator &x) const { 327 return Op == x.Op; 328 } 329 bool operator!=(const defusechain_iterator &x) const { 330 return !operator==(x); 331 } 332 333 /// atEnd - return true if this iterator is equal to reg_end() on the value. 334 bool atEnd() const { return Op == 0; } 335 336 // Iterator traversal: forward iteration only 337 defusechain_iterator &operator++() { // Preincrement 338 assert(Op && "Cannot increment end iterator!"); 339 Op = Op->getNextOperandForReg(); 340 341 // If this is an operand we don't care about, skip it. 342 while (Op && ((!ReturnUses && Op->isUse()) || 343 (!ReturnDefs && Op->isDef()) || 344 (SkipDebug && Op->isDebug()))) 345 Op = Op->getNextOperandForReg(); 346 347 return *this; 348 } 349 defusechain_iterator operator++(int) { // Postincrement 350 defusechain_iterator tmp = *this; ++*this; return tmp; 351 } 352 353 /// skipInstruction - move forward until reaching a different instruction. 354 /// Return the skipped instruction that is no longer pointed to, or NULL if 355 /// already pointing to end(). 356 MachineInstr *skipInstruction() { 357 if (!Op) return 0; 358 MachineInstr *MI = Op->getParent(); 359 do ++*this; 360 while (Op && Op->getParent() == MI); 361 return MI; 362 } 363 364 MachineOperand &getOperand() const { 365 assert(Op && "Cannot dereference end iterator!"); 366 return *Op; 367 } 368 369 /// getOperandNo - Return the operand # of this MachineOperand in its 370 /// MachineInstr. 371 unsigned getOperandNo() const { 372 assert(Op && "Cannot dereference end iterator!"); 373 return Op - &Op->getParent()->getOperand(0); 374 } 375 376 // Retrieve a reference to the current operand. 377 MachineInstr &operator*() const { 378 assert(Op && "Cannot dereference end iterator!"); 379 return *Op->getParent(); 380 } 381 382 MachineInstr *operator->() const { 383 assert(Op && "Cannot dereference end iterator!"); 384 return Op->getParent(); 385 } 386 }; 387 388}; 389 390} // End llvm namespace 391 392#endif 393