MCInstrDesc.h revision 46367768f75c860d64874067800711120fdbfc22
17f8f3f7f6400291d30531c88a98511f9fc626b4cChad Rosier//===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===// 2d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 3d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// The LLVM Compiler Infrastructure 4d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 5d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// This file is distributed under the University of Illinois Open Source 6d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// License. See LICENSE.TXT for details. 7d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 8d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 9d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 1022fee2dff4c43b551aefa44a96ca74fcade6bfacEvan Cheng// This file defines the MCOperandInfo and MCInstrDesc classes, which 110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach// are used to describe target instructions and their operands. 12d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// 13d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 14d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 15e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#ifndef LLVM_MC_MCINSTRDESC_H 16e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng#define LLVM_MC_MCINSTRDESC_H 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 181f6efa3996dd1929fbc129203ce5009b620e6969Michael J. Spencer#include "llvm/Support/DataTypes.h" 19fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach#include "llvm/MC/MCRegisterInfo.h" 20fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach#include "llvm/MC/MCInst.h" 2199405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes 22d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnernamespace llvm { 23d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 24d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 25d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Operand Flags and Description 26d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 270ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 28e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCOI { 2906801722a43c697eff0acee905de6b50257ce19bJim Grosbach // Operand constraints 30d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandConstraint { 3106801722a43c697eff0acee905de6b50257ce19bJim Grosbach TIED_TO = 0, // Must be allocated the same register as. 3206801722a43c697eff0acee905de6b50257ce19bJim Grosbach EARLY_CLOBBER // Operand is an early clobber register operand 33d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 340ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 35d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// OperandFlags - These are flags set on operands, but should be considered 36e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// private, all access should go through the MCOperandInfo accessors. 37d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// See the accessors for a description of what these are. 38d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum OperandFlags { 39d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner LookupPtrRegClass = 0, 40d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Predicate, 41d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner OptionalDef 42d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 435196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer 445196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer /// Operand Type - Operands are tagged with one of the values of this enum. 455196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer enum OperandType { 465196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_UNKNOWN, 475196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_IMMEDIATE, 485196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_REGISTER, 495196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_MEMORY, 505196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer OPERAND_PCREL 515196c12e9fdec9ef3c63d96cb529c1c1cb732773Benjamin Kramer }; 52d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 53d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 54e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCOperandInfo - This holds information about one operand of a machine 55d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// instruction, indicating the register class for register operands, etc. 56d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner/// 57e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCOperandInfo { 58d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 590ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// RegClass - This specifies the register class enumeration of the operand 60cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// if the operand is a register. If isLookupPtrRegClass is set, then this is 61cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to 62cb778a8634454c70d88955b3732f330a6cbe5b07Chris Lattner /// get a dynamic register class. 6339bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper int16_t RegClass; 640ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 65e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng /// Flags - These are flags from the MCOI::OperandFlags enum. 6639bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t Flags; 6739bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper 6839bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper /// OperandType - Information about the type of the operand. 6939bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint8_t OperandType; 700ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 71d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Lower 16 bits are used to specify which constraints are set. The higher 16 72d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// bits are used to specify the value of constraints (4 bits each). 7339bdc5526f9bb4985c5ea7711e603bb44707ed42Craig Topper uint32_t Constraints; 74d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Currently no other information. 750ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 76d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isLookupPtrRegClass - Set if this operand is a pointer value and it 77d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// requires a callback to look up its register class. 787e0d22cbf7b41e93279f574c9b3c557cdf517dcbJim Grosbach bool isLookupPtrRegClass() const {return Flags&(1 <<MCOI::LookupPtrRegClass);} 790ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 80d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isPredicate - Set if this is one of the operands that made up of 81d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// the predicate operand that controls an isPredicable() instruction. 82e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } 830ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 84d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isOptionalDef - Set if this operand is a optional def. 85d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 86e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } 87d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 88d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 890ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 90d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 91d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner// Machine Instruction Flags and Description 92d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner//===----------------------------------------------------------------------===// 93d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 94e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc flags - These should be considered private to the 95e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// implementation of the MCInstrDesc class. Clients should use the predicate 96e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// methods on MCInstrDesc, not use these directly. These all correspond to 97e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// bitfields in the MCInstrDesc::Flags field. 98e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengnamespace MCID { 99d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner enum { 100d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Variadic = 0, 101d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner HasOptionalDef, 102c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen Pseudo, 103d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Return, 104d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Call, 105d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Barrier, 106d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Terminator, 107d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Branch, 108d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner IndirectBranch, 10973739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling Compare, 110c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng MoveImm, 1110f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng Bitcast, 112f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen Select, 113d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner DelaySlot, 11415511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman FoldableAsLoad, 115dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner MayLoad, 116d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner MayStore, 117c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng Predicable, 118c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng NotDuplicable, 119a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner UnmodeledSideEffects, 120d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner Commutable, 121d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner ConvertibleTo3Addr, 122533297b58da8c74bec65551e1aface9801fc2259Dan Gohman UsesCustomInserter, 12337fefc20d3a1e3934a377567d54a141f67752227Evan Cheng HasPostISelHook, 1248370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling Rematerializable, 125799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng CheapAsAMove, 126799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraSrcRegAllocReq, 127799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng ExtraDefRegAllocReq 128d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner }; 129d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} 130d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 131e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// MCInstrDesc - Describe properties that are true of each instruction in the 132e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// target description file. This captures information about side effects, 133e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// register use and many other things. There is one instance of this struct 134e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// for each target instruction class, and the MachineInstr class points to 135e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng/// this struct directly to describe itself. 136e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass MCInstrDesc { 137d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattnerpublic: 138b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short Opcode; // The opcode number 139d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short NumOperands; // Num of args (may be more if variable_ops) 140b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned short NumDefs; // Num of args that are definitions 141d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned short SchedClass; // enum identifying instr sched class 14216884415db751c75f2133bd04921393c792b1158Owen Anderson unsigned short Size; // Number of bytes in encoding. 143b89be6150a8ea38fdaa2a242f6442e2d73326dabEvan Cheng unsigned Flags; // Flags identifying machine instr class 14499405df044f2c584242e711cc9023ec90356da82Bruno Cardoso Lopes uint64_t TSFlags; // Target Specific Flag values 145fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitUses; // Registers implicitly read by this instr 146fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *ImplicitDefs; // Registers implicitly defined by this instr 147e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands 148d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 14946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns the value of the specific constraint if 150d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// it is set. Returns -1 if it is not set. 151d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner int getOperandConstraint(unsigned OpNum, 152e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng MCOI::OperandConstraint Constraint) const { 153d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner if (OpNum < NumOperands && 154d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner (OpInfo[OpNum].Constraints & (1 << Constraint))) { 155d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned Pos = 16 + Constraint * 4; 156d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 157d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 158d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return -1; 159d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 160d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 16146367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the opcode number for this descriptor. 162d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getOpcode() const { 163d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return Opcode; 164d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1650ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 16646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of declared MachineOperands for this 167d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// MachineInstruction. Note that variadic (isVariadic() returns true) 168d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions may have additional operands at the end of the list, and note 169d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// that the machine instruction may include implicit register def/uses as 170d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// well. 171d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumOperands() const { 172d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumOperands; 173d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1740ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 17546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of MachineOperands that are register 1760ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// definitions. Register definitions always occur at the start of the 177b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// machine operand list. This is the number of "outs" in the .td file, 178b5544940c17720f51a74fea9fba33f26fafe4819Dan Gohman /// and does not include implicit defs. 179d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner unsigned getNumDefs() const { 180d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return NumDefs; 181d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1820ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 18346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return flags of this instruction. 1845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getFlags() const { return Flags; } 1857c2a4a30e0e16762c75adacebd05ec9fcbccf16bEvan Cheng 18646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction can have a variable number of 187d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands. In this case, the variable operands will be after the normal 188d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// operands but before the implicit definitions and uses (if any are 189d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// present). 190d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isVariadic() const { 191e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Variadic); 192d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1930ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 19446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Set if this instruction has an optional definition, e.g. 195d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// ARM instructions which can set condition code if 's' bit is set. 196d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasOptionalDef() const { 197e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::HasOptionalDef); 198d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 1990ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 20046367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a pseudo instruction that doesn't 201c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// correspond to a real machine instruction. 202c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// 203c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen bool isPseudo() const { 204c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen return Flags & (1 << MCID::Pseudo); 205c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen } 206c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 20746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a return. 208d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isReturn() const { 209e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Return); 210d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2110ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if the instruction is a call. 213d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCall() const { 214e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Call); 215d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2160ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 21746367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if the specified instruction stops control flow 218d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// from executing the instruction immediately following it. Examples include 219d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// unconditional branches and return instructions. 220d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBarrier() const { 221e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Barrier); 222d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2230ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 22446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this instruction part of the terminator for 225d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// a basic block. Typically this is things like return and branch 226d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions. 227d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 228d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Various passes use this to insert code into the bottom of a basic block, 229d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// but before control flow occurs. 230d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isTerminator() const { 231e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Terminator); 232d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2330ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 23446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Returns true if this is a conditional, unconditional, or 235d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// indirect branch. Predicates below can be used to discriminate between 236d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to 237d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// get more information. 238d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isBranch() const { 239e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Branch); 240d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 241d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 24246367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is an indirect branch, such as a 243d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// branch through a register. 244d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isIndirectBranch() const { 245e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::IndirectBranch); 246d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 24773739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling 24846367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which may fall 249d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// through to the next instruction or may transfer control flow to some other 250d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more 251d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// information about this branch. 252d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConditionalBranch() const { 253d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & !isBarrier() & !isIndirectBranch(); 254d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2550ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 25646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch which always 257d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transfers control flow to some other block. The 258d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::AnalyzeBranch method can be used to get more information 259d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// about this branch. 260d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isUnconditionalBranch() const { 261d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner return isBranch() & isBarrier() & !isIndirectBranch(); 262d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2630ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 26446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a branch or an instruction which directly 265fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// writes to the program counter. Considered 'may' affect rather than 266fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// 'does' affect as things like predication are not taken into account. 267fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const { 268fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (isBranch() || isCall() || isReturn() || isIndirectBranch()) 269fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 270fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach unsigned PC = RI.getProgramCounter(); 271fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (PC == 0) return false; 272fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return hasDefOfPhysReg(MI, PC, RI); 273fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach } 274fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 27546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction has a predicate operand 276dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// that controls execution. It may be set to 'always', or may be set to other 277dd2fa5195ea2d98b2b4ee18f9894ad674f132a40Jim Grosbach /// values. There are various methods in TargetInstrInfo that can be used to 278d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// control and modify the predicate in this instruction. 279d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isPredicable() const { 280e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Predicable); 281d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 2820ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 28346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a comparison. 28473739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling bool isCompare() const { 285e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Compare); 28673739d0bf19af3944aff6afaea2c4eda61061652Bill Wendling } 2870ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 28846367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a move immediate 2890ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// (including conditional moves) instruction. 290c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng bool isMoveImmediate() const { 291e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MoveImm); 292c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 2930f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng 29446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction is a bitcast instruction. 2950f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng bool isBitcast() const { 296e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Bitcast); 2970f040a258ff6a2372fc232212b5e4189e8e7185dEvan Cheng } 2980ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 29946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this is a select instruction. 300f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen bool isSelect() const { 301f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen return Flags & (1 << MCID::Select); 302f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen } 303f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 30446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction cannot be safely 305d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// duplicated. For example, if the instruction has a unique labels attached 306d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// to it, duplicating it would cause multiple definition errors. 307d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isNotDuplicable() const { 308e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::NotDuplicable); 309d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3100ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 311d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 312d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which must be filled by the code generator. 313d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool hasDelaySlot() const { 314e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::DelaySlot); 315d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3160ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 31715511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman /// canFoldAsLoad - Return true for instructions that can be folded as 31862c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// memory operands in other instructions. The most common use for this 31962c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// is instructions that are simple loads from memory that don't modify 32062c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// the loaded value in any way, but it can also be used for instructions 32162c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// that can be expressed as constant-pool loads, such as V_SETALLONES 32262c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// on x86, to allow them to be folded when it is beneficial. 32362c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// This should only be set on instructions that return a value in their 32462c939d7d5572e57963a5f26fb6fe802e13dc0bfDan Gohman /// only virtual register definition. 32515511cf1660cfd6bb8b8e8fca2db9450f50430eeDan Gohman bool canFoldAsLoad() const { 326e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::FoldableAsLoad); 327d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3280ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 329d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 330d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Side Effect Analysis 331d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 332dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner 33346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly read memory. 334dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// Instructions with this flag set are not necessarily simple load 335dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner /// instructions, they may load a value and modify it, for example. 336dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner bool mayLoad() const { 337e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayLoad); 338dcc8b4f5d3f62ae84aae100638085dedeee91588Chris Lattner } 3390ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 3400ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 34146367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction could possibly modify memory. 342d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Instructions with this flag set are not necessarily simple store 343d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instructions, they may store a modified value based on their operands, or 344d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// may not actually modify anything, for example. 345d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool mayStore() const { 346e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::MayStore); 347d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3480ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 349a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// hasUnmodeledSideEffects - Return true if this instruction has side 350a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// effects that are not modeled by other flags. This does not return true 351a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// for instructions whose effects are captured by: 352d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 353a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 1. Their operand list and implicit definition/use list. Register use/def 354a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// info is explicit for instructions. 355a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 2. Memory accesses. Use mayLoad/mayStore. 356a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. 357d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 358a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// Examples of side effects would be modifying 'invisible' machine state like 359a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// a control register, flushing a cache, modifying a register invisible to 360a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// LLVM, etc. 361d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 362a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner bool hasUnmodeledSideEffects() const { 363e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UnmodeledSideEffects); 364d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3650ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 366d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 367d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner // Flags that indicate whether an instruction can be modified by a method. 368d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner //===--------------------------------------------------------------------===// 3690ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 370d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isCommutable - Return true if this may be a 2- or 3-address 371d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (of the form "X = op Y, Z, ..."), which produces the same 3720ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// result if Y and Z are exchanged. If this flag is set, then the 373d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::commuteInstruction method may be used to hack on the 374d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction. 375d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 376d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Note that this flag may be set on instructions that are only commutable 377d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// sometimes. In these cases, the call to commuteInstruction will fail. 378d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// Also note that some instructions require non-trivial modification to 379d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// commute them. 380d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isCommutable() const { 381e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Commutable); 382d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 3830ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 384d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isConvertibleTo3Addr - Return true if this is a 2-address instruction 385d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// which can be changed into a 3-address instruction if needed. Doing this 386d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// transformation can be profitable in the register allocator, because it 387d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// means that the instruction can use a 2-address form if possible, but 388d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// degrade into a less efficient form if the source and dest register cannot 389d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// be assigned to the same register. For example, this allows the x86 390d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 391d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is the same speed as the shift but has bigger code size. 392d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 393d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this returns true, then the target must implement the 394d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 395d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is allowed to fail if the transformation isn't valid for this specific 396d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// instruction (e.g. shl reg, 4 on x86). 397d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 398d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isConvertibleTo3Addr() const { 399e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ConvertibleTo3Addr); 400d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4010ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 402533297b58da8c74bec65551e1aface9801fc2259Dan Gohman /// usesCustomInsertionHook - Return true if this instruction requires 403d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 404d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// machine basic block. If this is true for the instruction, it basically 4050ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach /// means that it is a pseudo instruction used at SelectionDAG time that is 406d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// expanded out into magic code by the target when MachineInstrs are formed. 407d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// 408d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 409d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// is used to insert this into the MachineBasicBlock. 410533297b58da8c74bec65551e1aface9801fc2259Dan Gohman bool usesCustomInsertionHook() const { 411e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::UsesCustomInserter); 412d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4130ba45d4fb3e11d8085b01008e31477bece20d01dJim Grosbach 41483a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// hasPostISelHook - Return true if this instruction requires *adjustment* 41583a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// after instruction selection by calling a target hook. For example, this 41683a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// can be used to fill in ARM 's' optional operand depending on whether 41783a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick /// the conditional flag register is used. 41883a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick bool hasPostISelHook() const { 41983a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick return Flags & (1 << MCID::HasPostISelHook); 42083a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick } 42183a8031336a1155e6b0c3e9a84164324e08d1c8bAndrew Trick 422d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// isRematerializable - Returns true if this instruction is a candidate for 423d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// remat. This flag is deprecated, please don't use it anymore. If this 424d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// flag is set, the isReallyTriviallyReMaterializable() method is called to 425d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner /// verify the instruction is really rematable. 426d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner bool isRematerializable() const { 427e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::Rematerializable); 428d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner } 4298370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling 4308370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or 4318370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling /// less) than a move instruction. This is useful during certain types of 432758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// optimizations (e.g., remat during two-address conversion or machine licm) 433758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// where we would like to remat or hoist the instruction, but not if it costs 434758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// more than moving the instruction into the appropriate register. Note, we 435758d20f653302ca2fd64f2c13b501156525093d2Evan Cheng /// are not marking copies from and to the same register class with this flag. 4368370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling bool isAsCheapAsAMove() const { 437e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::CheapAsAMove); 4388370d38adee63b3a4d87bfe81be4aacc55fe7cdaBill Wendling } 439799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 440799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands 441799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 442799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::STRD's two source registers must be an 443799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::STM registers have to be in ascending order. 444799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 445799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for sources of instructions with this flag. 446799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraSrcRegAllocReq() const { 447e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraSrcRegAllocReq); 448799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 449799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng 450799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// hasExtraDefRegAllocReq - Returns true if this instruction def operands 451799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// have special register allocation requirements that are not captured by the 452799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// operand register classes. e.g. ARM::LDRD's two def registers must be an 453799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// even / odd pair, ARM::LDM registers have to be in ascending order. 454799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// Post-register allocation passes should not attempt to change allocations 455799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng /// for definitions of instructions with this flag. 456799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng bool hasExtraDefRegAllocReq() const { 457e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng return Flags & (1 << MCID::ExtraDefRegAllocReq); 458799d697bf8d45ec404d0d105fc788ea5cf81c841Evan Cheng } 4595a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4605a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4615a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitUses - Return a list of registers that are potentially 4625a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// read by any instance of this machine instruction. For example, on X86, 4635a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// the "adc" instruction adds two register operands and adds the carry bit in 4645a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// from the flags register. In this case, the instruction is marked as 4655a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// implicitly reading the flags. Likewise, the variable shift instruction on 4665a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// X86 is marked as implicitly reading the 'CL' register, which it always 4675a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// does. 4685a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4695a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit uses. 470fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitUses() const { 4715a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitUses; 4725a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4735a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 47446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of implicit uses this instruction 4755a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitUses() const { 4765a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitUses == 0) return 0; 4775a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 4785a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitUses[i]; ++i) /*empty*/; 4795a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 4805a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4815a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 4825a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// getImplicitDefs - Return a list of registers that are potentially 4835a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// written by any instance of this machine instruction. For example, on X86, 4845a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// many instructions implicitly set the flags register. In this case, they 4855a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// are marked as setting the FLAGS. Likewise, many instructions always 4865a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// deposit their result in a physical register. For example, the X86 divide 4875a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction always deposits the quotient and remainder in the EAX/EDX 4885a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// registers. For that instruction, this will return a list containing the 4895a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// EAX/EDX/EFLAGS registers. 4905a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// 4915a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// This method returns null if the instruction has no implicit defs. 492fac259814923d091942b230e7bd002a8d1130bc3Craig Topper const uint16_t *getImplicitDefs() const { 4935a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return ImplicitDefs; 4945a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 4955a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 49646367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of implicit defs this instruct has. 4975a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getNumImplicitDefs() const { 4985a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (ImplicitDefs == 0) return 0; 4995a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned i = 0; 5005a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; ImplicitDefs[i]; ++i) /*empty*/; 5015a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5025a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5035a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 50446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5055a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// uses the specified physical register. 5065a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng bool hasImplicitUseOfPhysReg(unsigned Reg) const { 507fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpUses = ImplicitUses) 5085a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpUses; ++ImpUses) 5095a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (*ImpUses == Reg) return true; 5105a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5115a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5125a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 51346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction implicitly 5145a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// defines the specified physical register. 515fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool hasImplicitDefOfPhysReg(unsigned Reg, 516fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach const MCRegisterInfo *MRI = 0) const { 517fac259814923d091942b230e7bd002a8d1130bc3Craig Topper if (const uint16_t *ImpDefs = ImplicitDefs) 5185a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (; *ImpDefs; ++ImpDefs) 519fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) 520fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 5215a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return false; 5225a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5235a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 52446367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return true if this instruction defines the specified physical 525fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach /// register, either explicitly or implicitly. 526fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, 527fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach const MCRegisterInfo &RI) const { 528fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach for (int i = 0, e = NumDefs; i != e; ++i) 529fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach if (MI.getOperand(i).isReg() && 530fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 531fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return true; 532fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach return hasImplicitDefOfPhysReg(Reg, &RI); 533fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach } 534fbf3b4a07690751f72302757058ab0298dfb832eJim Grosbach 53546367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the scheduling class for this instruction. The 5365a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// scheduling class is an index into the InstrItineraryData table. This 5375a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// returns zero if there is no known scheduling information for the 5385a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// instruction. 5395a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSchedClass() const { 5405a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return SchedClass; 5415a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5425a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 54346367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Return the number of bytes in the encoding of this instruction, 5445a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// or zero if the encoding size cannot be known from the opcode. 5455a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng unsigned getSize() const { 5465a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return Size; 5475a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5485a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng 54946367768f75c860d64874067800711120fdbfc22Jim Grosbach /// \brief Find the index of the first operand in the 5505a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// operand list that is used to represent the predicate. It returns -1 if 5515a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng /// none is found. 5525a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng int findFirstPredOperandIdx() const { 5535a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (isPredicable()) { 5545a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng for (unsigned i = 0, e = getNumOperands(); i != e; ++i) 5555a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng if (OpInfo[i].isPredicate()) 5565a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return i; 5575a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 5585a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng return -1; 5595a96b3dad2f634c9081c8b2b6c2575441dc5a2bdEvan Cheng } 560d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner}; 561d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 562d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner} // end namespace llvm 563d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner 564d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#endif 565