1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren#include "llvm/ADT/SmallSet.h" 18ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick#include "llvm/CodeGen/DFAPacketizer.h" 196c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 20255f89faee13dc491cb64fbeae3c763e7e2ea4e6Chandler Carruth#include "llvm/MC/MCInstrInfo.h" 21a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 24729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass InstrItineraryData; 25506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass LiveVariables; 26506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MCAsmInfo; 27506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MachineMemOperand; 282312842de0c641107dd04d7e056d02491cc781caEvan Chengclass MachineRegisterInfo; 29962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Chengclass MDNode; 30ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattnerclass MCInst; 313c417554caedde3a333755916701c8380606342aAndrew Trickclass MCSchedModel; 32cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesclass MCSymbolRefExpr; 3343dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 34729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass ScheduleHazardRecognizer; 3543dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 362da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trickclass ScheduleDAG; 37506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterClass; 38506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterInfo; 39f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszakclass BranchProbability; 40cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hinesclass TargetSubtargetInfo; 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 42f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 43f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 44a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 453501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 4634695381d626485a560594f162701088079589dfMisha Brukman/// 4761e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 4834695381d626485a560594f162701088079589dfMisha Brukman/// 49e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Chengclass TargetInstrInfo : public MCInstrInfo { 50001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper TargetInstrInfo(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 51001d3dc976d7cda8a3dd8c7fd4020b0b96033f4eCraig Topper void operator=(const TargetInstrInfo &) LLVM_DELETED_FUNCTION; 52a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 534db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) 544db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng : CallFrameSetupOpcode(CFSetupOpcode), 554db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng CallFrameDestroyOpcode(CFDestroyOpcode) { 564db3cffe94a5285239cc0056f939c6b74a5ca0b6Evan Cheng } 573be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 58075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 5970535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 6015993f83a419950f06d2879d6701530ae6449317Evan Cheng /// getRegClass - Givem a machine instruction descriptor, returns the register 6115993f83a419950f06d2879d6701530ae6449317Evan Cheng /// class constraint for OpNum, or NULL. 62e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, 6315993f83a419950f06d2879d6701530ae6449317Evan Cheng unsigned OpNum, 64397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const TargetRegisterInfo *TRI, 65397fc4874efe9c17e737d4c5c50bd19dc3bf27f5Jakob Stoklund Olesen const MachineFunction &MF) const; 6615993f83a419950f06d2879d6701530ae6449317Evan Cheng 67041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 68d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 69d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 70a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isTriviallyReMaterializable(const MachineInstr *MI, 71dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines AliasAnalysis *AA = nullptr) const { 72518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 73a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman (MI->getDesc().isRematerializable() && 743731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman (isReallyTriviallyReMaterializable(MI, AA) || 75a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman isReallyTriviallyReMaterializableGeneric(MI, AA))); 76d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 77d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 78d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 79041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 80a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 81a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// specify whether the instruction is actually trivially rematerializable, 82a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// taking into consideration its operands. This predicate must return false 83a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if the instruction has any side effects other than producing a value, or 84a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if it requres any address registers that are not always available. 853731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 863731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const { 87a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 88d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 89d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 90a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohmanprivate: 91a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 92a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// for which the M_REMATERIALIZABLE flag is set and the target hook 93a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializable returns false, this function does 94a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// target-independent tests to determine if the instruction is really 95a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// trivially rematerializable. 96a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 97a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA) const; 98a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 99d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 100d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the 101d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// frame setup/destroy instructions if they exist (-1 otherwise). Some 102d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// targets use pseudo instructions in order to abstract away the difference 103d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// between operating with a frame pointer and operating without, through the 104d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// use of these two instructions. 105d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng /// 106d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } 107d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } 108d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng 1097da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 1107da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// extension instruction. That is, it's like a copy where it's legal for the 1117da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 1127da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// true, then it's expected the pre-extension value is available as a subreg 1137da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// of the result register. This also returns the sub-register index in 1147da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// SubIdx. 1157da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1167da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SrcReg, unsigned &DstReg, 1177da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SubIdx) const { 118a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng return false; 119a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng } 120a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng 121af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 122af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 123af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 124af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 125af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 126cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 127cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 128af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 129af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 130b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 131dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 132dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 133dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 134dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 135dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const { 136dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 137dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 138dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 139b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasLoadFromStackSlot - If the specified machine instruction has 140b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// a load from a stack slot, return true along with the FrameIndex 1415e3363255912c559e8251121491a2a9e901f07acDavid Greene /// of the loaded stack slot and the machine mem operand containing 1425e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the reference. If not, return false. Unlike 143b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isLoadFromStackSlot, this returns true for any instructions that 144b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// loads from the stack. This is just a hint, as some cases may be 145b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// missed. 146b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 1475e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 148fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen int &FrameIndex) const; 1496e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 150af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 151af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 152af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 153af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 154af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 155cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 156cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 157af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 158af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1595e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 160dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 161dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 162dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 163dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1645e3363255912c559e8251121491a2a9e901f07acDavid Greene int &FrameIndex) const { 165dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 166dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 167dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 168b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasStoreToStackSlot - If the specified machine instruction has a 169b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// store to a stack slot, return true along with the FrameIndex of 1705e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the loaded stack slot and the machine mem operand containing the 1715e3363255912c559e8251121491a2a9e901f07acDavid Greene /// reference. If not, return false. Unlike isStoreToStackSlot, 1722dbc8bdfe9191c2078daccbeefba9e69a690feb6Evan Cheng /// this returns true for any instructions that stores to the 1735e3363255912c559e8251121491a2a9e901f07acDavid Greene /// stack. This is just a hint, as some cases may be missed. 174b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasStoreToStackSlot(const MachineInstr *MI, 1755e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 176fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen int &FrameIndex) const; 177b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 17871804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford /// isStackSlotCopy - Return true if the specified machine instruction 17971804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford /// is a copy of one stack slot to another and has no other effect. 18071804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford /// Provide the identity of the two frame indices. 18171804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, 18271804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford int &SrcFrameIndex) const { 18371804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford return false; 18471804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford } 18571804149a3a6f6c081b874869b27fafe7d3288ceRichard Sandiford 186bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// Compute the size in bytes and offset within a stack slot of a spilled 187bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// register or subregister. 188bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// 189bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// \param [out] Size in bytes of the spilled value. 190bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// \param [out] Offset in bytes within the stack slot. 191bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// \returns true if both Size and Offset are successfully computed. 192bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// 193bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// Not all subregisters have computable spill slots. For example, 194bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// subregisters registers may not be byte-sized, and a pair of discontiguous 195bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// subregisters has no single offset. 196bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// 197bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// Targets with nontrivial bigendian implementations may need to override 198bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick /// this, particularly to support spilled vector registers. 199bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, 200bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick unsigned &Size, unsigned &Offset, 201bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick const TargetMachine *TM) const; 202bb756ca24401e190e3b704e5d92759c7a79cc6b7Andrew Trick 20322c310d78ce9630af15b0de94c18a409705b7496Tim Murray /// isAsCheapAsAMove - Return true if the instruction is as cheap as a move 20422c310d78ce9630af15b0de94c18a409705b7496Tim Murray /// instruction. 20522c310d78ce9630af15b0de94c18a409705b7496Tim Murray /// 20622c310d78ce9630af15b0de94c18a409705b7496Tim Murray /// Targets for different archs need to override this, and different 20722c310d78ce9630af15b0de94c18a409705b7496Tim Murray /// micro-architectures can also be finely tuned inside. 20822c310d78ce9630af15b0de94c18a409705b7496Tim Murray virtual bool isAsCheapAsAMove(const MachineInstr *MI) const { 20922c310d78ce9630af15b0de94c18a409705b7496Tim Murray return MI->isAsCheapAsAMove(); 21022c310d78ce9630af15b0de94c18a409705b7496Tim Murray } 21122c310d78ce9630af15b0de94c18a409705b7496Tim Murray 212ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 213ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 2149edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// The register in Orig->getOperand(0).getReg() will be substituted by 2159edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 2169edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// SubIdx. 217ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 218ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 219378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 220d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 221fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 222ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 22330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 22430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// MachineFunction::CloneMachineInstr(), but the target may update operands 22530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// that are required to be unique. 226d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// 227d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// The instruction must be duplicable as indicated by isNotDuplicable(). 22830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen virtual MachineInstr *duplicate(MachineInstr *Orig, 229fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen MachineFunction &MF) const; 23030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 23115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 23215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2332c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 2346c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 23515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 23615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 23715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 23815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 2396c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 24015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 2416c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 2426c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 243f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 244dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 24515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 24615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 247f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commuteInstruction - If a target has any instructions that are 248f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commutable but require converting to different instructions or making 249f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// non-trivial changes to commute them, this method can overloaded to do 250f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// that. The default implementation simply swaps the commutable operands. 251f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// If NewMI is false, MI is modified in place and returned; otherwise, a 252f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// new machine instruction is created and returned. Do not call this 253f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// method for a non-commutable instruction, but there may be some cases 254f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// where this method fails and returns null. 25558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 256fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen bool NewMI = false) const; 257d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 258261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// findCommutedOpIndices - If specified MI is commutable, return the two 259f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// operand indices that would swap value. Return false if the instruction 260261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// is not in a form which this routine understands. 261261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 262fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen unsigned &SrcOpIdx2) const; 263f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 264506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// produceSameValue - Return true if two machine instructions would produce 265506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// identical values. By default, this is only true when the two instructions 2669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// are deemed identical except for defs. If this function is called when the 2679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 2689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// aggressive checks. 269506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 2709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 271dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const MachineRegisterInfo *MRI = nullptr) const; 27212749db1503c2beed58ddcfba5f1b323611fb2ceEvan Cheng 273b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 274b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 275b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 276b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 277b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 27872dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 27972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 28072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 281b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 28285de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// 3. If this block ends with a conditional branch and it falls through to a 28385de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// successor block, it sets TBB to be the branch destination block and a 28485de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// list of operands that evaluate the condition. These operands can be 28585de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// passed to other TargetInstrInfo methods to create new branches. 286a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 4. If this block ends with a conditional branch followed by an 287a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// unconditional branch, it returns the 'true' destination in TBB, the 288a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 'false' destination in FBB, and a list of operands that evaluate the 289a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// condition. These operands can be passed to other TargetInstrInfo 290a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// methods to create new branches. 291b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 292b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 293b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 294b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 295dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// If AllowModify is true, then this routine is allowed to modify the basic 296dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// block (e.g. delete instructions after the unconditional branch). 297dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// 298b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 299b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 300dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 301dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify = false) const { 302b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 303905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 304a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 305b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 3068c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 307b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 308b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 30950bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement TargetInstrInfo::RemoveBranch!"); 310b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 311a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 312a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// InsertBranch - Insert branch code into the end of the specified 313a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// MachineBasicBlock. The operands to this method are the same as those 314a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// returned by AnalyzeBranch. This is only invoked in cases where 315a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// AnalyzeBranch returns success. It returns the number of instructions 316a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// inserted. 317c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// 318c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// It is also invoked by tail merging to add unconditional branches in 319c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// cases where AnalyzeBranch doesn't apply because there was no original 320c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// branch to analyze. At least this much must be implemented, else tail 321c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// merging needs to be disabled. 322b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3233bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3243bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3253bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 32650bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!"); 327b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 32886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 32986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 33086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// after it, replacing it with an unconditional branch to NewDest. This is 33186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// used by the tail merging pass. 33286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 333fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen MachineBasicBlock *NewDest) const; 3344d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng 335cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// getUnconditionalBranch - Get an instruction that performs an unconditional 336cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// branch to the given symbol. 337cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual void 338cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines getUnconditionalBranch(MCInst &MI, 339cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines const MCSymbolRefExpr *BranchTarget) const { 340cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines llvm_unreachable("Target didn't implement " 341cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines "TargetInstrInfo::getUnconditionalBranch!"); 342cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 343cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 344cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines /// getTrap - Get a machine trap instruction 345cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines virtual void getTrap(MCInst &MI) const { 346cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines llvm_unreachable("Target didn't implement TargetInstrInfo::getTrap!"); 347cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines } 348cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines 3494d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 3504d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// block at the specified instruction (i.e. instruction would be the start 3514d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// of a new basic block). 3524d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 3534d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng MachineBasicBlock::iterator MBBI) const { 3544d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng return true; 3554d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng } 35613151432edace19ee867a93b5c14573df4f75d24Evan Cheng 3578239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// isProfitableToIfCvt - Return true if it's profitable to predicate 3588239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// instructions with accumulated instruction latency of "NumCycles" 359b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson /// of the specified basic block, where the probability of the instructions 360e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// being executed is given by Probability, and Confidence is a measure 361e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// of our confidence that it will be properly predicted. 36213151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual 363575e90e955064f60ac66230dce6c27653973c149Kay Tiong Khoo bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 3648239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 365f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 36613151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 36713151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 3686e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 36913151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 37013151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// checks for the case where two basic blocks from true and false path 37113151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// of a if-then-else (diamond) are predicated on mutally exclusive 372b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson /// predicates, where the probability of the true path being taken is given 373e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// by Probability, and Confidence is a measure of our confidence that it 374e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// will be properly predicted. 37513151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 3768239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng isProfitableToIfCvt(MachineBasicBlock &TMBB, 3778239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumTCycles, unsigned ExtraTCycles, 3788239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 3798239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumFCycles, unsigned ExtraFCycles, 380f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 38113151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 38213151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 38313151432edace19ee867a93b5c14573df4f75d24Evan Cheng 38413151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToDupForIfCvt - Return true if it's profitable for 3858239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// if-converter to duplicate instructions of specified accumulated 3868239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// instruction latencies in the specified MBB to enable if-conversion. 3878239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// The probability of the instructions being executed is given by 3888239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// Probability, and Confidence is a measure of our confidence that it 3898239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// will be properly predicted. 39013151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 391575e90e955064f60ac66230dce6c27653973c149Kay Tiong Khoo isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 392f81b7f6069b27c0a515070dcb392f6828437412fJakub Staszak const BranchProbability &Probability) const { 39313151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 39413151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 3956e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 3968787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// isProfitableToUnpredicate - Return true if it's profitable to unpredicate 3978787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually 3988787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// exclusive predicates. 3998787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// e.g. 4008787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// subeq r0, r1, #1 4018787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// addne r0, r1, #1 4028787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// => 4038787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// sub r0, r1, #1 4048787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// addne r0, r1, #1 4058787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// 4068787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng /// This may be profitable is conditional instructions are always executed. 4078787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 4088787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng MachineBasicBlock &FMBB) const { 4098787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng return false; 4108787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng } 4118787c5f24e175a36f645784d533384f9f7cd86fcEvan Cheng 41233242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// canInsertSelect - Return true if it is possible to insert a select 41333242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// instruction that chooses between TrueReg and FalseReg based on the 41433242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// condition code in Cond. 41533242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// 41633242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// When successful, also return the latency in cycles from TrueReg, 41778dd7a580c7ad7234395d2c0207c98e751378cd7Jakob Stoklund Olesen /// FalseReg, and Cond to the destination register. In most cases, a select 41878dd7a580c7ad7234395d2c0207c98e751378cd7Jakob Stoklund Olesen /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 41978dd7a580c7ad7234395d2c0207c98e751378cd7Jakob Stoklund Olesen /// 42078dd7a580c7ad7234395d2c0207c98e751378cd7Jakob Stoklund Olesen /// Some x86 implementations have 2-cycle cmov instructions. 42133242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// 42233242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param MBB Block where select instruction would be inserted. 42333242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param Cond Condition returned by AnalyzeBranch. 42433242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param TrueReg Virtual register to select when Cond is true. 42533242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param FalseReg Virtual register to select when Cond is false. 42633242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param CondCycles Latency from Cond+Branch to select output. 42733242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param TrueCycles Latency from TrueReg to select output. 42833242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param FalseCycles Latency from FalseReg to select output. 42933242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen virtual bool canInsertSelect(const MachineBasicBlock &MBB, 43033242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen const SmallVectorImpl<MachineOperand> &Cond, 43133242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen unsigned TrueReg, unsigned FalseReg, 43233242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen int &CondCycles, 43333242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen int &TrueCycles, int &FalseCycles) const { 43433242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen return false; 43533242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen } 43633242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen 43733242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// insertSelect - Insert a select instruction into MBB before I that will 43833242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 43933242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// Cond is false. 44033242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// 44133242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// This function can only be called after canInsertSelect() returned true. 44233242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// The condition in Cond comes from AnalyzeBranch, and it can be assumed 44333242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// that the same flags or registers required by Cond are available at the 44433242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// insertion point. 44533242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// 44633242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param MBB Block where select instruction should be inserted. 44733242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param I Insertion point. 44833242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param DL Source location for debugging. 44933242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param DstReg Virtual register to be defined by select instruction. 45033242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param Cond Condition as computed by AnalyzeBranch. 45133242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param TrueReg Virtual register to copy when Cond is true. 45233242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen /// @param FalseReg Virtual register to copy when Cons is false. 45333242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen virtual void insertSelect(MachineBasicBlock &MBB, 45433242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen MachineBasicBlock::iterator I, DebugLoc DL, 45533242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen unsigned DstReg, 45633242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen const SmallVectorImpl<MachineOperand> &Cond, 45733242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen unsigned TrueReg, unsigned FalseReg) const { 45833242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); 45933242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen } 46033242fd3ed5586091e73254b58dd1825e9d53c60Jakob Stoklund Olesen 461f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// analyzeSelect - Analyze the given select instruction, returning true if 462f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// it cannot be understood. It is assumed that MI->isSelect() is true. 463f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 464f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// When successful, return the controlling condition and the operands that 465f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// determine the true and false result values. 466f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 467f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// Result = SELECT Cond, TrueOp, FalseOp 468f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 469f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// Some targets can optimize select instructions, for example by predicating 470f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// the instruction defining one of the operands. Such targets should set 471f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// Optimizable. 472f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 473f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param MI Select instruction to analyze. 474f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param Cond Condition controlling the select. 475f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param TrueOp Operand number of the value selected when Cond is true. 476f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param FalseOp Operand number of the value selected when Cond is false. 477f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param Optimizable Returned as true if MI is optimizable. 478f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @returns False on success. 479f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen virtual bool analyzeSelect(const MachineInstr *MI, 480f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen SmallVectorImpl<MachineOperand> &Cond, 481f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen unsigned &TrueOp, unsigned &FalseOp, 482f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen bool &Optimizable) const { 4831358841e91695bd0e498c02d064c480dc53c566aBenjamin Kramer assert(MI && MI->getDesc().isSelect() && "MI must be a select instruction"); 484f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen return true; 485f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen } 486f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 487f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// optimizeSelect - Given a select instruction that was understood by 488f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by 489f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// merging it with one of its operands. Returns NULL on failure. 490f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 491f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// When successful, returns the new select instruction. The client is 492f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// responsible for deleting MI. 493f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 494f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// If both sides of the select can be optimized, PreferFalse is used to pick 495f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// a side. 496f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// 497f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param MI Optimizable select instruction. 498f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. 499f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen /// @returns Optimized instruction or NULL. 500f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen virtual MachineInstr *optimizeSelect(MachineInstr *MI, 501f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen bool PreferFalse = false) const { 502f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen // This function must be implemented if Optimizable is ever set. 503f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); 504f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen } 505f2c64ef519b38a4328809b27b4a3a8e0c26e9709Jakob Stoklund Olesen 5063651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen /// copyPhysReg - Emit instructions to copy a pair of physical registers. 507b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// 508b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// This function should support copies within any legal register class as 509b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// well as any cross-class copies created during instruction selection. 510b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// 511b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// The source and destination registers may overlap, which may require a 512b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// careful implementation when multiple copy instructions are required for 513b4e090dffc4bed40cee22b94560aa8dd3b4af013Jakob Stoklund Olesen /// large registers. See for example the ARM target. 5143651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 5153651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen MachineBasicBlock::iterator MI, DebugLoc DL, 5163651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 517744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen bool KillSrc) const { 51850bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!"); 519744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen } 5203651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen 52195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 52295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 52395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 52495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 52595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 526f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 527f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 528f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 529746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 530746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 53150bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement " 53250bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "TargetInstrInfo::storeRegToStackSlot!"); 533f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 534f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 53595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 53695a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 53795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 53895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 539f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 540f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 541f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 542746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 543746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 54450bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper llvm_unreachable("Target didn't implement " 54550bee42b54cd9aec5f49566307df2b0cf23afcf6Craig Topper "TargetInstrInfo::loadRegFromStackSlot!"); 546f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 547d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 548c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// expandPostRAPseudo - This function is called for all pseudo instructions 549c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// that remain after register allocation. Many pseudo instructions are 550c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// created to help register allocation. This is the place to convert them 551c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// into real instructions. The target can edit MI in place, or it can insert 552c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// new instructions and erase MI. The function should return true if 553c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen /// anything was changed. 55492fb79b7a611ab4c1043f04e8acd08f963d073adJakob Stoklund Olesen virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 555c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen return false; 556c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen } 557c291e2f5780c3a8470113a2a58c1fa680cd54b20Jakob Stoklund Olesen 55843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 55943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 56043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 561e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// operand folded, otherwise NULL is returned. 562e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// The new instruction is inserted before MI, and the client is responsible 563e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// for removing the old instruction. 564e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 565c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 566c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 56743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 56843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 56943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 57043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 571e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 572c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 573c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 574c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 575c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 576c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 577c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 578c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 579c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 5805fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 5818e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 582c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 583dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 584c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 585c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 586c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 587c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 588c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 589c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 590c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 5915a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher const SmallVectorImpl<unsigned> &Ops, 592c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 593dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 59443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 59543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 596c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 5972b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 59843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 59943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 6008e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 601fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const; 60243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 60343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 60443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 60543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 60643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 60743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 608c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const{ 60943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 61043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 61143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 61243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 61343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 61443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 61543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 61643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 61743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 61843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 61943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 6200115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// possible. If LoadRegIndex is non-null, it is filled in with the operand 6210115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// index of the operand which will hold the register holding the loaded 6220115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// value. 62343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 6240115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman bool UnfoldLoad, bool UnfoldStore, 625dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned *LoadRegIndex = nullptr) const { 62643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 62743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 62896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 62996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 63096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to determine if two loads are loading from the same base address. It 63196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// should only return true if the base pointers are the same and the 63296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// only differences between the two addresses are the offset. It also returns 63396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// the offsets by reference. 63496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 6355a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher int64_t &Offset1, int64_t &Offset2) const { 63696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 63796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 63896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 63996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 6407a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 64196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// be scheduled togther. On some targets if two loads are loading from 64296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// addresses in the same cache line, it's better if they are scheduled 64396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// together. This function takes two integers that represent the load offsets 64496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// from the common base address. It returns true if it decides it's desirable 64596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to schedule the two loads together. "NumLoads" is the number of loads that 64696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// have already been scheduled after Load1. 64796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 64896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t Offset1, int64_t Offset2, 64996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng unsigned NumLoads) const { 65096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 65196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 6526e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 6539b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick /// \brief Get the base register and byte offset of a load/store instr. 6549b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt, 6559b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick unsigned &BaseReg, unsigned &Offset, 6569b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick const TargetRegisterInfo *TRI) const { 6579b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick return false; 6589b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick } 6599b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick 660d1d0d37a198df718b0fd1f838b7d9593b1636299Andrew Trick virtual bool enableClusterLoads() const { return false; } 661d1d0d37a198df718b0fd1f838b7d9593b1636299Andrew Trick 662a7d2d564d918a9cb9105d3b2b4176b45af36a20eAndrew Trick virtual bool shouldClusterLoads(MachineInstr *FirstLdSt, 663a7d2d564d918a9cb9105d3b2b4176b45af36a20eAndrew Trick MachineInstr *SecondLdSt, 664a7d2d564d918a9cb9105d3b2b4176b45af36a20eAndrew Trick unsigned NumLoads) const { 6659b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick return false; 6669b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick } 6679b5caaa9c452f262a52dd5ac7ebbc722da5a63deAndrew Trick 6686996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick /// \brief Can this target fuse the given instructions if they are scheduled 6696996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick /// adjacent. 6706996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick virtual bool shouldScheduleAdjacent(MachineInstr* First, 6716996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick MachineInstr *Second) const { 6726996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick return false; 6736996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick } 6746996fd0b543cf8bd4a0d4e09e80a168f0ae052c5Andrew Trick 6755f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 6765f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 6775f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 67844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 67944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 6805f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 681905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 6826e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 68365e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 68465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 6856e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick virtual void insertNoop(MachineBasicBlock &MBB, 686b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner MachineBasicBlock::iterator MI) const; 6876e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 6886e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 689ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 690ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner virtual void getNoopForMachoTarget(MCInst &NopInst) const { 691ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner // Default to just using 'nop' string. 692ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner } 6936e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 6946e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 695bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 6964f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 697f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 6984f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 6994f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 7004f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 701bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 702bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 703fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 704bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 7050402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 70602c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 707f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 708f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 709fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const SmallVectorImpl<MachineOperand> &Pred) const; 7104f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 711bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 7124f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 713f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 71444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 71544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 7164f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 7174f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 7180402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 719ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 720ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 721ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 722ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 723ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 724ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 725ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 726ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 727e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// isPredicable - Return true if the specified instruction can be predicated. 728e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// By default, this returns true for every instruction with a 729e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// PredicateOperand. 730e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng virtual bool isPredicable(MachineInstr *MI) const { 731e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng return MI->getDesc().isPredicable(); 732e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng } 733e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng 7344350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 7354350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 7364350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 73723066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 73823066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 73923066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 74086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// isSchedulingBoundary - Test if the given instruction should be 74186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// considered a scheduling boundary. This primarily includes labels and 74286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// terminators. 74386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 74486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 745fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const MachineFunction &MF) const; 74686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 747d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// Measure the specified inline asm to determine an approximation of its 748d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// length. 749d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner virtual unsigned getInlineAsmLength(const char *Str, 75033adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo &MAI) const; 751729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng 752c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 753c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// use for this target when scheduling the machine instructions before 754c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// register allocation. 755729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng virtual ScheduleHazardRecognizer* 756cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 757fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const ScheduleDAG *DAG) const; 7582da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 7590a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer 7600a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick /// to use for this target when scheduling the machine instructions before 7610a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick /// register allocation. 7620a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick virtual ScheduleHazardRecognizer* 7630a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick CreateTargetMIHazardRecognizer(const InstrItineraryData*, 764fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const ScheduleDAG *DAG) const; 7650a39d4e4c86540d7c89f6dbe511b70466e132715Andrew Trick 7662da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 7672da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// recognizer to use for this target when scheduling the machine instructions 7682da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// after register allocation. 7692da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick virtual ScheduleHazardRecognizer* 7702da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 771fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const ScheduleDAG *DAG) const; 772fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen 773fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen /// Provide a global flag for disabling the PreRA hazard recognizer that 774fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen /// targets may choose to honor. 775fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen bool usePreRAHazardRecognizer() const; 776e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 777de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// analyzeCompare - For a comparison instruction, return the source registers 778de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// in SrcReg and SrcReg2 if having two register operands, and the value it 779de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// compares against in CmpValue. Return true if the comparison instruction 780de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// can be analyzed. 781de7266c611b37ec050efb53b73166081a98cea13Manman Ren virtual bool analyzeCompare(const MachineInstr *MI, 782de7266c611b37ec050efb53b73166081a98cea13Manman Ren unsigned &SrcReg, unsigned &SrcReg2, 783de7266c611b37ec050efb53b73166081a98cea13Manman Ren int &Mask, int &Value) const { 784e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 785e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 786e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 787de7266c611b37ec050efb53b73166081a98cea13Manman Ren /// optimizeCompareInstr - See if the comparison instruction can be converted 788a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling /// into something more efficient. E.g., on ARM most instructions can set the 789eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng /// flags register, obviating the need for a separate CMP. 790de7266c611b37ec050efb53b73166081a98cea13Manman Ren virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, 791de7266c611b37ec050efb53b73166081a98cea13Manman Ren unsigned SrcReg, unsigned SrcReg2, 792de7266c611b37ec050efb53b73166081a98cea13Manman Ren int Mask, int Value, 793eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng const MachineRegisterInfo *MRI) const { 794e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 795e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 7966e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 797d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren /// optimizeLoadInstr - Try to remove the load by folding it to a register 798d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren /// operand at the use. We fold the load instructions if and only if the 799127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren /// def and use are in the same BB. We only look at one load and see 800127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 801127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren /// defined by the load we are trying to fold. DefMI returns the machine 802127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren /// instruction that defines FoldAsLoadDefReg, and the function returns 803127eea87d666ccc9fe7025f41148c33af0f8c84bManman Ren /// the machine instruction generated due to folding. 804d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI, 805d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren const MachineRegisterInfo *MRI, 806d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren unsigned &FoldAsLoadDefReg, 807d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren MachineInstr *&DefMI) const { 808dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 809d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren } 810d7d003c2b7b7f657eed364e4ac06f4ab32fc8c2dManman Ren 811c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// FoldImmediate - 'Reg' is known to be defined by a move immediate 812c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// instruction, try to fold the immediate into the use instruction. 813a36119beeceb125fe2097da2729dca886973b108Hal Finkel /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, 814a36119beeceb125fe2097da2729dca886973b108Hal Finkel /// then the caller may assume that DefMI has been erased from its parent 815a36119beeceb125fe2097da2729dca886973b108Hal Finkel /// block. The caller may assume that it will not be erased by this 816a36119beeceb125fe2097da2729dca886973b108Hal Finkel /// function otherwise. 817c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 818c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg, MachineRegisterInfo *MRI) const { 819c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 820c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 8215f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 8225f54ce347368105260be2cec497b6a4199dc5789Evan Cheng /// getNumMicroOps - Return the number of u-operations the given machine 823218ee74a011c0d350099c452810da0bd57a15047Andrew Trick /// instruction will be decoded to on the target cpu. The itinerary's 824218ee74a011c0d350099c452810da0bd57a15047Andrew Trick /// IssueWidth is the number of microops that can be dispatched each 825218ee74a011c0d350099c452810da0bd57a15047Andrew Trick /// cycle. An instruction with zero microops takes no dispatch resources. 8268239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 827fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const MachineInstr *MI) const; 828a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 829c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// isZeroCost - Return true for pseudo instructions that don't consume any 830c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// machine resources in their current form. These are common cases that the 831c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// scheduler should consider free, rather than conservatively handling them 832c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// as instructions with no itinerary. 833c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick bool isZeroCost(unsigned Opcode) const { 834c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return Opcode <= TargetOpcode::COPY; 835c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick } 836c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 837b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick virtual int getOperandLatency(const InstrItineraryData *ItinData, 838b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick SDNode *DefNode, unsigned DefIdx, 839fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen SDNode *UseNode, unsigned UseIdx) const; 840b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick 841a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// getOperandLatency - Compute and return the use operand latency of a given 8428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// pair of def and use. 843a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// In most cases, the static scheduling itinerary was enough to determine the 844a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// operand latency. But it may not be possible for instructions with variable 845a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// number of defs / uses. 846b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick /// 847b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick /// This is a raw interface to the itinerary that may be directly overriden by 848b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick /// a target. Use computeOperandLatency to get the best estimate of latency. 8498239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getOperandLatency(const InstrItineraryData *ItinData, 850b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *DefMI, unsigned DefIdx, 851b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *UseMI, 852fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen unsigned UseIdx) const; 853b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick 854b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick /// computeOperandLatency - Compute and return the latency of the given data 855397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick /// dependent def and use when the operand indices are already known. 856397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick unsigned computeOperandLatency(const InstrItineraryData *ItinData, 857397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick const MachineInstr *DefMI, unsigned DefIdx, 858b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick const MachineInstr *UseMI, unsigned UseIdx) 859b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick const; 860397f4e3583b36b23047fec06b1648f0771cd6fe3Andrew Trick 8618239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// getInstrLatency - Compute the instruction latency of a given instruction. 8628239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// If the instruction has higher cost when predicated, it's returned via 8638239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// PredCost. 864b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, 865b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *MI, 866dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned *PredCost = nullptr) const; 8678239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 868d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer virtual unsigned getPredicationCost(const MachineInstr *MI) const; 869d42730dc712026cbfb1322a979e0ac72cd31a19eArnold Schwaighofer 8708239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getInstrLatency(const InstrItineraryData *ItinData, 871fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen SDNode *Node) const; 8722312842de0c641107dd04d7e056d02491cc781caEvan Cheng 873b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick /// Return the default expected latency for a def based on it's opcode. 8743c417554caedde3a333755916701c8380606342aAndrew Trick unsigned defaultDefLatency(const MCSchedModel *SchedModel, 875b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick const MachineInstr *DefMI) const; 876b7e0289fb320c8440ba5eed121a8b932dbd806a2Andrew Trick 87734301ceca8913f3126339f332d3dc6f2d7ac0d78Andrew Trick int computeDefOperandLatency(const InstrItineraryData *ItinData, 878b86a0cdb674549d8493043331cecd9cbf53b80daAndrew Trick const MachineInstr *DefMI) const; 87934301ceca8913f3126339f332d3dc6f2d7ac0d78Andrew Trick 880e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick /// isHighLatencyDef - Return true if this opcode has high latency to its 881e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick /// result. 882ece96f5713e14b705d415eb95fe57c5fff841626Andrew Trick virtual bool isHighLatencyDef(int opc) const { return false; } 883e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick 8842312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 8852312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// and an use in the current loop, return true if the target considered 8862312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// it 'high'. This is used by optimization passes such as machine LICM to 8872312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// determine whether it makes sense to hoist an instruction out even in 8882312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// high register pressure situation. 8892312842de0c641107dd04d7e056d02491cc781caEvan Cheng virtual 8902312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 8912312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 8922312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 8932312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 8942312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 8952312842de0c641107dd04d7e056d02491cc781caEvan Cheng } 896c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 897c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 898c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng /// if the target considered it 'low'. 899c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng virtual 900c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng bool hasLowDefLatency(const InstrItineraryData *ItinData, 901fa2d98632c77e5d9c305e97e5fa25d06f579127bJakob Stoklund Olesen const MachineInstr *DefMI, unsigned DefIdx) const; 902d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng 9033be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick /// verifyInstruction - Perform target specific instruction verification. 9043be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick virtual 9053be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { 9063be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick return true; 9073be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick } 9083be654f8082dcbdff011a6716a7c90486e28fc9eAndrew Trick 90998e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// getExecutionDomain - Return the current execution domain and bit mask of 91098e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// possible domains for instruction. 91198e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 91298e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// Some micro-architectures have multiple execution domains, and multiple 91398e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// opcodes that perform the same operation in different domains. For 91498e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// example, the x86 architecture provides the por, orps, and orpd 91598e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// instructions that all do the same thing. There is a latency penalty if a 91698e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// register is written in one domain and read in another. 91798e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 91898e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// This function returns a pair (domain, mask) containing the execution 91998e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// domain of MI, and a bit mask of possible domains. The setExecutionDomain 92098e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// function can be used to change the opcode to one of the domains in the 92198e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// bit mask. Instructions whose execution domain can't be changed should 92298e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// return a 0 mask. 92398e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 92498e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// The execution domain numbers don't have any special meaning except domain 92598e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 0 is used for instructions that are not associated with any interesting 92698e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// execution domain. 92798e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 92898e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen virtual std::pair<uint16_t, uint16_t> 92998e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen getExecutionDomain(const MachineInstr *MI) const { 93098e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen return std::make_pair(0, 0); 93198e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen } 93298e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen 93398e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// setExecutionDomain - Change the opcode of MI to execute in Domain. 93498e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 93598e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// The bit (1 << Domain) must be set in the mask returned from 93698e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// getExecutionDomain(MI). 93798e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen /// 93898e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {} 93998e933f9ad3cc2ede3a0a337144a504265d614cdJakob Stoklund Olesen 940c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen 941c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// getPartialRegUpdateClearance - Returns the preferred minimum clearance 942c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// before an instruction with an unwanted partial register update. 943c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 944c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// Some instructions only write part of a register, and implicitly need to 945c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// read the other parts of the register. This may cause unwanted stalls 946c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// preventing otherwise unrelated instructions from executing in parallel in 947c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// an out-of-order CPU. 948c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 949c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// For example, the x86 instruction cvtsi2ss writes its result to bits 950c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so 951c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// the instruction needs to wait for the old value of the register to become 952c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// available: 953c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 954c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// addps %xmm1, %xmm0 955c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// movaps %xmm0, (%rax) 956c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// cvtsi2ss %rbx, %xmm0 957c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 958c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// In the code above, the cvtsi2ss instruction needs to wait for the addps 959c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// instruction before it can issue, even though the high bits of %xmm0 960c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// probably aren't needed. 961c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 962c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// This hook returns the preferred clearance before MI, measured in 963c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// instructions. Other defs of MI's operand OpNum are avoided in the last N 964c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// instructions before MI. It should only return a positive value for 965c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// unwanted dependencies. If the old bits of the defined register have 966c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// useful values, or if MI is determined to otherwise read the dependency, 967c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// the hook should return 0. 968c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 969c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// The unwanted dependency may be handled by: 970c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 971c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1. Allocating the same register for an MI def and use. That makes the 972c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// unwanted dependency identical to a required dependency. 973c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 974c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 2. Allocating a register for the def that has no defs in the previous N 975c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// instructions. 976c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 977c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 3. Calling breakPartialRegDependency() with the same arguments. This 978c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// allows the target to insert a dependency breaking instruction. 979c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 980c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen virtual unsigned 981c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 982c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen const TargetRegisterInfo *TRI) const { 983c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen // The default implementation returns 0 for no partial register dependency. 984c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen return 0; 985c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen } 986c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen 987a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// \brief Return the minimum clearance before an instruction that reads an 988a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// unused register. 989a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// 990a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// For example, AVX instructions may copy part of an register operand into 991a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// the unused high bits of the destination register. 992a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// 993a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14 994a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// 995a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a 996a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// false dependence on any previous write to %xmm0. 997a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// 998a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// This hook works similarly to getPartialRegUpdateClearance, except that it 999a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// does not take an operand index. Instead sets \p OpNum to the index of the 1000a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick /// unused register. 1001a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 1002a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick const TargetRegisterInfo *TRI) const { 1003a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick // The default implementation returns 0 for no undef register dependency. 1004a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick return 0; 1005a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick } 1006a6a9ac5aa1092067e6e1546226d8bdd6a4bfcf99Andrew Trick 1007c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// breakPartialRegDependency - Insert a dependency-breaking instruction 1008c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// before MI to eliminate an unwanted dependency on OpNum. 1009c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1010c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// If it wasn't possible to avoid a def in the last N instructions before MI 1011c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// (see getPartialRegUpdateClearance), this hook will be called to break the 1012c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// unwanted dependency. 1013c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1014c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// On x86, an xorps instruction can be used as a dependency breaker: 1015c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1016c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// addps %xmm1, %xmm0 1017c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// movaps %xmm0, (%rax) 1018c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// xorps %xmm0, %xmm0 1019c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// cvtsi2ss %rbx, %xmm0 1020c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1021c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// An <imp-kill> operand should be added to MI if an instruction was 1022c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// inserted. This ties the instructions together in the post-ra scheduler. 1023c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen /// 1024c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen virtual void 1025c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 1026c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen const TargetRegisterInfo *TRI) const {} 1027c2ecf3efbf375fc82bb1cea6afd7448498f9ae75Jakob Stoklund Olesen 1028ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick /// Create machine specific model for scheduling. 1029ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick virtual DFAPacketizer* 1030ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick CreateTargetScheduleState(const TargetMachine*, const ScheduleDAG*) const { 1031dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 1032ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick } 1033ee498d3254b86bceb4f441741e9f442990647ce6Andrew Trick 1034d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Chengprivate: 1035d5b03f252c0db6b49a242abab63d7c5a260fceaeEvan Cheng int CallFrameSetupOpcode, CallFrameDestroyOpcode; 1036a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 1037a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1038d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 1039d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 1040a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 1041