TargetInstrInfo.h revision 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#include "llvm/Target/TargetInstrDesc.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 22ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 236c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 24d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Andersonclass CalleeSavedInfo; 2543dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 2643dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 27a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 28f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 29f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 30a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 313501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 3234695381d626485a560594f162701088079589dfMisha Brukman/// 3361e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 3434695381d626485a560594f162701088079589dfMisha Brukman/// 35075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 36749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 37749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner unsigned NumOpcodes; // Number of entries in the desc array 3834695381d626485a560594f162701088079589dfMisha Brukman 39075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 40075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 42749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 43075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 4470535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 454ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 464ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 474ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 481ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 494406604047423576e36657c7ede266ca42e79642Dan Gohman DBG_LABEL = 2, 504406604047423576e36657c7ede266ca42e79642Dan Gohman EH_LABEL = 3, 514406604047423576e36657c7ede266ca42e79642Dan Gohman GC_LABEL = 4, 524406604047423576e36657c7ede266ca42e79642Dan Gohman DECLARE = 5, 534406604047423576e36657c7ede266ca42e79642Dan Gohman EXTRACT_SUBREG = 6, 544406604047423576e36657c7ede266ca42e79642Dan Gohman INSERT_SUBREG = 7, 554406604047423576e36657c7ede266ca42e79642Dan Gohman IMPLICIT_DEF = 8, 564406604047423576e36657c7ede266ca42e79642Dan Gohman SUBREG_TO_REG = 9 576634e26aa11b0e2eabde8b3b463bb943364f8d9dChristopher Lamb }; 5834695381d626485a560594f162701088079589dfMisha Brukman 59bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 6034695381d626485a560594f162701088079589dfMisha Brukman 61e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 62e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 63e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 64749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &get(unsigned Opcode) const { 65749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner assert(Opcode < NumOpcodes && "Invalid opcode!"); 66749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return Descriptors[Opcode]; 67a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 684683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 69041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 70d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 71d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 729f8fea3531f8f8d04d1e183ff570be37d41d13f5Bill Wendling bool isTriviallyReMaterializable(const MachineInstr *MI) const { 73749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return MI->getDesc().isRematerializable() && 74041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling isReallyTriviallyReMaterializable(MI); 75d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 76d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 77d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 78041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 79041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 80041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// instruction itself is actually trivially rematerializable, considering 81041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// its operands. This is used for targets that have instructions that are 82041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// only trivially rematerializable for specific uses. This predicate must 83041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// return false if the instruction has any side effects other than 84041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// producing a value, or if it requres any address registers that are not 85041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// always available. 869f8fea3531f8f8d04d1e183ff570be37d41d13f5Bill Wendling virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 87d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return true; 88d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 89d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 90d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 9104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// Return true if the instruction is a register to register move and return 9204ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng /// the source and dest operands and their sub-register indices by reference. 935e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 9404ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcReg, unsigned& DstReg, 9504ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 965e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 975e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 98af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 99af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 100af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 101af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 102af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 103af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 104cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 105cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 106af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 107af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 108af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 109af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 110af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 111af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 112af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 113af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 114cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 115cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 116af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 117af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1185e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 119ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 120ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 121ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 122ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 123ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 124ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const = 0; 125ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 126a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// isInvariantLoad - Return true if the specified instruction (which is 127a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// marked mayLoad) is loading from a location whose value is invariant across 128a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// the function. For example, loading a value from the constant pool or from 129a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// from the argument area of a function if it does not change. This should 130a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// only return true of *all* loads the instruction does are invariant (if it 131a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner /// does multiple loads). 132cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual bool isInvariantLoad(const MachineInstr *MI) const { 133a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner return false; 134a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner } 135a22edc82cab86be4cb8876da1e6e78f82bb47a3eChris Lattner 13615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 13715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1382c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 1396c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 14015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 14115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 14215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 14315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 1446c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 14515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 1466c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 1476c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 148f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 14915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 15015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 15115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 152d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 153d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 154d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 155d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 156d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 157d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 158d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 159d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 160d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 161d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 16258dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// If NewMI is true, then a new machine instruction must be created. 16358dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng /// 16458dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 16558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const = 0; 166d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 167f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// CommuteChangesDestination - Return true if commuting the specified 168f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// instruction will also changes the destination operand. Also return the 169f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// current operand index of the would be new destination register by 170f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// reference. This can happen when the commutable instruction is also a 171f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng /// two-address instruction. 172f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng virtual bool CommuteChangesDestination(MachineInstr *MI, 173f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng unsigned &OpIdx) const = 0; 174f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 175b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 176b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 177b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 178b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 179b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 18072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 18172dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 18272dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 183b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 1846c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 1856c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// an successor block, it sets TBB to be the branch destination block and a 1866c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// list of operands that evaluate the condition. These 1876c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 1886c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 1896c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 4. If this block ends with an conditional branch and an unconditional 1906c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// block, it returns the 'true' destination in TBB, the 'false' destination 1916c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// in FBB, and a list of operands that evaluate the condition. These 1926c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 1936c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 194b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 195b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 196b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 197b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 198b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 199b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 20044eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson SmallVectorImpl<MachineOperand> &Cond) const { 201b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 202905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 203b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 204b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2058c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 206b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 207b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 208b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 209b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 210b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 211b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 212b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 213b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 21433644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 21533644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 216b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// null, Cond is empty) needs to be inserted. It returns the number of 217b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// instructions inserted. 218b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 219d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 22044eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond) const { 22124321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 222b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 223b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 224b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 225a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// copyRegToReg - Emit instructions to copy between a pair of registers. It 226a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// returns false if the target does not how to copy between the specified 227a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// registers. 228940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 229d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 230d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 231d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 232d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 233d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 234c93457053cfecb24105ee3800c8e53921b950d8fCedric Venet return false; 235d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 236d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 23795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 23895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 23995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 24095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 24195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 242f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 243f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 244f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 245f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 246f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 247f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 248f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 24995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToAddr - Store the specified register of the given register class 25095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// to the specified address. The store instruction is to be added to the 25195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// given machine basic block before the specified machine instruction. If 25295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// isKill is true, the register operand is the last use and must be marked 25395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// kill. 254f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 255f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 256f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 257f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 258f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!"); 259f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 260f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 26195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 26295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 26395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 26495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 265f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 266f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 267f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 268f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 269f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 270f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 271f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 27295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromAddr - Load the specified register of the given register class 27395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified address. The load instruction is to be added to 27495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// the given machine basic block before the specified machine instruction. 275f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 276f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 277f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 278f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 279f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!"); 280f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 281f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 282d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 283d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 284d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of store instructions via 285d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// storeRegToStackSlot(). Returns false otherwise. 286d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 287d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 288d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 289d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 290d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 291d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 292d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 293d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 294d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of load instructions via loadRegToStackSlot(). 295d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// Returns false otherwise. 296d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 297d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 298d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson const std::vector<CalleeSavedInfo> &CSI) const { 299d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 300d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 301d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 30243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 30343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 30443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 30543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// operand folded, otherwise NULL is returned. The client is responsible for 30643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// removing the old instruction and adding the new one in the instruction 30743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stream. 308c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 309c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 310c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 311c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 31243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 31343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 31443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 31543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 316c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 317c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 318c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 319c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 320c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 321c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 322c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 323c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 324c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 325c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 3265fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 3278e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 328c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 329c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return 0; 330c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 331c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 332c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 333c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 334c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 335c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 336c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 337c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 338c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 33943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 34043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 34143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 342c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 3432b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 34443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 34543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 3468e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 3478e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const { 34843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 34943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 35043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 35143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 35243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 35343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 35443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 35543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 35643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const{ 35743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 35843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 35943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 36043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 36143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 36243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 36343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 36443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 36543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 36643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 36743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 36843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible. 36943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 37043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool UnfoldLoad, bool UnfoldStore) const { 37143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 37243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 37343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 374c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 375c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 376c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 377c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 3788e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman virtual bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 379c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 380c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 381c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 3825f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 3835f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 3845f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 38544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 38644eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 3875f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 388905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 3890271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 39065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 39165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 39265e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 39365e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 39465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 39565e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 39665e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 39721d03f2de0087d60dbf575d95924404a97852879Evan Cheng 398bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 3994f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 400f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 4014f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4024f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4034f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 404bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 405bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 406318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 407bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 4080402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 40902c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 410f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 411f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 41244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const = 0; 4134f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 414bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 4154f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 416f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 41744eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 41844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 4194f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4204f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4210402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 422ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 423ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 424ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 425ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 426ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 427ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 428ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 429ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 43023066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng /// IgnoreRegisterClassBarriers - Returns true if pre-register allocation 43123066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng /// live interval splitting pass should ignore barriers of the specified 43223066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng /// register class. 43323066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng virtual bool IgnoreRegisterClassBarriers(const TargetRegisterClass *RC) const{ 43423066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 43523066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 43623066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 43721d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 43821d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// values. 43921d03f2de0087d60dbf575d95924404a97852879Evan Cheng virtual const TargetRegisterClass *getPointerRegClass() const { 44021d03f2de0087d60dbf575d95924404a97852879Evan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 44121d03f2de0087d60dbf575d95924404a97852879Evan Cheng abort(); 442fb062ece96092e70a835c0d462613b07228d60a3Jeff Cohen return 0; // Must return a value in order to compile with VS 2005 44321d03f2de0087d60dbf575d95924404a97852879Evan Cheng } 44452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 44552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Returns the size of the specified Instruction. 44652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 44752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 44852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 44952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 45052e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 45152e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 45252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetFunctionSizeInBytes - Returns the size of the specified MachineFunction. 45352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 45452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 455a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 456a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 457641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 458641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 459641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 460641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 461641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 462641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 463749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 464641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 465641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 46658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 46758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const; 468f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng virtual bool CommuteChangesDestination(MachineInstr *MI, 469f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng unsigned &OpIdx) const; 470641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 47144eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const; 472ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 473ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 474ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng unsigned DestReg, 475ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng const MachineInstr *Orig) const; 47652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 477641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 478641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 479d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 480d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 481a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 482