TargetInstrInfo.h revision 15993f83a419950f06d2879d6701530ae6449317
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#include "llvm/Target/TargetInstrDesc.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 22729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass InstrItineraryData; 23506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass LiveVariables; 24506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MCAsmInfo; 25506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MachineMemOperand; 262312842de0c641107dd04d7e056d02491cc781caEvan Chengclass MachineRegisterInfo; 27962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Chengclass MDNode; 28ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattnerclass MCInst; 2943dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 30729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass ScheduleHazardRecognizer; 3143dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 322da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trickclass ScheduleDAG; 33506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterClass; 34506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterInfo; 35a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 36f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 37f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 38a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 393501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 4034695381d626485a560594f162701088079589dfMisha Brukman/// 4161e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 4234695381d626485a560594f162701088079589dfMisha Brukman/// 43075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 44749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 45749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner unsigned NumOpcodes; // Number of entries in the desc array 4634695381d626485a560594f162701088079589dfMisha Brukman 47075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 48075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 49a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 50749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 51075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 5270535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 53bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 5434695381d626485a560594f162701088079589dfMisha Brukman 55e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 56e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 57e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 58749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &get(unsigned Opcode) const { 59749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner assert(Opcode < NumOpcodes && "Invalid opcode!"); 60749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return Descriptors[Opcode]; 61a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 624683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 6315993f83a419950f06d2879d6701530ae6449317Evan Cheng /// getRegClass - Givem a machine instruction descriptor, returns the register 6415993f83a419950f06d2879d6701530ae6449317Evan Cheng /// class constraint for OpNum, or NULL. 6515993f83a419950f06d2879d6701530ae6449317Evan Cheng const TargetRegisterClass *getRegClass(const TargetInstrDesc &TID, 6615993f83a419950f06d2879d6701530ae6449317Evan Cheng unsigned OpNum, 6715993f83a419950f06d2879d6701530ae6449317Evan Cheng const TargetRegisterInfo *TRI) const; 6815993f83a419950f06d2879d6701530ae6449317Evan Cheng 69041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 70d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 71d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 72a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isTriviallyReMaterializable(const MachineInstr *MI, 73a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA = 0) const { 74518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 75a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman (MI->getDesc().isRematerializable() && 763731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman (isReallyTriviallyReMaterializable(MI, AA) || 77a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman isReallyTriviallyReMaterializableGeneric(MI, AA))); 78d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 79d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 80d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 81041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 82a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 83a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// specify whether the instruction is actually trivially rematerializable, 84a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// taking into consideration its operands. This predicate must return false 85a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if the instruction has any side effects other than producing a value, or 86a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if it requres any address registers that are not always available. 873731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 883731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const { 89a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 90d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 91d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 92a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohmanprivate: 93a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 94a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// for which the M_REMATERIALIZABLE flag is set and the target hook 95a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializable returns false, this function does 96a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// target-independent tests to determine if the instruction is really 97a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// trivially rematerializable. 98a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 99a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA) const; 100a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 101d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 1027da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 1037da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// extension instruction. That is, it's like a copy where it's legal for the 1047da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 1057da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// true, then it's expected the pre-extension value is available as a subreg 1067da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// of the result register. This also returns the sub-register index in 1077da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// SubIdx. 1087da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1097da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SrcReg, unsigned &DstReg, 1107da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SubIdx) const { 111a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng return false; 112a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng } 113a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng 114af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 115af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 116af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 117af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 118af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 119cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 120cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 121af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 122af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 123b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 124dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 125dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 126dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 127dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 128dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const { 129dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 130dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 131dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 132b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasLoadFromStackSlot - If the specified machine instruction has 133b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// a load from a stack slot, return true along with the FrameIndex 1345e3363255912c559e8251121491a2a9e901f07acDavid Greene /// of the loaded stack slot and the machine mem operand containing 1355e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the reference. If not, return false. Unlike 136b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isLoadFromStackSlot, this returns true for any instructions that 137b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// loads from the stack. This is just a hint, as some cases may be 138b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// missed. 139b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 1405e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 141b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const { 142b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene return 0; 143b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene } 1446e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 145af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 146af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 147af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 148af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 149af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 150cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 151cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 152af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 153af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1545e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 155dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 156dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 157dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 158dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1595e3363255912c559e8251121491a2a9e901f07acDavid Greene int &FrameIndex) const { 160dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 161dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 162dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 163b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasStoreToStackSlot - If the specified machine instruction has a 164b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// store to a stack slot, return true along with the FrameIndex of 1655e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the loaded stack slot and the machine mem operand containing the 1665e3363255912c559e8251121491a2a9e901f07acDavid Greene /// reference. If not, return false. Unlike isStoreToStackSlot, 1672dbc8bdfe9191c2078daccbeefba9e69a690feb6Evan Cheng /// this returns true for any instructions that stores to the 1685e3363255912c559e8251121491a2a9e901f07acDavid Greene /// stack. This is just a hint, as some cases may be missed. 169b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasStoreToStackSlot(const MachineInstr *MI, 1705e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 171b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const { 172b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene return 0; 173b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene } 174b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 175ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 176ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 1779edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// The register in Orig->getOperand(0).getReg() will be substituted by 1789edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 1799edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// SubIdx. 180ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 181ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 182378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 183d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 1849edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const = 0; 185ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 18668fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 18768fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng /// two-addrss instruction inserted by two-address pass. 18868fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 18968fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng MachineInstr *UseMI, 19068fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng const TargetRegisterInfo &TRI) const { 19168fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng // Do nothing. 19268fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng } 19368fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng 19430ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 19530ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// MachineFunction::CloneMachineInstr(), but the target may update operands 19630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// that are required to be unique. 197d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// 198d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// The instruction must be duplicable as indicated by isNotDuplicable(). 19930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen virtual MachineInstr *duplicate(MachineInstr *Orig, 20030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const = 0; 20130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 20215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 20315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2042c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 2056c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 20615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 20715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 20815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 20915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 2106c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 21115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 2126c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 2136c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 214f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 21515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 21615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 21715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 218f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commuteInstruction - If a target has any instructions that are 219f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commutable but require converting to different instructions or making 220f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// non-trivial changes to commute them, this method can overloaded to do 221f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// that. The default implementation simply swaps the commutable operands. 222f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// If NewMI is false, MI is modified in place and returned; otherwise, a 223f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// new machine instruction is created and returned. Do not call this 224f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// method for a non-commutable instruction, but there may be some cases 225f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// where this method fails and returns null. 22658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 22758dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const = 0; 228d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 229261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// findCommutedOpIndices - If specified MI is commutable, return the two 230f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// operand indices that would swap value. Return false if the instruction 231261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// is not in a form which this routine understands. 232261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 233261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const = 0; 234f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 235506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// produceSameValue - Return true if two machine instructions would produce 236506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// identical values. By default, this is only true when the two instructions 2379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// are deemed identical except for defs. If this function is called when the 2389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for 2399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng /// aggressive checks. 240506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 2419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 2429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI = 0) const = 0; 24312749db1503c2beed58ddcfba5f1b323611fb2ceEvan Cheng 244b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 245b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 246b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 247b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 248b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 24972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 25072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 25172dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 252b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 25385de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// 3. If this block ends with a conditional branch and it falls through to a 25485de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// successor block, it sets TBB to be the branch destination block and a 25585de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// list of operands that evaluate the condition. These operands can be 25685de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// passed to other TargetInstrInfo methods to create new branches. 257a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 4. If this block ends with a conditional branch followed by an 258a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// unconditional branch, it returns the 'true' destination in TBB, the 259a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 'false' destination in FBB, and a list of operands that evaluate the 260a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// condition. These operands can be passed to other TargetInstrInfo 261a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// methods to create new branches. 262b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 263b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 264b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 265b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 266dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// If AllowModify is true, then this routine is allowed to modify the basic 267dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// block (e.g. delete instructions after the unconditional branch). 268dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// 269b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 270b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 271dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 272dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify = false) const { 273b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 274905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 275a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 276b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2778c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 278b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 279b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 2806e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 281b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 282b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 283a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 284a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// InsertBranch - Insert branch code into the end of the specified 285a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// MachineBasicBlock. The operands to this method are the same as those 286a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// returned by AnalyzeBranch. This is only invoked in cases where 287a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// AnalyzeBranch returns success. It returns the number of instructions 288a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// inserted. 289c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// 290c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// It is also invoked by tail merging to add unconditional branches in 291c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// cases where AnalyzeBranch doesn't apply because there was no original 292c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// branch to analyze. At least this much must be implemented, else tail 293c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// merging needs to be disabled. 294b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 2953bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 2963bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 2973bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 2986e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 299b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 300b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 30186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 30286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 30386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// after it, replacing it with an unconditional branch to NewDest. This is 30486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// used by the tail merging pass. 30586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 30686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const = 0; 3074d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng 3084d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 3094d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// block at the specified instruction (i.e. instruction would be the start 3104d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// of a new basic block). 3114d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 3124d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng MachineBasicBlock::iterator MBBI) const { 3134d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng return true; 3144d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng } 31513151432edace19ee867a93b5c14573df4f75d24Evan Cheng 3168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// isProfitableToIfCvt - Return true if it's profitable to predicate 3178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// instructions with accumulated instruction latency of "NumCycles" 318b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson /// of the specified basic block, where the probability of the instructions 319e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// being executed is given by Probability, and Confidence is a measure 320e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// of our confidence that it will be properly predicted. 32113151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual 3228239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 3238239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned ExtraPredCycles, 324e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 32513151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 32613151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 3276e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 32813151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 32913151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// checks for the case where two basic blocks from true and false path 33013151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// of a if-then-else (diamond) are predicated on mutally exclusive 331b20b85168c0e9819e6545f08281e9b83c82108f0Owen Anderson /// predicates, where the probability of the true path being taken is given 332e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// by Probability, and Confidence is a measure of our confidence that it 333e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson /// will be properly predicted. 33413151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 3358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng isProfitableToIfCvt(MachineBasicBlock &TMBB, 3368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumTCycles, unsigned ExtraTCycles, 3378239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng MachineBasicBlock &FMBB, 3388239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned NumFCycles, unsigned ExtraFCycles, 339e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 34013151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 34113151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 34213151432edace19ee867a93b5c14573df4f75d24Evan Cheng 34313151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToDupForIfCvt - Return true if it's profitable for 3448239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// if-converter to duplicate instructions of specified accumulated 3458239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// instruction latencies in the specified MBB to enable if-conversion. 3468239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// The probability of the instructions being executed is given by 3478239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// Probability, and Confidence is a measure of our confidence that it 3488239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// will be properly predicted. 34913151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 3508239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 351e3cc84a43d6a4bb6c50f58f3dd8e60e28787509eOwen Anderson float Probability, float Confidence) const { 35213151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 35313151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 3546e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 3553651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen /// copyPhysReg - Emit instructions to copy a pair of physical registers. 3563651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 3573651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen MachineBasicBlock::iterator MI, DebugLoc DL, 3583651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 359744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen bool KillSrc) const { 360744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen assert(0 && "Target didn't implement TargetInstrInfo::copyPhysReg!"); 361744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37Jakob Stoklund Olesen } 3623651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen 36395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 36495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 36595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 36695a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 36795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 368f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 369f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 370f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 371746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 372746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 3735a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 374f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 375f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 37695a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 37795a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 37895a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 37995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 380f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 381f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 382f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 383746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 384746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 3855a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 386f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 387d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 388962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// emitFrameIndexDebugValue - Emit a target-dependent form of 389962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// DBG_VALUE encoding the address of a frame index. Addresses would 390962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// normally be lowered the same way as other addresses on the target, 391962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// e.g. in load instructions. For targets that do not support this 392962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// the debug info is simply lost. 393efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// If you add this for a target you should handle this DBG_VALUE in the 394efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// target-specific AsmPrinter code as well; you will probably get invalid 395efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// assembly output if you don't. 396962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 3978601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 398962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng uint64_t Offset, 399962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng const MDNode *MDPtr, 400962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng DebugLoc dl) const { 401962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return 0; 402962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng } 403962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng 40443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 40543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 40643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 407e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// operand folded, otherwise NULL is returned. 408e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// The new instruction is inserted before MI, and the client is responsible 409e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen /// for removing the old instruction. 410e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 411c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 412c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 41343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 41443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 41543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 41643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 417e05442d50806e2850eae1571958816028093df85Jakob Stoklund Olesen MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI, 418c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 419c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 420c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 421c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 422c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 423c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 424c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 425c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 4265fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 4278e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 428c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 429c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return 0; 430c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 431c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 432c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 433c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 434c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 435c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 436c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 4375a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher const SmallVectorImpl<unsigned> &Ops, 438c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 43943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 44043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 44143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 442c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 4432b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 44443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 44543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 4468e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 4471f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const =0; 44843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 44943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 45043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 45143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 45243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 45343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 454c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const{ 45543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 45643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 45743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 45843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 45943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 46043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 46143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 46243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 46343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 46443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 46543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 4660115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// possible. If LoadRegIndex is non-null, it is filled in with the operand 4670115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// index of the operand which will hold the register holding the loaded 4680115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// value. 46943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 4700115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman bool UnfoldLoad, bool UnfoldStore, 4710115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman unsigned *LoadRegIndex = 0) const { 47243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 47343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 47496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 47596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 47696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to determine if two loads are loading from the same base address. It 47796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// should only return true if the base pointers are the same and the 47896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// only differences between the two addresses are the offset. It also returns 47996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// the offsets by reference. 48096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 4815a3eb8f0e1141825634be38165e40871ce60b3d5Eric Christopher int64_t &Offset1, int64_t &Offset2) const { 48296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 48396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 48496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 48596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 4867a2bdde0a0eebcd2125055e0eacaca040f0b766cChris Lattner /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 48796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// be scheduled togther. On some targets if two loads are loading from 48896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// addresses in the same cache line, it's better if they are scheduled 48996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// together. This function takes two integers that represent the load offsets 49096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// from the common base address. It returns true if it decides it's desirable 49196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to schedule the two loads together. "NumLoads" is the number of loads that 49296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// have already been scheduled after Load1. 49396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 49496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t Offset1, int64_t Offset2, 49596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng unsigned NumLoads) const { 49696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 49796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 4986e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 4995f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 5005f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 5015f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 50244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 50344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 5045f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 505905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 5066e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 50765e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 50865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 5096e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick virtual void insertNoop(MachineBasicBlock &MBB, 510b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner MachineBasicBlock::iterator MI) const; 5116e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 5126e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 513ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 514ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner virtual void getNoopForMachoTarget(MCInst &NopInst) const { 515ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner // Default to just using 'nop' string. 516ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner } 5176e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 5186e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 519bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 5204f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 521f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 5224f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 5234f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 5244f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 525bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 526bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 527318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 528bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 5290402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 53002c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 531f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 532f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 53344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const = 0; 5344f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 535bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 5364f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 537f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 53844eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 53944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 5404f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 5414f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 5420402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 543ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 544ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 545ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 546ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 547ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 548ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 549ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 550ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 551e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// isPredicable - Return true if the specified instruction can be predicated. 552e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// By default, this returns true for every instruction with a 553e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// PredicateOperand. 554e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng virtual bool isPredicable(MachineInstr *MI) const { 555e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng return MI->getDesc().isPredicable(); 556e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng } 557e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng 5584350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 5594350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 5604350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 56123066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 56223066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 56323066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 56486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// isSchedulingBoundary - Test if the given instruction should be 56586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// considered a scheduling boundary. This primarily includes labels and 56686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// terminators. 56786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 56886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 56986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const = 0; 57086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 571d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// Measure the specified inline asm to determine an approximation of its 572d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// length. 573d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner virtual unsigned getInlineAsmLength(const char *Str, 57433adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo &MAI) const; 575729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng 576c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to 577c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// use for this target when scheduling the machine instructions before 578c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// register allocation. 579729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng virtual ScheduleHazardRecognizer* 5802da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetHazardRecognizer(const TargetMachine *TM, 5812da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const = 0; 5822da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 5832da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard 5842da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// recognizer to use for this target when scheduling the machine instructions 5852da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick /// after register allocation. 5862da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick virtual ScheduleHazardRecognizer* 5872da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 5882da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG *DAG) const = 0; 589e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 590c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// AnalyzeCompare - For a comparison instruction, return the source register 591c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// in SrcReg and the value it compares against in CmpValue. Return true if 592c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling /// the comparison instruction can be analyzed. 593c98af3370f899a0d1570b1dff01a2e36632f884fBill Wendling virtual bool AnalyzeCompare(const MachineInstr *MI, 59404ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif unsigned &SrcReg, int &Mask, int &Value) const { 595e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 596e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 597e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling 598a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling /// OptimizeCompareInstr - See if the comparison instruction can be converted 599a65568676d0d9d53dd4aae8f1c58271bb4cfff10Bill Wendling /// into something more efficient. E.g., on ARM most instructions can set the 600eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng /// flags register, obviating the need for a separate CMP. 60104ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, 60204ac81d5db058a3a9492e1aff1f398a8643bfda9Gabor Greif unsigned SrcReg, int Mask, int Value, 603eb96a2f6c03c0ec97c56a3493ac38024afacc774Evan Cheng const MachineRegisterInfo *MRI) const { 604e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling return false; 605e4ddbdfd3cf031034020671d03626f0373fbd5caBill Wendling } 6066e8f4c404825b79f9b9176483653f1aa927dfbdeAndrew Trick 607c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// FoldImmediate - 'Reg' is known to be defined by a move immediate 608c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng /// instruction, try to fold the immediate into the use instruction. 609c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, 610c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng unsigned Reg, MachineRegisterInfo *MRI) const { 611c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng return false; 612c4af4638dfdab0dc3b6257276cfad2ee45053060Evan Cheng } 6135f54ce347368105260be2cec497b6a4199dc5789Evan Cheng 6145f54ce347368105260be2cec497b6a4199dc5789Evan Cheng /// getNumMicroOps - Return the number of u-operations the given machine 6155f54ce347368105260be2cec497b6a4199dc5789Evan Cheng /// instruction will be decoded to on the target cpu. 6168239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, 6178239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI) const; 618a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng 619c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// isZeroCost - Return true for pseudo instructions that don't consume any 620c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// machine resources in their current form. These are common cases that the 621c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// scheduler should consider free, rather than conservatively handling them 622c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick /// as instructions with no itinerary. 623c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick bool isZeroCost(unsigned Opcode) const { 624c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick return Opcode <= TargetOpcode::COPY; 625c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick } 626c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 627a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// getOperandLatency - Compute and return the use operand latency of a given 6288239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// pair of def and use. 629a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// In most cases, the static scheduling itinerary was enough to determine the 630a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// operand latency. But it may not be possible for instructions with variable 631a0792de66c8364d47b0a688c7f408efb7b10f31bEvan Cheng /// number of defs / uses. 6328239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getOperandLatency(const InstrItineraryData *ItinData, 6338239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *DefMI, unsigned DefIdx, 6348239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *UseMI, unsigned UseIdx) const; 6358239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 6368239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getOperandLatency(const InstrItineraryData *ItinData, 6378239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *DefNode, unsigned DefIdx, 6388239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *UseNode, unsigned UseIdx) const; 6398239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 6408239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// getInstrLatency - Compute the instruction latency of a given instruction. 6418239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// If the instruction has higher cost when predicated, it's returned via 6428239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng /// PredCost. 6438239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getInstrLatency(const InstrItineraryData *ItinData, 6448239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng const MachineInstr *MI, 6458239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng unsigned *PredCost = 0) const; 6468239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng 6478239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng virtual int getInstrLatency(const InstrItineraryData *ItinData, 6488239daf7c83a65a189c352cce3191cdc3bbfe151Evan Cheng SDNode *Node) const; 6492312842de0c641107dd04d7e056d02491cc781caEvan Cheng 650e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick /// isHighLatencyDef - Return true if this opcode has high latency to its 651e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick /// result. 652ece96f5713e14b705d415eb95fe57c5fff841626Andrew Trick virtual bool isHighLatencyDef(int opc) const { return false; } 653e0ef509aeb47b396cf1bdc170ca4f468f799719fAndrew Trick 6542312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 6552312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// and an use in the current loop, return true if the target considered 6562312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// it 'high'. This is used by optimization passes such as machine LICM to 6572312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// determine whether it makes sense to hoist an instruction out even in 6582312842de0c641107dd04d7e056d02491cc781caEvan Cheng /// high register pressure situation. 6592312842de0c641107dd04d7e056d02491cc781caEvan Cheng virtual 6602312842de0c641107dd04d7e056d02491cc781caEvan Cheng bool hasHighOperandLatency(const InstrItineraryData *ItinData, 6612312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineRegisterInfo *MRI, 6622312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *DefMI, unsigned DefIdx, 6632312842de0c641107dd04d7e056d02491cc781caEvan Cheng const MachineInstr *UseMI, unsigned UseIdx) const { 6642312842de0c641107dd04d7e056d02491cc781caEvan Cheng return false; 6652312842de0c641107dd04d7e056d02491cc781caEvan Cheng } 666c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng 667c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 668c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng /// if the target considered it 'low'. 669c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng virtual 670c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng bool hasLowDefLatency(const InstrItineraryData *ItinData, 671c8141dfc7f983cb04e65d8acd6bcbdc8e4b8a0aeEvan Cheng const MachineInstr *DefMI, unsigned DefIdx) const; 672a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 673a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 674641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 675641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 676641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 677641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 678641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 679641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 680749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 681641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 682641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 68386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 68486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const; 68558dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 68658dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const; 687261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 688261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const; 6891f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen virtual bool canFoldMemoryOperand(const MachineInstr *MI, 6901f32340d95ac480bfc74bcfd00fd5cffbe078652Jakob Stoklund Olesen const SmallVectorImpl<unsigned> &Ops) const; 691641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 69244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const; 693ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 694ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 695378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubReg, 696d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 6979edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 69830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen virtual MachineInstr *duplicate(MachineInstr *Orig, 69930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const; 700506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 7019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineInstr *MI1, 7029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineRegisterInfo *MRI) const; 70386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 70486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 70586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const; 706729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng 707c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick bool usePreRAHazardRecognizer() const; 708c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4Andrew Trick 709729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng virtual ScheduleHazardRecognizer * 7102da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const; 7112da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick 7122da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick virtual ScheduleHazardRecognizer * 7132da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 7142da8bc8a5f7705ac131184cd247f48500da0d74eAndrew Trick const ScheduleDAG*) const; 715641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 716641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 717d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 718d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 719a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 720