TargetInstrInfo.h revision 1b1b737d7dc7b3330331cf65514719d719f88a43
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 56fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// This file was developed by the LLVM research group and is distributed under 66fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// the University of Illinois Open Source License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 18551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 192cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 20be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 21a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 22d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 245684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 25f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 265684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Value; 27588668d4681bf928e09534c373b1bcf86757f899Vikram S. Adveclass Type; 285684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Instruction; 292cc214c06cbb94f95928636981c9805d6300cff1Chris Lattnerclass Constant; 30e7506a366e8bd56c97d10beb68e4db953aebaecaChris Lattnerclass Function; 31c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 32ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 33a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 34f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 35f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 36f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 38ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 39c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 40a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 423501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 4300876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4400876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 453501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 46a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 47f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 0; 48f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CALL_FLAG = 1 << 1; 49f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_RET_FLAG = 1 << 2; 50f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BARRIER_FLAG = 1 << 3; 51f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 52f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_LOAD_FLAG = 1 << 5; 53f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_STORE_FLAG = 1 << 6; 5415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_2_ADDR_FLAG - 3-addr instructions which really work like 2-addr ones. 56f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_2_ADDR_FLAG = 1 << 7; 5715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// M_CONVERTIBLE_TO_3_ADDR - This is a M_2_ADDR_FLAG instruction which can be 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 6015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 6115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 62f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 8; 6315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 6415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 6515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 66f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_COMMUTABLE = 1 << 9; 67a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 68075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 69075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 70075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 71075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 72f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_TERMINATOR_FLAG = 1 << 10; 73075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 7409321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 7509321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// insertion support when the DAG scheduler is inserting it into a machine basic 7609321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// block. 77f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 11; 7809321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner 798d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 808d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// operands in addition to the minimum number operands specified. 818d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Chengconst unsigned M_VARIABLE_OPS = 1 << 12; 828d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 831b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner// M_PREDICATED - Set if this instruction has a predicate that controls its 841b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner// execution. 851b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattnerconst unsigned M_PREDICATED = 1 << 13; 861b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 871b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 8821d03f2de0087d60dbf575d95924404a97852879Evan Cheng// Machine operand flags 8921d03f2de0087d60dbf575d95924404a97852879Evan Cheng// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 9021d03f2de0087d60dbf575d95924404a97852879Evan Cheng// requires a callback to look up its register class. 9121d03f2de0087d60dbf575d95924404a97852879Evan Chengconst unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 9221d03f2de0087d60dbf575d95924404a97852879Evan Cheng 93ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 94ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 95ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 96ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 97ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 9860f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// RegClass - This specifies the register class enumeration of the operand 9960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// if the operand is a register. If not, this contains 0. 10060f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short RegClass; 10160f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short Flags; 102e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// Lower 16 bits are used to specify which constraints are set. The higher 16 103e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// bits are used to specify the value of constraints (4 bits each). 104e2ba8975883874633a1035c245af3b948b940b25Evan Cheng unsigned int Constraints; 105ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 106ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 107ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 108ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 1091fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 1101fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 1114683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 1128d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng unsigned numOperands; // Num of args (may be more if variable_ops). 11375e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 11475e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 11575e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 116f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 117f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 118ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 119a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 120a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 121a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1223501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 12334695381d626485a560594f162701088079589dfMisha Brukman/// 1243501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 12534695381d626485a560594f162701088079589dfMisha Brukman/// 126075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 127075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 128bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 129075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 13034695381d626485a560594f162701088079589dfMisha Brukman 131075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 132075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 133a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 134bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 135075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 13670535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1374ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 1384ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 1394ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 1404ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner INLINEASM = 1 1414ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner }; 14234695381d626485a560594f162701088079589dfMisha Brukman 143bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 14434695381d626485a560594f162701088079589dfMisha Brukman 145e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 146e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 147e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 1482441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 1492441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 1502441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 151a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1524683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 1532441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 1542441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 1554683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 15634695381d626485a560594f162701088079589dfMisha Brukman 1572441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 1582441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 159a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 160450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1612441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 1622441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 163a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 164d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1652441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 1662441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 167d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 168d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 1692441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 1702441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 171d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 172d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 173450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 174a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 175a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 176a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 17734695381d626485a560594f162701088079589dfMisha Brukman // 1782441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 1792441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 180a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 181450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 1822441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isTwoAddrInstr(MachineOpCode Opcode) const { 1832441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_2_ADDR_FLAG; 1849ada014ec09579a7dd3833f779a1de82bd71bce1Misha Brukman } 1851b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner bool isPredicated(MachineOpCode Opcode) const { 1861b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner return get(Opcode).Flags & M_PREDICATED; 1871b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner } 18813d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng bool isCommutableInstr(MachineOpCode Opcode) const { 18913d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng return get(Opcode).Flags & M_COMMUTABLE; 19013d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng } 191075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner bool isTerminatorInstr(unsigned Opcode) const { 192075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 193075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 1940271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1950271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBranch(MachineOpCode Opcode) const { 1960271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 1970271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 1980271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 1990271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 2000271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// from executing the instruction immediately following it. Examples include 2010271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// unconditional branches and return instructions. 2020271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBarrier(MachineOpCode Opcode) const { 2030271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 2040271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2050271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2060271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isCall(MachineOpCode Opcode) const { 2070271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_CALL_FLAG; 2080271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2090271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isLoad(MachineOpCode Opcode) const { 2100271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 2110271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2120271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isStore(MachineOpCode Opcode) const { 2130271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_STORE_FLAG; 2140271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2150271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 216b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 217b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// which must be filled by the code generator. 218b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner bool hasDelaySlot(unsigned Opcode) const { 219b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 220b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 221b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 2220271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 2230271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 2240271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// machine basic block. 2250271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool usesCustomDAGSchedInsertionHook(unsigned Opcode) const { 2260271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 2270271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 228d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2298d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng bool hasVariableOperands(MachineOpCode Opcode) const { 2308d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng return get(Opcode).Flags & M_VARIABLE_OPS; 2318d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng } 2328d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 233e2ba8975883874633a1035c245af3b948b940b25Evan Cheng // Operand constraints: only "tied_to" for now. 234e2ba8975883874633a1035c245af3b948b940b25Evan Cheng enum OperandConstraint { 235e2ba8975883874633a1035c245af3b948b940b25Evan Cheng TIED_TO = 0 // Must be allocated the same register as. 236e2ba8975883874633a1035c245af3b948b940b25Evan Cheng }; 237e2ba8975883874633a1035c245af3b948b940b25Evan Cheng 238e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 239e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// it is set. Returns -1 if it is not set. 240e2ba8975883874633a1035c245af3b948b940b25Evan Cheng int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 241981b5bd7080db6dbbac6931863d8a2e6d1fc5a0cEvan Cheng OperandConstraint Constraint) const { 242e2ba8975883874633a1035c245af3b948b940b25Evan Cheng assert(OpNum < get(Opcode).numOperands && 243e2ba8975883874633a1035c245af3b948b940b25Evan Cheng "Invalid operand # of TargetInstrInfo"); 244e2ba8975883874633a1035c245af3b948b940b25Evan Cheng if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) { 245e2ba8975883874633a1035c245af3b948b940b25Evan Cheng unsigned Pos = 16 + Constraint * 4; 246e2ba8975883874633a1035c245af3b948b940b25Evan Cheng return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf; 247e2ba8975883874633a1035c245af3b948b940b25Evan Cheng } 248e2ba8975883874633a1035c245af3b948b940b25Evan Cheng return -1; 249e2ba8975883874633a1035c245af3b948b940b25Evan Cheng } 250e2ba8975883874633a1035c245af3b948b940b25Evan Cheng 251e6ae14e1f413987f3de31a7cad1b20a7893f8caeEvan Cheng /// findTiedToSrcOperand - Returns the operand that is tied to the specified 252981b5bd7080db6dbbac6931863d8a2e6d1fc5a0cEvan Cheng /// dest operand. Returns -1 if there isn't one. 253e6ae14e1f413987f3de31a7cad1b20a7893f8caeEvan Cheng int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const; 254981b5bd7080db6dbbac6931863d8a2e6d1fc5a0cEvan Cheng 255ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL 256ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner /// instruction if it has one. This is used by codegen passes that update 257ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner /// DWARF line number info as they modify the code. 258ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner virtual unsigned getDWARF_LABELOpcode() const { 259ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner return 0; 260ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner } 261ae1dc403274d3a64bcee31f15e2d25e4b7178811Chris Lattner 2620cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 2630cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 2645e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 2655e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 2665e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 2675e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 2685e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 269af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 270af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 271af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 272af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 273af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 274af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 275af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 276af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 277af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 278af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 279af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 280af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 281af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 282af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 283af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 284af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 285af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 286af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 2875e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 28815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 28915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 29015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// may be able to convert a two-address instruction into a true 29115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// three-address instruction on demand. This allows the X86 target (for 29215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 29315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 29415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 29515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 29615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// performed, otherwise it returns the new instruction. 29715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 29815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const { 29915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 30015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 30115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 302d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 303d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 304d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 305d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 306d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 307d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 308d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 309d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 310d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 311d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 312d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 313d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 314b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 315b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 316b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 317b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 318b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 31972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 32072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 32172dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 322b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 32372dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 3. If this block ends with an conditional branch, it returns the 'true' 324b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// destination in TBB, the 'false' destination in FBB, and a list of 325b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// operands that evaluate the condition. These operands can be passed to 326b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// other TargetInstrInfo methods to create new branches. 327b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 328b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 329b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 330b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 331b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 332b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 333b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner std::vector<MachineOperand> &Cond) const { 334b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 335905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 336b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 337b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 338b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// this is only invoked in cases where AnalyzeBranch returns success. 339d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner virtual void RemoveBranch(MachineBasicBlock &MBB) const { 340b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 341b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 342b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 343b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 344b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 34533644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 34633644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 34733644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// null, Cond is empty) needs to be inserted. 348d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 349d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 350d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner const std::vector<MachineOperand> &Cond) const { 35124321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 352b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 353b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 354c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 355c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 356c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 357c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 358c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 359c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 360c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 361c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 3625f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 3635f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 3645f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 3655f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 3665f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 367905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 3680271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 36965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 37065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 37165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 37265e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 37365e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 37465e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 37565e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 37621d03f2de0087d60dbf575d95924404a97852879Evan Cheng 37721d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 37821d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// values. 37921d03f2de0087d60dbf575d95924404a97852879Evan Cheng virtual const TargetRegisterClass *getPointerRegClass() const { 38021d03f2de0087d60dbf575d95924404a97852879Evan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 38121d03f2de0087d60dbf575d95924404a97852879Evan Cheng abort(); 38221d03f2de0087d60dbf575d95924404a97852879Evan Cheng } 383a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 384a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 385d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 386d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 387a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 388