TargetInstrInfo.h revision 2cc214c06cbb94f95928636981c9805d6300cff1
1a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//===-- llvm/Target/InstrInfo.h - Target Instruction Information --*-C++-*-==// 2a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 3a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 4a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 5a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//===---------------------------------------------------------------------===// 6a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 7a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#ifndef LLVM_TARGET_MACHINEINSTRINFO_H 8a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#define LLVM_TARGET_MACHINEINSTRINFO_H 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 10360e17eaf1a2abda82b02235dc57d26d8f83c937Chris Lattner#include "Support/DataTypes.h" 112cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 12a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adveclass MachineInstrDescriptor; 145684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 15f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 165684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Value; 175684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass Instruction; 182cc214c06cbb94f95928636981c9805d6300cff1Chris Lattnerclass Constant; 19e7506a366e8bd56c97d10beb68e4db953aebaecaChris Lattnerclass Function; 20c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adveclass MachineCodeForInstruction; 21a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 22f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 23f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 24f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 25a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 26f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnertypedef int MachineOpCode; 27c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 28a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 29851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adveconst MachineOpCode INVALID_MACHINE_OPCODE = -1; 30851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adve 31851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adve 32a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// Global variable holding an array of descriptors for machine instructions. 33a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// The actual object needs to be created separately for each target machine. 34a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This variable is initialized and reset by class MachineInstrInfo. 35a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 36a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// FIXME: This should be a property of the target so that more than one target 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// at a time can be active... 38a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 39a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adveextern const MachineInstrDescriptor *TargetInstrDescriptors; 40a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 41a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 42a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 43a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// struct MachineInstrDescriptor: 44a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// Predefined information about each machine instruction. 45a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// Designed to initialized statically. 46a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 47a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// class MachineInstructionInfo 48a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// Interface to description of machine instructions 49a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 50a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 51a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 52c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_NOP_FLAG = 1 << 0; 53c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 1; 54c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_CALL_FLAG = 1 << 2; 55c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_RET_FLAG = 1 << 3; 56c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_ARITH_FLAG = 1 << 4; 57c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_CC_FLAG = 1 << 6; 58c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_LOGICAL_FLAG = 1 << 6; 59c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_INT_FLAG = 1 << 7; 60c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_FLOAT_FLAG = 1 << 8; 61c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_CONDL_FLAG = 1 << 9; 62c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_LOAD_FLAG = 1 << 10; 63c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_PREFETCH_FLAG = 1 << 11; 64c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_STORE_FLAG = 1 << 12; 65c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_DUMMY_PHI_FLAG = 1 << 13; 66c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattnerconst unsigned M_PSEUDO_FLAG = 1 << 14; 67a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 68a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 69a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advestruct MachineInstrDescriptor { 70c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner const char * opCodeString; // Assembly language mnemonic for the opcode. 71c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner int numOperands; // Number of args; -1 if variable #args 72c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner int resultPos; // Position of the result; -1 if no result 73c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0. 74697954c15da58bd8b186dbafdedd8b06db770201Chris Lattner bool immedIsSignExtended; // Is IMMED field sign-extended? If so, 75a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // smallest -ve value is -(maxImmedConst+1). 76c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned numDelaySlots; // Number of delay slots after instruction 77c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned latency; // Latency in machine cycles 78a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve InstrSchedClass schedClass; // enum identifying instr sched class 79c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned iclass; // flags identifying machine instr class 80a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 81a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 82a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 832cc214c06cbb94f95928636981c9805d6300cff1Chris Lattnerclass MachineInstrInfo { 8444508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Advepublic: 8544508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Adve const TargetMachine& target; 8644508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Adve 87a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adveprotected: 88a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve const MachineInstrDescriptor* desc; // raw array to allow static init'n 89c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned descSize; // number of entries in the desc array 90c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 91a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 922cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner MachineInstrInfo(const MachineInstrInfo &); // DO NOT IMPLEMENT 932cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner void operator=(const MachineInstrInfo &); // DO NOT IMPLEMENT 94a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 9544508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Adve MachineInstrInfo(const TargetMachine& tgt, 9644508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Adve const MachineInstrDescriptor *desc, unsigned descSize, 97a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve unsigned numRealOpCodes); 98a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual ~MachineInstrInfo(); 99a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 100a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve unsigned getNumRealOpCodes() const { return numRealOpCodes; } 101a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve unsigned getNumTotalOpCodes() const { return descSize; } 102a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 103a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const { 104a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve assert(opCode >= 0 && opCode < (int)descSize); 105a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return desc[opCode]; 106a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 107a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 108a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve int getNumOperands(MachineOpCode opCode) const { 109a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).numOperands; 110a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 111a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 112a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve int getResultPos(MachineOpCode opCode) const { 113a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).resultPos; 114a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 115a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 116a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve unsigned getNumDelaySlots(MachineOpCode opCode) const { 117a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).numDelaySlots; 118a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 119a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 120a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve InstrSchedClass getSchedClass(MachineOpCode opCode) const { 121a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).schedClass; 122a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 123a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 124a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 125a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 126a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 127a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 128c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned getIClass(MachineOpCode opCode) const { 129a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass; 130a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 131a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isNop(MachineOpCode opCode) const { 132a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_NOP_FLAG; 133a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 134a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isBranch(MachineOpCode opCode) const { 135a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_BRANCH_FLAG; 136a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 137a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isCall(MachineOpCode opCode) const { 138a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_CALL_FLAG; 139a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 140a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isReturn(MachineOpCode opCode) const { 141a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_RET_FLAG; 142a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 143a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isControlFlow(MachineOpCode opCode) const { 144a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_BRANCH_FLAG 145a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve || getDescriptor(opCode).iclass & M_CALL_FLAG 146a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve || getDescriptor(opCode).iclass & M_RET_FLAG; 147a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 148a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isArith(MachineOpCode opCode) const { 149502374a58fcd1c28065170a8c4a210be002ff190Chris Lattner return getDescriptor(opCode).iclass & M_ARITH_FLAG; 150a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 151a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isCCInstr(MachineOpCode opCode) const { 152a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_CC_FLAG; 153a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 154a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isLogical(MachineOpCode opCode) const { 155a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_LOGICAL_FLAG; 156a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 157a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isIntInstr(MachineOpCode opCode) const { 158a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_INT_FLAG; 159a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 160a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isFloatInstr(MachineOpCode opCode) const { 161a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_FLOAT_FLAG; 162a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 163502374a58fcd1c28065170a8c4a210be002ff190Chris Lattner bool isConditional(MachineOpCode opCode) const { 164a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_CONDL_FLAG; 165a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 166a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isLoad(MachineOpCode opCode) const { 167a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_LOAD_FLAG; 168a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 169a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isPrefetch(MachineOpCode opCode) const { 170a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 171a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 172a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isLoadOrPrefetch(MachineOpCode opCode) const { 173a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_LOAD_FLAG 174a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve || getDescriptor(opCode).iclass & M_PREFETCH_FLAG; 175a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 176a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isStore(MachineOpCode opCode) const { 177a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_STORE_FLAG; 178a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 179a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool isMemoryAccess(MachineOpCode opCode) const { 180a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_LOAD_FLAG 181a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve || getDescriptor(opCode).iclass & M_PREFETCH_FLAG 182a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve || getDescriptor(opCode).iclass & M_STORE_FLAG; 183a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 1840d3ea0268f44f8fd4ddf7a15f3624b384b0691dbRuchira Sasanka bool isDummyPhiInstr(const MachineOpCode opCode) const { 185a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG; 186a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 187b9f550ddfbaf963a0aced2df8cd40c71021fd3e5Ruchira Sasanka bool isPseudoInstr(const MachineOpCode opCode) const { 188b9f550ddfbaf963a0aced2df8cd40c71021fd3e5Ruchira Sasanka return getDescriptor(opCode).iclass & M_PSEUDO_FLAG; 189b9f550ddfbaf963a0aced2df8cd40c71021fd3e5Ruchira Sasanka } 190d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 191a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Check if an instruction can be issued before its operands are ready, 192a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // or if a subsequent instruction that uses its result can be issued 193a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // before the results are ready. 194a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Default to true since most instructions on many architectures allow this. 195a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 196a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual bool hasOperandInterlock(MachineOpCode opCode) const { 197a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return true; 198a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 199a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 200a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual bool hasResultInterlock(MachineOpCode opCode) const { 201a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return true; 202a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 203a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 204a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 205a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Latencies for individual instructions and instruction pairs 206a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 207a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual int minLatency(MachineOpCode opCode) const { 208a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).latency; 209a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 210a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 211a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual int maxLatency(MachineOpCode opCode) const { 212a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).latency; 213a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 2144c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve 2154c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve // 2164c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve // Which operand holds an immediate constant? Returns -1 if none 2174c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve // 218851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adve virtual int getImmedConstantPos(MachineOpCode opCode) const { 2194c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve return -1; // immediate position is machine specific, so say -1 == "none" 2204c5fe2d3ed4043c34f3305c081297ba4ca26ddc2Vikram S. Adve } 221a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 222a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Check if the specified constant fits in the immediate field 223a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // of this machine instruction 224a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 225a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual bool constantFitsInImmedField(MachineOpCode opCode, 226a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve int64_t intValue) const; 227a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 228a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Return the largest +ve constant that can be held in the IMMMED field 229a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // of this machine instruction. 230a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // isSignExtended is set to true if the value is sign-extended before use 231a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // (this is true for all immediate fields in SPARC instructions). 232a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Return 0 if the instruction has no IMMED field. 233a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 234a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve virtual uint64_t maxImmedConstant(MachineOpCode opCode, 235a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve bool &isSignExtended) const { 236a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve isSignExtended = getDescriptor(opCode).immedIsSignExtended; 237a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve return getDescriptor(opCode).maxImmedConst; 238a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 2395684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve 2405684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve //------------------------------------------------------------------------- 2414900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve // Queries about representation of LLVM quantities (e.g., constants) 2424900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve //------------------------------------------------------------------------- 2434900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve 2442cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner /// ConstantTypeMustBeLoaded - Test if this type of constant must be loaded 2452cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner /// from memory into a register, i.e., cannot be set bitwise in register and 2462cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner /// cannot use immediate fields of instructions. Note that this only makes 2472cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner /// sense for primitive types. 2482cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner /// 2492cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner virtual bool ConstantTypeMustBeLoaded(const Constant* CV) const; 2504900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve 2514900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve // Test if this constant may not fit in the immediate field of the 2524900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve // machine instructions (probably) generated for this instruction. 2534900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve // 2544900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve virtual bool ConstantMayNotFitInImmedField(const Constant* CV, 2554900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve const Instruction* I) const { 2564900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve return true; // safe but very conservative 2574900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve } 2584900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve 2594900116ab0c17252bdca2e66b87d8b6da1839b54Vikram S. Adve //------------------------------------------------------------------------- 2605684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve // Code generation support for creating individual machine instructions 2615684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve //------------------------------------------------------------------------- 262d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 263d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve // Get certain common op codes for the current target. this and all the 264d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve // Create* methods below should be moved to a machine code generation class 265d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve // 266d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve virtual MachineOpCode getNOPOpCode() const = 0; 267d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2685684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve // Create an instruction sequence to put the constant `val' into 269e9bb2df410f7a22decad9a883f7139d5857c1520Chris Lattner // the virtual register `dest'. `val' may be a Constant or a 2705684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve // GlobalValue, viz., the constant address of a global variable or function. 271c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // The generated instructions are returned in `mvec'. 272c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 273bba2485c709adecd65526fbcfea77f2344d29d69Vikram S. Adve // Symbolic constants or constants that must be accessed from memory 274fce1143bcfa73f61845002fa50473d1a01384202Misha Brukman // are added to the constant pool via MachineFunction::get(F). 2755684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve // 276c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve virtual void CreateCodeToLoadConst(const TargetMachine& target, 277c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Function* F, 278851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adve Value* val, 2795684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adve Instruction* dest, 280c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve std::vector<MachineInstr*>& mvec, 281bba2485c709adecd65526fbcfea77f2344d29d69Vikram S. Adve MachineCodeForInstruction& mcfi) const=0; 282bba2485c709adecd65526fbcfea77f2344d29d69Vikram S. Adve 2834938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // Create an instruction sequence to copy an integer value `val' 2844938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // to a floating point value `dest' by copying to memory and back. 2854938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // val must be an integral type. dest must be a Float or Double. 286c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // The generated instructions are returned in `mvec'. 287c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 288c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any stack space required is allocated via mcff. 28944508e333cc1d36e699aa330d84312d1c8fc655aVikram S. Adve // 290c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target, 291c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Function* F, 292c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Value* val, 293c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Instruction* dest, 294c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve std::vector<MachineInstr*>& mvec, 295c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve MachineCodeForInstruction& mcfi)const=0; 2964938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve 2974938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // Similarly, create an instruction sequence to copy an FP value 2984938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // `val' to an integer value `dest' by copying to memory and back. 299c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // The generated instructions are returned in `mvec'. 300c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 301c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any stack space required is allocated via mcff. 302c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // 303c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target, 304c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Function* F, 305c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Value* val, 306c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Instruction* dest, 307c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve std::vector<MachineInstr*>& mvec, 308c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve MachineCodeForInstruction& mcfi)const=0; 309c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve 310c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Create instruction(s) to copy src to dest, for arbitrary types 311c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // The generated instructions are returned in `mvec'. 312c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 313c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any stack space required is allocated via mcff. 3144938d4528f80dd015c58dec9d6d72bc27bf26bbdVikram S. Adve // 315851597c3b34a03b700f48d284fb9b186ccf9ef91Vikram S. Adve virtual void CreateCopyInstructionsByType(const TargetMachine& target, 316c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Function* F, 317c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Value* src, 318c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Instruction* dest, 319c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve std::vector<MachineInstr*>& mvec, 320c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve MachineCodeForInstruction& mcfi)const=0; 321c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve 322c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Create instruction sequence to produce a sign-extended register value 323c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // from an arbitrary sized value (sized in bits, not bytes). 32468f716190baa08675793adba428605797eb658a4Vikram S. Adve // The generated instructions are appended to `mvec'. 32568f716190baa08675793adba428605797eb658a4Vikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 326c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // Any stack space required is allocated via mcff. 327c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve // 328c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve virtual void CreateSignExtensionInstructions(const TargetMachine& target, 329c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve Function* F, 33068f716190baa08675793adba428605797eb658a4Vikram S. Adve Value* srcVal, 3319d0168d2d54008729632f676475ce710448cf8a8Vikram S. Adve Value* destVal, 332c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned numLowBits, 333c864fde15c68fe56d2af48ddeaddfd4e13006f4aVikram S. Adve std::vector<MachineInstr*>& mvec, 33468f716190baa08675793adba428605797eb658a4Vikram S. Adve MachineCodeForInstruction& mcfi) const=0; 33568f716190baa08675793adba428605797eb658a4Vikram S. Adve 33668f716190baa08675793adba428605797eb658a4Vikram S. Adve // Create instruction sequence to produce a zero-extended register value 33768f716190baa08675793adba428605797eb658a4Vikram S. Adve // from an arbitrary sized value (sized in bits, not bytes). 33868f716190baa08675793adba428605797eb658a4Vikram S. Adve // The generated instructions are appended to `mvec'. 33968f716190baa08675793adba428605797eb658a4Vikram S. Adve // Any temp. registers (TmpInstruction) created are recorded in mcfi. 34068f716190baa08675793adba428605797eb658a4Vikram S. Adve // Any stack space required is allocated via mcff. 34168f716190baa08675793adba428605797eb658a4Vikram S. Adve // 34268f716190baa08675793adba428605797eb658a4Vikram S. Adve virtual void CreateZeroExtensionInstructions(const TargetMachine& target, 34368f716190baa08675793adba428605797eb658a4Vikram S. Adve Function* F, 34468f716190baa08675793adba428605797eb658a4Vikram S. Adve Value* srcVal, 3459d0168d2d54008729632f676475ce710448cf8a8Vikram S. Adve Value* destVal, 346c7e65fb7d850d010a141420d7b1d8ddad484d3b3Chris Lattner unsigned srcSizeInBits, 34768f716190baa08675793adba428605797eb658a4Vikram S. Adve std::vector<MachineInstr*>& mvec, 34868f716190baa08675793adba428605797eb658a4Vikram S. Adve MachineCodeForInstruction& mcfi) const=0; 349a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 350a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 351a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 352