TargetInstrInfo.h revision 3651d92d91062ea4b1ee8b2a88eca03bd39e1968
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 1061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman// This file describes the target machine instruction set to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17d3f99e2bbf5e62261c8948127aacfe9a7d3b2456Chris Lattner#include "llvm/Target/TargetInstrDesc.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 20d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 21d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 22d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Andersonclass CalleeSavedInfo; 23729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass InstrItineraryData; 24506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass LiveVariables; 25506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MCAsmInfo; 26506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass MachineMemOperand; 27962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Chengclass MDNode; 28ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattnerclass MCInst; 2943dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SDNode; 30729aab3dd3a6ea5ca23430936270154090fcc10bEvan Chengclass ScheduleHazardRecognizer; 3143dbe05279b753aabda571d9c83eaeb36987001aOwen Andersonclass SelectionDAG; 32506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterClass; 33506049f29f4f202a8e45feb916cc0264440a7f6dEvan Chengclass TargetRegisterInfo; 34a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 35f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersontemplate<class T> class SmallVectorImpl; 36f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 383501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 3934695381d626485a560594f162701088079589dfMisha Brukman/// 4061e804f22bde414b2e8a8da22daf575a7e8ad816Dan Gohman/// TargetInstrInfo - Interface to description of machine instruction set 4134695381d626485a560594f162701088079589dfMisha Brukman/// 42075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 43749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc *Descriptors; // Raw array to allow static init'n 44749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner unsigned NumOpcodes; // Number of entries in the desc array 4534695381d626485a560594f162701088079589dfMisha Brukman 46075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 47075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 48a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 49749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); 50075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 5170535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 52bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 5334695381d626485a560594f162701088079589dfMisha Brukman 54e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 55e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 56e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 57749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner const TargetInstrDesc &get(unsigned Opcode) const { 58749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner assert(Opcode < NumOpcodes && "Invalid opcode!"); 59749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner return Descriptors[Opcode]; 60a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 614683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 62041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 63d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 64d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 65a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isTriviallyReMaterializable(const MachineInstr *MI, 66a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA = 0) const { 67518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF || 68a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman (MI->getDesc().isRematerializable() && 693731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman (isReallyTriviallyReMaterializable(MI, AA) || 70a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman isReallyTriviallyReMaterializableGeneric(MI, AA))); 71d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 72d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 73d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 74041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 75a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// which the M_REMATERIALIZABLE flag is set, this hook lets the target 76a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// specify whether the instruction is actually trivially rematerializable, 77a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// taking into consideration its operands. This predicate must return false 78a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if the instruction has any side effects other than producing a value, or 79a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// if it requres any address registers that are not always available. 803731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 813731bc026cc6c4fb7deb7ac67e2c3be0c22498beDan Gohman AliasAnalysis *AA) const { 82a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman return false; 83d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 84d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 85a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohmanprivate: 86a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializableGeneric - For instructions with opcodes 87a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// for which the M_REMATERIALIZABLE flag is set and the target hook 88a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// isReallyTriviallyReMaterializable returns false, this function does 89a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// target-independent tests to determine if the instruction is really 90a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman /// trivially rematerializable. 91a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, 92a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman AliasAnalysis *AA) const; 93a70dca156fa76d452f54829b5c5f962ddfd94ef2Dan Gohman 94d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 95c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// isMoveInstr - Return true if the instruction is a register to register 96c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// move and return the source and dest operands and their sub-register 97c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// indices by reference. 985e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 9904ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcReg, unsigned& DstReg, 10004ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned& SrcSubIdx, unsigned& DstSubIdx) const { 1015e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 1025e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 103c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 1047da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 1057da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// extension instruction. That is, it's like a copy where it's legal for the 1067da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 1077da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// true, then it's expected the pre-extension value is available as a subreg 1087da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// of the result register. This also returns the sub-register index in 1097da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng /// SubIdx. 1107da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng virtual bool isCoalescableExtInstr(const MachineInstr &MI, 1117da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SrcReg, unsigned &DstReg, 1127da9ecf9677b751d81515f95168ae3cb2df54160Evan Cheng unsigned &SubIdx) const { 113a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng return false; 114a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng } 115a5a81d70720a4ce6ac7538927c2a874b0dfa8bd2Evan Cheng 116c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// isIdentityCopy - Return true if the instruction is a copy (or 117c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// extract_subreg, insert_subreg, subreg_to_reg) where the source and 118c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng /// destination registers are the same. 119a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng bool isIdentityCopy(const MachineInstr &MI) const { 120a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; 121c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && 122c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng SrcReg == DstReg) 123c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng return true; 124c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 125518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if (MI.getOpcode() == TargetOpcode::EXTRACT_SUBREG && 126a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) 127a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng return true; 128c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng 129518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner if ((MI.getOpcode() == TargetOpcode::INSERT_SUBREG || 130518bb53485df640d7b7e3f6b0544099020c42aa7Chris Lattner MI.getOpcode() == TargetOpcode::SUBREG_TO_REG) && 131a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) 132a5dc45e3c8fa26e62b187284a240adf3879b56e2Evan Cheng return true; 133c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng return false; 134c9dfeb1be841045427d71b85e95ac7355b64e8b1Evan Cheng } 135af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 136af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 137af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 138af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 139af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 140af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 141cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 142cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 143af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 144af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 145b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 146dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 147dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 148dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 149dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 150dda3978d7877d2d60390833c73ed24857295e89cDavid Greene int &FrameIndex) const { 151dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 152dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 153dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 154b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasLoadFromStackSlot - If the specified machine instruction has 155b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// a load from a stack slot, return true along with the FrameIndex 1565e3363255912c559e8251121491a2a9e901f07acDavid Greene /// of the loaded stack slot and the machine mem operand containing 1575e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the reference. If not, return false. Unlike 158b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// isLoadFromStackSlot, this returns true for any instructions that 159b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// loads from the stack. This is just a hint, as some cases may be 160b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// missed. 161b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasLoadFromStackSlot(const MachineInstr *MI, 1625e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 163b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const { 164b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene return 0; 165b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene } 166af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 167af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 168af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 169af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 170af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 171af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 172cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 173cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohman int &FrameIndex) const { 174af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 175af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 1765e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 177dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 178dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// stack locations as well. This uses a heuristic so it isn't 179dda3978d7877d2d60390833c73ed24857295e89cDavid Greene /// reliable for correctness. 180dda3978d7877d2d60390833c73ed24857295e89cDavid Greene virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 1815e3363255912c559e8251121491a2a9e901f07acDavid Greene int &FrameIndex) const { 182dda3978d7877d2d60390833c73ed24857295e89cDavid Greene return 0; 183dda3978d7877d2d60390833c73ed24857295e89cDavid Greene } 184dda3978d7877d2d60390833c73ed24857295e89cDavid Greene 185b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// hasStoreToStackSlot - If the specified machine instruction has a 186b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene /// store to a stack slot, return true along with the FrameIndex of 1875e3363255912c559e8251121491a2a9e901f07acDavid Greene /// the loaded stack slot and the machine mem operand containing the 1885e3363255912c559e8251121491a2a9e901f07acDavid Greene /// reference. If not, return false. Unlike isStoreToStackSlot, 1892dbc8bdfe9191c2078daccbeefba9e69a690feb6Evan Cheng /// this returns true for any instructions that stores to the 1905e3363255912c559e8251121491a2a9e901f07acDavid Greene /// stack. This is just a hint, as some cases may be missed. 191b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene virtual bool hasStoreToStackSlot(const MachineInstr *MI, 1925e3363255912c559e8251121491a2a9e901f07acDavid Greene const MachineMemOperand *&MMO, 193b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene int &FrameIndex) const { 194b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene return 0; 195b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene } 196b87bc95db075dae3033a3c541b55b4cb711c332cDavid Greene 197ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// reMaterialize - Re-issue the specified 'original' instruction at the 198ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng /// specific location targeting a new destination register. 1999edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// The register in Orig->getOperand(0).getReg() will be substituted by 2009edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 2019edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen /// SubIdx. 202ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 203ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 204378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubIdx, 205d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 2069edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const = 0; 207ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng 20868fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 20968fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng /// two-addrss instruction inserted by two-address pass. 21068fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng virtual void scheduleTwoAddrSource(MachineInstr *SrcMI, 21168fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng MachineInstr *UseMI, 21268fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng const TargetRegisterInfo &TRI) const { 21368fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng // Do nothing. 21468fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng } 21568fc2daf8fa446be04d2ed2b3cbb1b00c382458fEvan Cheng 21630ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// duplicate - Create a duplicate of the Orig instruction in MF. This is like 21730ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// MachineFunction::CloneMachineInstr(), but the target may update operands 21830ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen /// that are required to be unique. 219d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// 220d1862037f04954f00cd6e6066ee213cfdc292877Jakob Stoklund Olesen /// The instruction must be duplicable as indicated by isNotDuplicable(). 22130ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen virtual MachineInstr *duplicate(MachineInstr *Orig, 22230ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const = 0; 22330ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen 22415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 22515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 2262c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 2276c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 22815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 22915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 23015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 23115f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 2326c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 23315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 2346c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 2356c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 236f660c171c838793b87b7e58e91609cecf256378dOwen Anderson MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const { 23715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 23815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 23915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 240f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commuteInstruction - If a target has any instructions that are 241f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// commutable but require converting to different instructions or making 242f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// non-trivial changes to commute them, this method can overloaded to do 243f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// that. The default implementation simply swaps the commutable operands. 244f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// If NewMI is false, MI is modified in place and returned; otherwise, a 245f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// new machine instruction is created and returned. Do not call this 246f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// method for a non-commutable instruction, but there may be some cases 247f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// where this method fails and returns null. 24858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 24958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const = 0; 250d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 251261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// findCommutedOpIndices - If specified MI is commutable, return the two 252f0e1b8942157f4344cce36e98c7dabb230d52bf8Bob Wilson /// operand indices that would swap value. Return false if the instruction 253261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng /// is not in a form which this routine understands. 254261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 255261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const = 0; 256f20db159541bf27f5d2fdf8d4ba1c8b270b936dfEvan Cheng 257506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// produceSameValue - Return true if two machine instructions would produce 258506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// identical values. By default, this is only true when the two instructions 259506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng /// are deemed identical except for defs. 260506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 261506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const = 0; 26212749db1503c2beed58ddcfba5f1b323611fb2ceEvan Cheng 263b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 264b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 265b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 266b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 267b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 26872dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 26972dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 27072dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 271b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 27285de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// 3. If this block ends with a conditional branch and it falls through to a 27385de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// successor block, it sets TBB to be the branch destination block and a 27485de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// list of operands that evaluate the condition. These operands can be 27585de1e5bade2f3755e47ed6fd43c92fcf99ff08bBill Wendling /// passed to other TargetInstrInfo methods to create new branches. 276a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 4. If this block ends with a conditional branch followed by an 277a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// unconditional branch, it returns the 'true' destination in TBB, the 278a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// 'false' destination in FBB, and a list of operands that evaluate the 279a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// condition. These operands can be passed to other TargetInstrInfo 280a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// methods to create new branches. 281b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 282b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 283b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 284b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 285dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// If AllowModify is true, then this routine is allowed to modify the basic 286dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// block (e.g. delete instructions after the unconditional branch). 287dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng /// 288b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 289b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 290dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng SmallVectorImpl<MachineOperand> &Cond, 291dc54d317e7a381ef8e4aca80d54ad1466bb85ddaEvan Cheng bool AllowModify = false) const { 292b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 293905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 294a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 295b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 2968c8b2a89f9173aaa06e91ff43c3a46276f23b355Dan Gohman /// This is only invoked in cases where AnalyzeBranch returns success. It 297b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 298b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 299b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 300b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 301b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 302a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman 303a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// InsertBranch - Insert branch code into the end of the specified 304a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// MachineBasicBlock. The operands to this method are the same as those 305a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// returned by AnalyzeBranch. This is only invoked in cases where 306a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// AnalyzeBranch returns success. It returns the number of instructions 307a5595b02daae4641f7120b44ef05ba9c494bb461Dan Gohman /// inserted. 308c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// 309c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// It is also invoked by tail merging to add unconditional branches in 310c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// cases where AnalyzeBranch doesn't apply because there was no original 311c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// branch to analyze. At least this much must be implemented, else tail 312c1c9d7e6a95e2090d74f271209fc9337e74ab9bfDale Johannesen /// merging needs to be disabled. 313b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 3143bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings MachineBasicBlock *FBB, 3153bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings const SmallVectorImpl<MachineOperand> &Cond, 3163bf912593301152b65accb9d9c37a95172f1df5aStuart Hastings DebugLoc DL) const { 31724321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 318b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 319b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 32086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 32186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything 32286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// after it, replacing it with an unconditional branch to NewDest. This is 32386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// used by the tail merging pass. 32486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 32586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const = 0; 3264d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng 3274d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic 3284d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// block at the specified instruction (i.e. instruction would be the start 3294d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng /// of a new basic block). 3304d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 3314d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng MachineBasicBlock::iterator MBBI) const { 3324d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng return true; 3334d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855Evan Cheng } 33413151432edace19ee867a93b5c14573df4f75d24Evan Cheng 33513151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToIfCvt - Return true if it's profitable to first "NumInstrs" 33613151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// of the specified basic block. 33713151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual 33813151432edace19ee867a93b5c14573df4f75d24Evan Cheng bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const { 33913151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 34013151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 34113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 34213151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one 34313151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// checks for the case where two basic blocks from true and false path 34413151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// of a if-then-else (diamond) are predicated on mutally exclusive 34513151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// predicates. 34613151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 34713151432edace19ee867a93b5c14573df4f75d24Evan Cheng isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs, 34813151432edace19ee867a93b5c14573df4f75d24Evan Cheng MachineBasicBlock &FMBB, unsigned NumFInstrs) const { 34913151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 35013151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 35113151432edace19ee867a93b5c14573df4f75d24Evan Cheng 35213151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// isProfitableToDupForIfCvt - Return true if it's profitable for 35313151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// if-converter to duplicate a specific number of instructions in the 35413151432edace19ee867a93b5c14573df4f75d24Evan Cheng /// specified MBB to enable if-conversion. 35513151432edace19ee867a93b5c14573df4f75d24Evan Cheng virtual bool 35613151432edace19ee867a93b5c14573df4f75d24Evan Cheng isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs) const { 35713151432edace19ee867a93b5c14573df4f75d24Evan Cheng return false; 35813151432edace19ee867a93b5c14573df4f75d24Evan Cheng } 359b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 360a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// copyRegToReg - Emit instructions to copy between a pair of registers. It 361a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// returns false if the target does not how to copy between the specified 362a6548d0f29d848ce5e2c10ebd6aae196ce3d8651Evan Cheng /// registers. 363940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson virtual bool copyRegToReg(MachineBasicBlock &MBB, 364d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 365d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 366d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 36734dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman const TargetRegisterClass *SrcRC, 36834dcc6fadca0a1117cdbd0e9b35c991a55b6e556Dan Gohman DebugLoc DL) const { 369d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 370c93457053cfecb24105ee3800c8e53921b950d8fCedric Venet return false; 371d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 3723651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen 3733651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen /// copyPhysReg - Emit instructions to copy a pair of physical registers. 3743651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 3753651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen MachineBasicBlock::iterator MI, DebugLoc DL, 3763651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 3773651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen bool KillSrc) const =0; 3783651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen 37995a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// storeRegToStackSlot - Store the specified register of the given register 38095a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class to the specified stack frame index. The store instruction is to be 38195a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 38295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. If isKill is true, the register operand is the last use and 38395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// must be marked kill. 384f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 385f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 386f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FrameIndex, 387746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 388746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 389f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!"); 390f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 391f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 39295a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// loadRegFromStackSlot - Load the specified register of the given register 39395a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// class from the specified stack frame index. The load instruction is to be 39495a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// added to the given machine basic block before the specified machine 39595a3f0d99e9551404c217f62d0991b922ead22a9Evan Cheng /// instruction. 396f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 397f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineBasicBlock::iterator MI, 398f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FrameIndex, 399746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 400746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 401f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!"); 402f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 403f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 404d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee 405d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 406d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of store instructions via 407d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// storeRegToStackSlot(). Returns false otherwise. 408d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, 409d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 4102457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const std::vector<CalleeSavedInfo> &CSI, 4112457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const TargetRegisterInfo *TRI) const { 412d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 413d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 414d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 415d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee 416d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// saved registers and returns true if it isn't possible / profitable to do 417d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// so by issuing a series of load instructions via loadRegToStackSlot(). 418d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson /// Returns false otherwise. 419d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 420d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson MachineBasicBlock::iterator MI, 4212457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const std::vector<CalleeSavedInfo> &CSI, 4222457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng const TargetRegisterInfo *TRI) const { 423d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson return false; 424d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson } 425d94b6a16fec7d5021e3922b0e34f9ddb268d54b1Owen Anderson 426962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// emitFrameIndexDebugValue - Emit a target-dependent form of 427962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// DBG_VALUE encoding the address of a frame index. Addresses would 428962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// normally be lowered the same way as other addresses on the target, 429962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// e.g. in load instructions. For targets that do not support this 430962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng /// the debug info is simply lost. 431efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// If you add this for a target you should handle this DBG_VALUE in the 432efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// target-specific AsmPrinter code as well; you will probably get invalid 433efc3a6348addd7c9158348fa01f4602e0e0b1688Dale Johannesen /// assembly output if you don't. 434962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, 4358601a3d4decff0a380e059b037dabf71075497d3Evan Cheng int FrameIx, 436962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng uint64_t Offset, 437962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng const MDNode *MDPtr, 438962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng DebugLoc dl) const { 439962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng return 0; 440962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng } 441962021bc7f6721c20c7dfe8ca809e2d98b1c554aEvan Cheng 44243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Attempt to fold a load or store of the specified stack 44343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// slot into the specified machine instruction for the specified operand(s). 44443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// If this is possible, a new instruction is returned with the specified 44543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// operand folded, otherwise NULL is returned. The client is responsible for 44643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// removing the old instruction and adding the new one in the instruction 44743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stream. 448c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 449c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 450c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 451c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const; 45243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 45343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// foldMemoryOperand - Same as the previous version except it allows folding 45443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// of any load and store from / to any address, not just from a specific 45543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// stack slot. 456c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* foldMemoryOperand(MachineFunction &MF, 457c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 458c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 459c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const; 460c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 461c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanprotected: 462c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 463c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 464c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 465c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 4665fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 4678e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 468c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FrameIndex) const { 469c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman return 0; 470c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman } 471c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman 472c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperandImpl - Target-dependent implementation for 473c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// foldMemoryOperand. Target-independent code in foldMemoryOperand will 474c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman /// take care of adding a MachineMemOperand to the newly created instruction. 475c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, 476c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 477c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman const SmallVectorImpl<unsigned> &Ops, 478c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* LoadMI) const { 47943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 48043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 48143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 482c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohmanpublic: 4832b00aebda9705b7d76e90e632a5de511e59c739dDan Gohman /// canFoldMemoryOperand - Returns true for the specified load / store if 48443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// folding is possible. 48543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual 4868e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman bool canFoldMemoryOperand(const MachineInstr *MI, 4878e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops) const { 48843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 48943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 49043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 49143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// unfoldMemoryOperand - Separate a single instruction which folded a load or 49243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// a store or a load and a store into two or more instruction. If this is 49343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// possible, returns true as well as the new instructions by reference. 49443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 49543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 496c781a243a3d17e7e763515794168d8fa6043f565Evan Cheng SmallVectorImpl<MachineInstr*> &NewMIs) const{ 49743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 49843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 49943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 50043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 50143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson SmallVectorImpl<SDNode*> &NewNodes) const { 50243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return false; 50343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 50443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 50543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 50643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// instruction after load / store are unfolded from an instruction of the 50743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson /// specified opcode. It returns zero if the specified unfolding is not 5080115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// possible. If LoadRegIndex is non-null, it is filled in with the operand 5090115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// index of the operand which will hold the register holding the loaded 5100115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman /// value. 51143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 5120115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman bool UnfoldLoad, bool UnfoldStore, 5130115e164bad632572e2cfbaf72f0f0882d5319deDan Gohman unsigned *LoadRegIndex = 0) const { 51443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return 0; 51543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 51696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 51796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 51896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to determine if two loads are loading from the same base address. It 51996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// should only return true if the base pointers are the same and the 52096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// only differences between the two addresses are the offset. It also returns 52196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// the offsets by reference. 52296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 52396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t &Offset1, int64_t &Offset2) const { 52496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 52596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 52696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng 52796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 52896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// determine (in conjuction with areLoadsFromSameBasePtr) if two loads should 52996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// be scheduled togther. On some targets if two loads are loading from 53096dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// addresses in the same cache line, it's better if they are scheduled 53196dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// together. This function takes two integers that represent the load offsets 53296dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// from the common base address. It returns true if it decides it's desirable 53396dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// to schedule the two loads together. "NumLoads" is the number of loads that 53496dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng /// have already been scheduled after Load1. 53596dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 53696dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng int64_t Offset1, int64_t Offset2, 53796dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng unsigned NumLoads) const { 53896dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng return false; 53996dc115ef3ee019cb91d7c112358a77536c38a53Evan Cheng } 54043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 5415f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 5425f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 5435f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 54444eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson virtual 54544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 5465f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 547905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 5480271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 54965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 55065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 55165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 552b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner MachineBasicBlock::iterator MI) const; 553b6bbfebdc683a6a123410bca1175e14d264d4bc2Chris Lattner 554ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner 555ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 556ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner virtual void getNoopForMachoTarget(MCInst &NopInst) const { 557ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner // Default to just using 'nop' string. 558ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner } 559ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner 560ee9eb411fffddbb8fe70418c05946a131889b487Chris Lattner 561bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 5624f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 563f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 5644f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 5654f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 5664f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 567bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 568bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 569318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 570bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 5710402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 57202c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 573f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 574f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 57544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const = 0; 5764f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 577bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 5784f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 579f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 58044eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 58144eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred2) const { 5824f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 5834f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 5840402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 585ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 586ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 587ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 588ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 589ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 590ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 591ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 592ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 593e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// isPredicable - Return true if the specified instruction can be predicated. 594e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// By default, this returns true for every instruction with a 595e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng /// PredicateOperand. 596e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng virtual bool isPredicable(MachineInstr *MI) const { 597e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng return MI->getDesc().isPredicable(); 598e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng } 599e54cb16308ad40d0f0b257de47efaa0ee5a47004Evan Cheng 6004350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 6014350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng /// instruction that defines the specified register class. 6024350eb86a7cdc83fa6a5f4819a7f0534ace5cd58Evan Cheng virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 60323066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng return true; 60423066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng } 60523066288fdf4867f53f208f9aaf2952b1c049394Evan Cheng 60686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// isSchedulingBoundary - Test if the given instruction should be 60786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// considered a scheduling boundary. This primarily includes labels and 60886050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng /// terminators. 60986050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 61086050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 61186050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const = 0; 61286050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng 61352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// GetInstSize - Returns the size of the specified Instruction. 61452e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 61552e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetInstSizeInBytes(const MachineInstr *MI) const { 61652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray assert(0 && "Target didn't implement TargetInstrInfo::GetInstSize!"); 61752e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray return 0; 61852e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray } 61952e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray 620d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// GetFunctionSizeInBytes - Returns the size of the specified 621d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// MachineFunction. 62252e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray /// 62352e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const = 0; 624d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner 625d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// Measure the specified inline asm to determine an approximation of its 626d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner /// length. 627d90183d25dcbc0eabde56319fed4e8d6ace2e6ebChris Lattner virtual unsigned getInlineAsmLength(const char *Str, 62833adcfb4d217f5f23d9bde8ba02b8e48f9605fc5Chris Lattner const MCAsmInfo &MAI) const; 629729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng 630729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng /// CreateTargetHazardRecognizer - Allocate and return a hazard recognizer 631729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng /// to use for this target when scheduling the machine instructions after 632729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng /// register allocation. 633729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng virtual ScheduleHazardRecognizer* 634729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const = 0; 635a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 636a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 637641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 638641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 639641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 640641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 641641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 642641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 643749c6f6b5ed301c84aac562e414486549d7b98ebChris Lattner TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) 644641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 645641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 64686050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, 64786050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng MachineBasicBlock *NewDest) const; 64858dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng virtual MachineInstr *commuteInstruction(MachineInstr *MI, 64958dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6Evan Cheng bool NewMI = false) const; 650261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 651261ce1d5f89155d2e6f914f281db2004c89ee839Evan Cheng unsigned &SrcOpIdx2) const; 652641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 65344eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Pred) const; 654ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng virtual void reMaterialize(MachineBasicBlock &MBB, 655ca1267c02b025cc719190b05f9e1a5d174a9caf7Evan Cheng MachineBasicBlock::iterator MI, 656378445303b10b092a898a75131141a8259cff50bEvan Cheng unsigned DestReg, unsigned SubReg, 657d57cdd5683ea926e489067364fb7ffe5fd5d35eeEvan Cheng const MachineInstr *Orig, 6589edf7deb37f0f97664f279040fa15d89f32e23d9Jakob Stoklund Olesen const TargetRegisterInfo &TRI) const; 65930ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen virtual MachineInstr *duplicate(MachineInstr *Orig, 66030ac0467ced4627a9b84d8a1d3ca5e8706ddad63Jakob Stoklund Olesen MachineFunction &MF) const; 661506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng virtual bool produceSameValue(const MachineInstr *MI0, 662506049f29f4f202a8e45feb916cc0264440a7f6dEvan Cheng const MachineInstr *MI1) const; 66386050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng virtual bool isSchedulingBoundary(const MachineInstr *MI, 66486050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineBasicBlock *MBB, 66586050dc8cc0aaea8c9dfeb89de02cafbd7f48d92Evan Cheng const MachineFunction &MF) const; 66652e724ad7e679ee590f4bd763d55280586a8f1bcNicolas Geoffray virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const; 667729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng 668729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng virtual ScheduleHazardRecognizer * 669729aab3dd3a6ea5ca23430936270154090fcc10bEvan Cheng CreateTargetPostRAHazardRecognizer(const InstrItineraryData&) const; 6703651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen virtual void copyPhysReg(MachineBasicBlock &MBB, 6713651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen MachineBasicBlock::iterator MI, DebugLoc DL, 6723651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen unsigned DestReg, unsigned SrcReg, 6733651d92d91062ea4b1ee8b2a88eca03bd39e1968Jakob Stoklund Olesen bool KillSrc) const; 674641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 675641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 676d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 677d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 678a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 679