TargetInstrInfo.h revision 641055225092833197efe8e5bce01d50bcf1daae
1075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// 234695381d626485a560594f162701088079589dfMisha Brukman// 36fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// The LLVM Compiler Infrastructure 46fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell// 57ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// This file is distributed under the University of Illinois Open Source 67ed47a13356daed2a34cd2209a31f92552e3bdd8Chris Lattner// License. See LICENSE.TXT for details. 734695381d626485a560594f162701088079589dfMisha Brukman// 86fbcc26f1460eaee4e0eb8b426fc1ff0c7af11beJohn Criswell//===----------------------------------------------------------------------===// 9a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 10a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// This file describes the target machine instructions to the code generator. 11a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve// 12f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner//===----------------------------------------------------------------------===// 13a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 143501feab811c86c9659248a4875fc31a3165f84dChris Lattner#ifndef LLVM_TARGET_TARGETINSTRINFO_H 153501feab811c86c9659248a4875fc31a3165f84dChris Lattner#define LLVM_TARGET_TARGETINSTRINFO_H 16a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 17905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos#include "llvm/CodeGen/MachineBasicBlock.h" 186c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng#include "llvm/CodeGen/MachineFunction.h" 19551ccae044b0ff658fe629dd67edd5ffe75d10e8Reid Spencer#include "llvm/Support/DataTypes.h" 202cc214c06cbb94f95928636981c9805d6300cff1Chris Lattner#include <vector> 21be67780f31958b05ad3c510ca3a973d327517e86Chris Lattner#include <cassert> 22a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 23d0fde30ce850b78371fd1386338350591f9ff494Brian Gaekenamespace llvm { 24d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 255684c4e2b41f1d6ddf70b116a84f438040f66297Vikram S. Adveclass MachineInstr; 26f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattnerclass TargetMachine; 27ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetRegisterClass; 286c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengclass LiveVariables; 29a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 30f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 31f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner// Data types used to define information about a single machine instruction 32f3aaadf48277acddc3f6fdc4cc8d18b13d313595Chris Lattner//--------------------------------------------------------------------------- 33a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 34ab8672c8bb83e722b856eac67863542ea7e0cbb2Alkis Evlogimenostypedef short MachineOpCode; 35c188b733babbcdb0ff51613d0bb133e0496963b6Chris Lattnertypedef unsigned InstrSchedClass; 36a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 37a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve//--------------------------------------------------------------------------- 383501feab811c86c9659248a4875fc31a3165f84dChris Lattner// struct TargetInstrDescriptor: 3900876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Predefined information about each machine instruction. 4000876a2808f1a8061f7e0852c7949fc5074ecb04Misha Brukman// Designed to initialized statically. 413501feab811c86c9659248a4875fc31a3165f84dChris Lattner// 42a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 43f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BRANCH_FLAG = 1 << 0; 44f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_CALL_FLAG = 1 << 1; 45f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_RET_FLAG = 1 << 2; 46f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_BARRIER_FLAG = 1 << 3; 47f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_DELAY_SLOT_FLAG = 1 << 4; 48f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_LOAD_FLAG = 1 << 5; 49f7fb31ea33c78f1bc46c23d9edbf9580b7756bbeChris Lattnerconst unsigned M_STORE_FLAG = 1 << 6; 5020ab29068d8a8ec31f26f022634f1e0bc4b1da56Owen Andersonconst unsigned M_INDIRECT_FLAG = 1 << 7; 516e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_IMPLICIT_DEF_FLAG = 1 << 8; 5215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 53a1fd6504aaf62b87530e8230517957bad3facc96Evan Cheng// M_CONVERTIBLE_TO_3_ADDR - This is a 2-address instruction which can be 5415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// changed into a 3-address instruction if the first two operands cannot be 5515f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// assigned to the same register. The target must implement the 5615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// TargetInstrInfo::convertToThreeAddress method for this instruction. 576e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_CONVERTIBLE_TO_3_ADDR = 1 << 9; 5815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 5915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// This M_COMMUTABLE - is a 2- or 3-address instruction (of the form X = op Y, 6015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner// Z), which produces the same result if Y and Z are exchanged. 616e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_COMMUTABLE = 1 << 10; 62a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 63075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic 64075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// block? Typically this is things like return and branch instructions. 65075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// Various passes use this to insert code into the bottom of a basic block, but 66075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner// before control flow occurs. 676e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_TERMINATOR_FLAG = 1 << 11; 68075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner 6909321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// M_USES_CUSTOM_DAG_SCHED_INSERTION - Set if this instruction requires custom 7009321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// insertion support when the DAG scheduler is inserting it into a machine basic 7109321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner// block. 726e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_USES_CUSTOM_DAG_SCHED_INSERTION = 1 << 12; 7309321dcf5a3d8acb89dfcad2191c630a54938458Chris Lattner 748d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// M_VARIABLE_OPS - Set if this instruction can have a variable number of extra 758d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng// operands in addition to the minimum number operands specified. 766e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_VARIABLE_OPS = 1 << 13; 778d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 781bccb49082a8049d296dcdb2a741929437b6176fEvan Cheng// M_PREDICABLE - Set if this instruction has a predicate operand that 791bccb49082a8049d296dcdb2a741929437b6176fEvan Cheng// controls execution. It may be set to 'always'. 806e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_PREDICABLE = 1 << 14; 811b1b737d7dc7b3330331cf65514719d719f88a43Chris Lattner 82d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman// M_REMATERIALIZIBLE - Set if this instruction can be trivally re-materialized 83d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman// at any time, e.g. constant generation, load from constant pool. 846e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_REMATERIALIZIBLE = 1 << 15; 85d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 864e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng// M_NOT_DUPLICABLE - Set if this instruction cannot be safely duplicated. 874e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng// (e.g. instructions with unique labels attached). 886e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_NOT_DUPLICABLE = 1 << 16; 89ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 90ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng// M_HAS_OPTIONAL_DEF - Set if this instruction has an optional definition, e.g. 91ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng// ARM instructions which can set condition code if 's' bit is set. 926e141fd04897e5eb4925bb6351297170ebd8a756Evan Chengconst unsigned M_HAS_OPTIONAL_DEF = 1 << 17; 934e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 947d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// M_NEVER_HAS_SIDE_EFFECTS - Set if this instruction has no side effects that 957d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// are not captured by any operands of the instruction or other flags, and when 967d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// *all* instances of the instruction of that opcode have no side effects. 977d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// 987d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// Note: This and M_MAY_HAVE_SIDE_EFFECTS are mutually exclusive. You can't set 997d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// both! If neither flag is set, then the instruction *always* has side effects. 1007d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendlingconst unsigned M_NEVER_HAS_SIDE_EFFECTS = 1 << 18; 1017d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling 1027d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// M_MAY_HAVE_SIDE_EFFECTS - Set if some instances of this instruction can have 1037d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// side effects. The virtual method "isReallySideEffectFree" is called to 1047d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// determine this. Load instructions are an example of where this is useful. In 1057d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// general, loads always have side effects. However, loads from constant pools 1067d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// don't. We let the specific back end make this determination. 1077d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// 1087d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// Note: This and M_NEVER_HAS_SIDE_EFFECTS are mutually exclusive. You can't set 1097d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling// both! If neither flag is set, then the instruction *always* has side effects. 1107d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendlingconst unsigned M_MAY_HAVE_SIDE_EFFECTS = 1 << 19; 1116b1da9c39f0731d15cb743441bea6d4089efd9f8Bill Wendling 11221d03f2de0087d60dbf575d95924404a97852879Evan Cheng// Machine operand flags 11321d03f2de0087d60dbf575d95924404a97852879Evan Cheng// M_LOOK_UP_PTR_REG_CLASS - Set if this operand is a pointer value and it 11421d03f2de0087d60dbf575d95924404a97852879Evan Cheng// requires a callback to look up its register class. 11521d03f2de0087d60dbf575d95924404a97852879Evan Chengconst unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0; 11621d03f2de0087d60dbf575d95924404a97852879Evan Cheng 1175de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// M_PREDICATE_OPERAND - Set if this is one of the operands that made up of the 1185de723c1189c596a9c1b90ce4ee90c137f198ad4Evan Cheng/// predicate operand that controls an M_PREDICATED instruction. 119f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattnerconst unsigned M_PREDICATE_OPERAND = 1 << 1; 120f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 121ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng/// M_OPTIONAL_DEF_OPERAND - Set if this operand is a optional def. 122ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng/// 123ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Chengconst unsigned M_OPTIONAL_DEF_OPERAND = 1 << 2; 124ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 1256c14147d934bd644fc9d24a3b36f3c38799a3401Evan Chengnamespace TOI { 1266c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng // Operand constraints: only "tied_to" for now. 1276c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng enum OperandConstraint { 1286c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TIED_TO = 0 // Must be allocated the same register as. 1296c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng }; 1306c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng} 131f6e8e6bace845cbbb6c1f6d859ffd8a3a154222bChris Lattner 132ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// TargetOperandInfo - This holds information about one operand of a machine 133ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// instruction, indicating the register class for register operands, etc. 134ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner/// 135ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerclass TargetOperandInfo { 136ae72f4a642192abab5a2d10592200a94fcba61deChris Lattnerpublic: 13760f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// RegClass - This specifies the register class enumeration of the operand 13860f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey /// if the operand is a register. If not, this contains 0. 13960f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short RegClass; 14060f09928a0d22d5927ff0a40fe9163cf1ba1014aJim Laskey unsigned short Flags; 141e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// Lower 16 bits are used to specify which constraints are set. The higher 16 142e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// bits are used to specify the value of constraints (4 bits each). 143e2ba8975883874633a1035c245af3b948b940b25Evan Cheng unsigned int Constraints; 144ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner /// Currently no other information. 145ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner}; 146ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 147ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner 1481fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerclass TargetInstrDescriptor { 1491fca5ff62bb2ecb5bfc8974f4dbfc56e9d3ca721Chris Lattnerpublic: 15033247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng MachineOpCode Opcode; // The opcode. 15133247d537ddce29e65bc324bf8d40a15d2d88c01Evan Cheng unsigned short numOperands; // Num of args (may be more if variable_ops). 152b5910820ce8608b75cb88e6c4efd2d1a5858159aEvan Cheng unsigned short numDefs; // Num of args that are definitions. 1534683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner const char * Name; // Assembly language mnemonic for the opcode. 15475e961ae6b2e2801160e560057ad97ece4443986Chris Lattner InstrSchedClass schedClass; // enum identifying instr sched class 15575e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned Flags; // flags identifying machine instr class 15675e961ae6b2e2801160e560057ad97ece4443986Chris Lattner unsigned TSFlags; // Target Specific Flag values 157f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitUses; // Registers implicitly read by this instr 158f6d12fbd9cc0355978a739f5ab213eff85b75a19Chris Lattner const unsigned *ImplicitDefs; // Registers implicitly defined by this instr 159ae72f4a642192abab5a2d10592200a94fcba61deChris Lattner const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands. 1606c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng 1616c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 1626c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// it is set. Returns -1 if it is not set. 1636c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng int getOperandConstraint(unsigned OpNum, 1646c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 165f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng assert((OpNum < numOperands || (Flags & M_VARIABLE_OPS)) && 166f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng "Invalid operand # of TargetInstrInfo"); 167f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng if (OpNum < numOperands && 168f2f6a1baf78f3bdf375b258996abd567c20496bcEvan Cheng (OpInfo[OpNum].Constraints & (1 << Constraint))) { 1696c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng unsigned Pos = 16 + Constraint * 4; 1706c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; 1716c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 1726c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return -1; 1736c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng } 174cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng 175cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// findTiedToSrcOperand - Returns the operand that is tied to the specified 176cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng /// dest operand. Returns -1 if there isn't one. 177cc22a7a2adfea3fc318a6d8ca0c692a8e892105bEvan Cheng int findTiedToSrcOperand(unsigned OpNum) const; 178a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 179a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 180a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 1813501feab811c86c9659248a4875fc31a3165f84dChris Lattner//--------------------------------------------------------------------------- 18234695381d626485a560594f162701088079589dfMisha Brukman/// 1833501feab811c86c9659248a4875fc31a3165f84dChris Lattner/// TargetInstrInfo - Interface to description of machine instructions 18434695381d626485a560594f162701088079589dfMisha Brukman/// 185075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattnerclass TargetInstrInfo { 186075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner const TargetInstrDescriptor* desc; // raw array to allow static init'n 187bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned NumOpcodes; // number of entries in the desc array 188075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner unsigned numRealOpCodes; // number of non-dummy op codes 18934695381d626485a560594f162701088079589dfMisha Brukman 190075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT 191075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT 192a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Advepublic: 193bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes); 194075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner virtual ~TargetInstrInfo(); 19570535c608d88ce25fb992dba3b6d3d0176153a09Chris Lattner 1964ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner // Invariant opcodes: All instruction sets have these as their low opcodes. 1974ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner enum { 1984ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner PHI = 0, 1991ee29257428960fede862fcfdbe80d5d007927e9Jim Laskey INLINEASM = 1, 20008d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb LABEL = 2, 20108d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb EXTRACT_SUBREG = 3, 20208d52071bae2f8cc2e9aa6a451118b83d043813bChristopher Lamb INSERT_SUBREG = 4 2034ed88eb8229848cd6add06a1ec90e497e382306fChris Lattner }; 20434695381d626485a560594f162701088079589dfMisha Brukman 205bceb68807fdb86c794bc8d8f8aef0940f12c2cebChris Lattner unsigned getNumOpcodes() const { return NumOpcodes; } 20634695381d626485a560594f162701088079589dfMisha Brukman 207e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// get - Return the machine instruction descriptor that corresponds to the 208e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// specified instruction opcode. 209e30eeaaf72b461aebf3dfcdd7c119eea76458561Chris Lattner /// 2102441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const TargetInstrDescriptor& get(MachineOpCode Opcode) const { 2112441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner assert((unsigned)Opcode < NumOpcodes); 2122441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return desc[Opcode]; 213a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 2144683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner 2152441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const char *getName(MachineOpCode Opcode) const { 2162441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Name; 2174683f9bfb4dc2f5557e8a7a229912e7f2ed366caChris Lattner } 21834695381d626485a560594f162701088079589dfMisha Brukman 2192441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner int getNumOperands(MachineOpCode Opcode) const { 2202441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).numOperands; 221a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 222450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 223ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng int getNumDefs(MachineOpCode Opcode) const { 224ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng return get(Opcode).numDefs; 225ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng } 226ffddf97e5dd1fc222cec049c30ca5d9018a741f8Evan Cheng 2272441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner InstrSchedClass getSchedClass(MachineOpCode Opcode) const { 2282441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).schedClass; 229a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 230d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 2312441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitUses(MachineOpCode Opcode) const { 2322441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitUses; 233d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 234d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 2352441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner const unsigned *getImplicitDefs(MachineOpCode Opcode) const { 2362441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).ImplicitDefs; 237d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke } 238d7908f679eeadc108e09e2aca5faba0b5410ea4aBrian Gaeke 239450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 240a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // 241a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // Query instruction class flags according to the machine-independent 242a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve // flags listed above. 24334695381d626485a560594f162701088079589dfMisha Brukman // 2442441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner bool isReturn(MachineOpCode Opcode) const { 2452441d6a895c1aad171bfbdc84cd6e246171b101dChris Lattner return get(Opcode).Flags & M_RET_FLAG; 246a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve } 247450b6d29988fa01e828e5b7917a47726a4dd46ecChris Lattner 24813d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng bool isCommutableInstr(MachineOpCode Opcode) const { 24913d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng return get(Opcode).Flags & M_COMMUTABLE; 25013d41b9d721f98372b97d2ec119e6c91932ab0aeEvan Cheng } 251d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool isTerminatorInstr(MachineOpCode Opcode) const { 252075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner return get(Opcode).Flags & M_TERMINATOR_FLAG; 253075b4a066db31f48e0f6daec34b1ff463523cd3fChris Lattner } 2540271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2550271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBranch(MachineOpCode Opcode) const { 2560271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BRANCH_FLAG; 2570271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2580271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 25920ab29068d8a8ec31f26f022634f1e0bc4b1da56Owen Anderson bool isIndirectBranch(MachineOpCode Opcode) const { 26020ab29068d8a8ec31f26f022634f1e0bc4b1da56Owen Anderson return get(Opcode).Flags & M_INDIRECT_FLAG; 26120ab29068d8a8ec31f26f022634f1e0bc4b1da56Owen Anderson } 26220ab29068d8a8ec31f26f022634f1e0bc4b1da56Owen Anderson 2630271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// isBarrier - Returns true if the specified instruction stops control flow 2640271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// from executing the instruction immediately following it. Examples include 2650271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// unconditional branches and return instructions. 2660271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isBarrier(MachineOpCode Opcode) const { 2670271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_BARRIER_FLAG; 2680271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2690271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 2700271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isCall(MachineOpCode Opcode) const { 2710271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_CALL_FLAG; 2720271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2730271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isLoad(MachineOpCode Opcode) const { 2740271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_LOAD_FLAG; 2750271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2760271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner bool isStore(MachineOpCode Opcode) const { 2770271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_STORE_FLAG; 2780271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 2790271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 280b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// hasDelaySlot - Returns true if the specified instruction has a delay slot 281b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// which must be filled by the code generator. 282d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool hasDelaySlot(MachineOpCode Opcode) const { 283b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return get(Opcode).Flags & M_DELAY_SLOT_FLAG; 284b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 285b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 2860271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// usesCustomDAGSchedInsertionHook - Return true if this instruction requires 2870271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// custom insertion support when the DAG scheduler is inserting it into a 2880271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner /// machine basic block. 289d46a8ea5d5383c16554a86105a43f63fa3786efbEvan Cheng bool usesCustomDAGSchedInsertionHook(MachineOpCode Opcode) const { 2900271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner return get(Opcode).Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION; 2910271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner } 292d55697cf136150b697b9bbddce9088e87a1be963Vikram S. Adve 2938d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng bool hasVariableOperands(MachineOpCode Opcode) const { 2948d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng return get(Opcode).Flags & M_VARIABLE_OPS; 2958d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng } 2968d3af5e7d082dbd029c3987ceadbdcf9e49af6d7Evan Cheng 2974e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng bool isPredicable(MachineOpCode Opcode) const { 2984e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng return get(Opcode).Flags & M_PREDICABLE; 2994e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng } 3004e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 3014e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng bool isNotDuplicable(MachineOpCode Opcode) const { 3024e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng return get(Opcode).Flags & M_NOT_DUPLICABLE; 3034e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng } 3044e6b1e1d999a224d932c466118aad577f27cdd56Evan Cheng 305ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng bool hasOptionalDef(MachineOpCode Opcode) const { 306ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return get(Opcode).Flags & M_HAS_OPTIONAL_DEF; 307ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 308ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 309041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isTriviallyReMaterializable - Return true if the instruction is trivially 310d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// rematerializable, meaning it has no side effects and requires no operands 311d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman /// that aren't always available. 312041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling bool isTriviallyReMaterializable(MachineInstr *MI) const { 313d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return (MI->getInstrDescriptor()->Flags & M_REMATERIALIZIBLE) && 314041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling isReallyTriviallyReMaterializable(MI); 315d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 316d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 3174be2f7fe57896142ffd81432eab4dc31d21d689bBill Wendling /// hasUnmodelledSideEffects - Returns true if the instruction has side 3184be2f7fe57896142ffd81432eab4dc31d21d689bBill Wendling /// effects that are not captured by any operands of the instruction or other 3194be2f7fe57896142ffd81432eab4dc31d21d689bBill Wendling /// flags. 3204be2f7fe57896142ffd81432eab4dc31d21d689bBill Wendling bool hasUnmodelledSideEffects(MachineInstr *MI) const { 321882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); 322882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling if (!(TID->Flags & M_NEVER_HAS_SIDE_EFFECTS || 323882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling TID->Flags & M_MAY_HAVE_SIDE_EFFECTS)) return true; 324882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling if (TID->Flags & M_NEVER_HAS_SIDE_EFFECTS) return false; 325882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling return !isReallySideEffectFree(MI); // May have side effects 326882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling } 327d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanprotected: 328041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// isReallyTriviallyReMaterializable - For instructions with opcodes for 329041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// which the M_REMATERIALIZABLE flag is set, this function tests whether the 330041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// instruction itself is actually trivially rematerializable, considering 331041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// its operands. This is used for targets that have instructions that are 332041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// only trivially rematerializable for specific uses. This predicate must 333041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// return false if the instruction has any side effects other than 334041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// producing a value, or if it requres any address registers that are not 335041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling /// always available. 336041b3f835682588cb63df7e609d726369dd6b7d3Bill Wendling virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const { 337d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman return true; 338d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman } 339d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohman 3407d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling /// isReallySideEffectFree - If the M_MAY_HAVE_SIDE_EFFECTS flag is set, this 3417d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling /// method is called to determine if the specific instance of this 342882d2914871de826bb0c564c7db8a942f3c44a96Bill Wendling /// instruction has side effects. This is useful in cases of instructions, 3437d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling /// like loads, which generally always have side effects. A load from a 3447d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling /// constant pool doesn't have side effects, though. So we need to 3457d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling /// differentiate it from the general case. 3467d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling virtual bool isReallySideEffectFree(MachineInstr *MI) const { 3477d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling return false; 3487d9e97c2ac6f47473b2cb34971c53db30e5e9c27Bill Wendling } 349d45eddd214061bf12ad1e6b86497a41725e61d75Dan Gohmanpublic: 350e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// getOperandConstraint - Returns the value of the specific constraint if 351e2ba8975883874633a1035c245af3b948b940b25Evan Cheng /// it is set. Returns -1 if it is not set. 352e2ba8975883874633a1035c245af3b948b940b25Evan Cheng int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum, 3536c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng TOI::OperandConstraint Constraint) const { 3546c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng return get(Opcode).getOperandConstraint(OpNum, Constraint); 355e2ba8975883874633a1035c245af3b948b940b25Evan Cheng } 356e2ba8975883874633a1035c245af3b948b940b25Evan Cheng 3570cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// Return true if the instruction is a register to register move 3580cad9f53b15b7308e977864d681f710646e7d376Alkis Evlogimenos /// and leave the source and dest operands in the passed parameters. 3595e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos virtual bool isMoveInstr(const MachineInstr& MI, 3605e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& sourceReg, 3615e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos unsigned& destReg) const { 3625e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos return false; 3635e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos } 364af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 365af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isLoadFromStackSlot - If the specified machine instruction is a direct 366af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// load from a stack slot, return the virtual or physical register number of 367af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the destination along with the FrameIndex of the loaded stack slot. If 368af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 369af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than loading from the stack slot. 370af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ 371af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 372af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 373af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner 374af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// isStoreToStackSlot - If the specified machine instruction is a direct 375af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// store to a stack slot, return the virtual or physical register number of 376af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// the source reg along with the FrameIndex of the loaded stack slot. If 377af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// not, return 0. This predicate must return 0 if the instruction has 378af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner /// any side effects other than storing to the stack slot. 379af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { 380af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner return 0; 381af9fa2bd0c1ee25f3adda96b3e5d7129fbab393aChris Lattner } 3825e30002af70ef09a42cac155d9196f7f0f3b1695Alkis Evlogimenos 38315f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// convertToThreeAddress - This method must be implemented by targets that 38415f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 3852c8c3e2e31e641085060edce0ddde3833ffa53daDan Gohman /// may be able to convert a two-address instruction into one or more true 3866c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// three-address instructions on demand. This allows the X86 target (for 38715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// example) to convert ADD and SHL instructions into LEA instructions if they 38815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// would require register copies due to two-addressness. 38915f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 39015f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// This method returns a null pointer if the transformation cannot be 3916c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng /// performed, otherwise it returns the last new instruction. 39215f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner /// 3936c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng virtual MachineInstr * 3946c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng convertToThreeAddress(MachineFunction::iterator &MFI, 3956c14147d934bd644fc9d24a3b36f3c38799a3401Evan Cheng MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const { 39615f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner return 0; 39715f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner } 39815f63ad2e59998f0bf1a3a23547582074391f650Chris Lattner 399d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// commuteInstruction - If a target has any instructions that are commutable, 400d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// but require converting to a different instruction or making non-trivial 401d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// changes to commute them, this method can overloaded to do this. The 402d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// default implementation of this method simply swaps the first two operands 403d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// of MI and returns it. 404d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 405d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// If a target wants to make more aggressive changes, they can construct and 406d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// return a new machine instruction. If an instruction cannot commute, it 407d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// can also return null. 408d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner /// 409641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0; 410d7e2fe40e42dffa04a770191c3414446d5e8c30aChris Lattner 411b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning 412b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 413b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// implemented for a target). Upon success, this returns false and returns 414b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// with the following information in various cases: 415b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 41672dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 1. If this block ends with no branches (it just falls through to its succ) 41772dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// just return false, leaving TBB/FBB null. 41872dc5852684bd56af68b3f344b295d9ff5c3a13fChris Lattner /// 2. If this block ends with only an unconditional branch, it sets TBB to be 419b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// the destination block. 4206c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 3. If this block ends with an conditional branch and it falls through to 4216c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// an successor block, it sets TBB to be the branch destination block and a 4226c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// list of operands that evaluate the condition. These 4236c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 4246c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 4256c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// 4. If this block ends with an conditional branch and an unconditional 4266c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// block, it returns the 'true' destination in TBB, the 'false' destination 4276c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// in FBB, and a list of operands that evaluate the condition. These 4286c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// operands can be passed to other TargetInstrInfo methods to create new 4296c1d2b90e31ea3337705372d1757727d6764686dEvan Cheng /// branches. 430b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 431b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// Note that RemoveBranch and InsertBranch must be implemented to support 432b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// cases where this method returns success. 433b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// 434b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 435b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner MachineBasicBlock *&FBB, 436b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner std::vector<MachineOperand> &Cond) const { 437b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner return true; 438905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 439b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 440b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// RemoveBranch - Remove the branching code at the end of the specific MBB. 441b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// this is only invoked in cases where AnalyzeBranch returns success. It 442b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// returns the number of instructions that were removed. 443b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const { 444b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!"); 445b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 446b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 447b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 448b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// InsertBranch - Insert a branch into the end of the specified 449b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner /// MachineBasicBlock. This operands to this method are the same as those 45033644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch 45133644ba8d22a91b8fe0f0da3d73fc7cf38a46b06Chris Lattner /// returns success and when an unconditional branch (TBB is non-null, FBB is 452b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// null, Cond is empty) needs to be inserted. It returns the number of 453b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng /// instructions inserted. 454b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 455d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner MachineBasicBlock *FBB, 456d51c87f22f9b666204b27b301af771bc5badc142Chris Lattner const std::vector<MachineOperand> &Cond) const { 45724321d7e23a482cbd0b7502f43e9026f87a3684dRafael Espindola assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!"); 458b5cdaa257e167a08a8a54ea9249d847ccc415ce0Evan Cheng return 0; 459b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner } 460b2cd26127973b97c3ed8d74a063e70a259369e44Chris Lattner 461d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson /// copyRegToReg - Add a copy between a pair of registers 462d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson virtual void copyRegToReg(MachineBasicBlock &MBB, 463d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator MI, 464d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 465d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 466d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 467d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!"); 468d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 469d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 470c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// BlockHasNoFallThrough - Return true if the specified block does not 471c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// fall-through into its successor block. This is primarily used when a 472c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// branch is unanalyzable. It is useful for things like unconditional 473c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner /// indirect branches (jump tables). 474c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 475c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner return false; 476c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner } 477c24ff8ed12d01a1b1d2fac57876fc7580024ec49Chris Lattner 4785f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// ReverseBranchCondition - Reverses the branch condition of the specified 4795f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// condition list, returning false on success and true if it cannot be 4805f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner /// reversed. 4815f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 4825f1e4dbdf77de6887441af20857967a3d24c01abChris Lattner return true; 483905f7af59cb85ea71b6c011f1e79f24f8db16efcAlkis Evlogimenos } 4840271077eba5f62796f4c725baa8e7fc88bf97650Chris Lattner 48565e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// insertNoop - Insert a noop into the instruction stream at the specified 48665e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner /// point. 48765e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner virtual void insertNoop(MachineBasicBlock &MBB, 48865e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner MachineBasicBlock::iterator MI) const { 48965e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner assert(0 && "Target didn't implement insertNoop!"); 49065e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner abort(); 49165e9f3969bec427f14d41f0aaef12ed689ca85b5Chris Lattner } 49221d03f2de0087d60dbf575d95924404a97852879Evan Cheng 493bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isPredicated - Returns true if the instruction is already predicated. 4944f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// 495f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual bool isPredicated(const MachineInstr *MI) const { 4964f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 4974f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 4984f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 499bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// isUnpredicatedTerminator - Returns true if the instruction is a 500bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// terminator instruction that has not been predicated. 501318093b6f8d21ac8eab34573b0526984895fe941Dale Johannesen virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const; 502bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng 5030402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng /// PredicateInstruction - Convert the instruction into a predicated 50402c602b333ed2a1a13a17981f3c3f2f5463d5e5cEvan Cheng /// instruction. It returns true if the operation was successful. 505f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 506f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool PredicateInstruction(MachineInstr *MI, 507641055225092833197efe8e5bce01d50bcf1daaeChris Lattner const std::vector<MachineOperand> &Pred) const = 0; 5084f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng 509bfd2ec4a8ef51ebe982363a7e8d7156fdb3827d8Evan Cheng /// SubsumesPredicate - Returns true if the first specified predicate 5104f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng /// subsumes the second, e.g. GE subsumes GT. 511f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng virtual 512f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1, 513f277ee4be7edabb759a7f78138b693d72d0c263fEvan Cheng const std::vector<MachineOperand> &Pred2) const { 5144f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng return false; 5154f85cd77046d76bd9091aa6caa06e767bd22f64cEvan Cheng } 5160402e170e8058cc5256e0c7b94ae37484253d73dEvan Cheng 517ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// DefinesPredicate - If the specified instruction defines any predicate 518ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// or condition code register(s) used for predication, returns true as well 519ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng /// as the definition predicate(s) by reference. 520ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng virtual bool DefinesPredicate(MachineInstr *MI, 521ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng std::vector<MachineOperand> &Pred) const { 522ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng return false; 523ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng } 524ed80ef6089ef83bd1c79f1477d7a12a949474af5Evan Cheng 52521d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// getPointerRegClass - Returns a TargetRegisterClass used for pointer 52621d03f2de0087d60dbf575d95924404a97852879Evan Cheng /// values. 52721d03f2de0087d60dbf575d95924404a97852879Evan Cheng virtual const TargetRegisterClass *getPointerRegClass() const { 52821d03f2de0087d60dbf575d95924404a97852879Evan Cheng assert(0 && "Target didn't implement getPointerRegClass!"); 52921d03f2de0087d60dbf575d95924404a97852879Evan Cheng abort(); 530fb062ece96092e70a835c0d462613b07228d60a3Jeff Cohen return 0; // Must return a value in order to compile with VS 2005 53121d03f2de0087d60dbf575d95924404a97852879Evan Cheng } 532a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve}; 533a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve 534641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfoImpl - This is the default implementation of 535641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// TargetInstrInfo, which just provides a couple of default implementations 536641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// for various methods. This separated out because it is implemented in 537641055225092833197efe8e5bce01d50bcf1daaeChris Lattner/// libcodegen, not in libtarget. 538641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerclass TargetInstrInfoImpl : public TargetInstrInfo { 539641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerprotected: 540641055225092833197efe8e5bce01d50bcf1daaeChris Lattner TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes) 541641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfo(desc, NumOpcodes) {} 542641055225092833197efe8e5bce01d50bcf1daaeChris Lattnerpublic: 543641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; 544641055225092833197efe8e5bce01d50bcf1daaeChris Lattner virtual bool PredicateInstruction(MachineInstr *MI, 545641055225092833197efe8e5bce01d50bcf1daaeChris Lattner const std::vector<MachineOperand> &Pred) const; 546641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 547641055225092833197efe8e5bce01d50bcf1daaeChris Lattner}; 548641055225092833197efe8e5bce01d50bcf1daaeChris Lattner 549d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke} // End llvm namespace 550d0fde30ce850b78371fd1386338350591f9ff494Brian Gaeke 551a578a6d054e8219c730840700d8d5fd29f15a962Vikram S. Adve#endif 552